superrob1500
/
mirror-linux
mirror of https://github.com/torvalds/linux
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Pin control fixes for the v7.1 kernel: 

- Implement the GPIO .get_direction() callback in the Mediatek
   driver to rid dmesg warnings.
 
 - Mark the Qualcomm IPQ4019 pins used as GPIO as using the
   GPIO pin function, so there is no conflict with orthogonal
   muxing.
 
 - Fix incorrect settings of the "PUPD" (pull-up-pull-down)
   register during suspend/resume in the Renesas RZG2L.
 
 - Fix the SMT register cache to be per-bank in the Renesas
   RZG2L.
 
 - Fix the QDSS track clock and control pin group names in the
   Qualcomm Eliza driver.
 
 - Fix a deadlock in the Amlogic driver, caused by playing
   around in sysfs.
 
 - Fix some GPIO wakeup interrupt handling in Qualcomm QCS615.
   and a similar fix for the Qualcomm SM8150.
 
 - Allow parsing DTs without explicit function nodes in the
   Freescale i.MX1 driver.
 
 - Enable the IRQ for the WACF2200 touchscreen using a DMI
   quirk.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmoQdtwACgkQQRCzN7AZ
 XXMAIQ/+KsiMLrdx7/5hapLHAPj2p4ZznO9Tvw0q2JQD4S93AqLosg5njUsyDlCn
 D8mfPx3td7lQX6GbypfnFkppJU7I/wr5UjYn8iouRDVKJSN1zdUXRRylOU9DYpnq
 a7DNR+ScVfxTtNeLFB9XhB5RzxVmkERjVNzan+T+BmHa1M4eUoIBkrwWGV4U9b4d
 2296ESnzKH2mtfbkeh9L1x70705kzWR15hhn2xwHsNwtg/8z7oGxCeZTnbEseuam
 QBzD2sfKVf7+uj4QItIuzyr//RfIVcOsWuxB/jZhgh3ob2plp5T362pV0QOA1706
 TvGYSGyMhz/BobIDKtg7g3q0i5XJpHalA8RRjhY8jWduUymYPti7SUDuhetN/MMK
 z7qiAqzUwvXY5KadVza2P6lu+PKliusdqFSoF5AooC7JwFXGJrCSxno+oR/AzByg
 SuwQt3wBFM/Ik1qtmdt0EL0J3euxCoivPrzTAWyBsY4YoTsGnUXEUn/vAIA7CfIQ
 SjD2XvNJ2okZfWQKfl6pNdpyM/Y9UTNA3wN7qoAfvo0f4Zxyy5eqYfim9FWpgwQ+
 Bchx+CcXc9iEuc9Ja3zzikkR2IVE5AcLlFtPmiKK3nkqhO6MiU+1kzsDk8jT2Bt1
 PYNkIWZjMRZq3Ya56JCOHlxTPAWBG5mXLP1YEz3MwUVVSe+wGwI=
 =bMLM
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v7.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:

 - Implement the GPIO .get_direction() callback in the Mediatek driver
   to rid dmesg warnings

 - Mark the Qualcomm IPQ4019 pins used as GPIO as using the GPIO pin
   function, so there is no conflict with orthogonal muxing

 - Fix incorrect settings of the "PUPD" (pull-up-pull-down) register
   during suspend/resume in the Renesas RZG2L

 - Fix the SMT register cache to be per-bank in the Renesas RZG2L

 - Fix the QDSS track clock and control pin group names in the Qualcomm
   Eliza driver

 - Fix a deadlock in the Amlogic driver, caused by playing around in
   sysfs

 - Fix some GPIO wakeup interrupt handling in Qualcomm QCS615. and a
   similar fix for the Qualcomm SM8150

 - Allow parsing DTs without explicit function nodes in the Freescale
   i.MX1 driver

 - Enable the IRQ for the WACF2200 touchscreen using a DMI quirk

* tag 'pinctrl-v7.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl-amd: enable IRQ for WACF2200 touchscreen on Lenovo Yoga 7 14AGP11
  pinctrl: imx1: Allow parsing DT without function nodes
  pinctrl: qcom: Fix wakeirq map by removing disconnected irqs for sm8150
  pinctrl: qcom: Fix GPIO to PDC wake irq map for qcs615
  pinctrl: meson: amlogic-a4: fix deadlock issue
  pinctrl: qcom: eliza: Fix QDSS trace clock/control pingroup names
  pinctrl: renesas: rzg2l: Fix SMT register cache handling
  pinctrl: renesas: rzg2l: Fix incorrect PUPD register offset for high pins during suspend/resume
  pinctrl: qcom: ipq4019: mark gpio as a GPIO pin function
  pinctrl: mediatek: moore: implement gpio_chip::get_direction()
master
Linus Torvalds 2026-05-22 12:33:28 -07:00
parent 99e08debac 3812a9e842
commit 003759d49a
10 changed files with 129 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
drivers/pinctrl/freescale/pinctrl-imx1-core.c
View File

@ -540,10 +540,34 @@ static int imx1_pinctrl_parse_functions(struct device_node *np,
return 0;
}
/*
* Check if the DT contains pins in the direct child nodes. This indicates the
* newer DT format to store pins. This function returns true if the first found
* fsl,pins property is in a child of np. Otherwise false is returned.
*/
static bool imx1_pinctrl_dt_is_flat_functions(struct device_node *np)
{
struct device_node *function_np;
struct device_node *pinctrl_np;
for_each_child_of_node(np, function_np) {
if (of_property_present(function_np, "fsl,pins"))
return true;
for_each_child_of_node(function_np, pinctrl_np) {
if (of_property_present(pinctrl_np, "fsl,pins"))
return false;
}
}
return true;
}
static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info)
{
struct device_node *np = pdev->dev.of_node;
bool flat_funcs;
int ret;
u32 nfuncs = 0;
u32 ngroups = 0;
@ -552,9 +576,15 @@ static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
if (!np)
return -ENODEV;
for_each_child_of_node_scoped(np, child) {
++nfuncs;
ngroups += of_get_child_count(child);
flat_funcs = imx1_pinctrl_dt_is_flat_functions(np);
if (flat_funcs) {
nfuncs = 1;
ngroups = of_get_child_count(np);
} else {
for_each_child_of_node_scoped(np, child) {
++nfuncs;
ngroups += of_get_child_count(child);
}
}
if (!nfuncs) {
@ -574,10 +604,14 @@ static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
if (!info->functions || !info->groups)
return -ENOMEM;
for_each_child_of_node_scoped(np, child) {
ret = imx1_pinctrl_parse_functions(child, info, ifunc++);
if (ret == -ENOMEM)
return -ENOMEM;
if (flat_funcs) {
imx1_pinctrl_parse_functions(np, info, 0);
} else {
for_each_child_of_node_scoped(np, child) {
ret = imx1_pinctrl_parse_functions(child, info, ifunc++);
if (ret == -ENOMEM)
return -ENOMEM;
}
}
return 0;

18
drivers/pinctrl/mediatek/pinctrl-moore.c
View File

@ -520,6 +520,23 @@ static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
return pinctrl_gpio_direction_output(chip, gpio);
}
static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
int ret, dir;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
if (!desc->name)
return -ENOTSUPP;
ret = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &dir);
if (ret)
return ret;
return dir ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
}
static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
@ -566,6 +583,7 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw)
chip->parent = hw->dev;
chip->request = gpiochip_generic_request;
chip->free = gpiochip_generic_free;
chip->get_direction = mtk_gpio_get_direction;
chip->direction_input = pinctrl_gpio_direction_input;
chip->direction_output = mtk_gpio_direction_output;
chip->get = mtk_gpio_get;

6
drivers/pinctrl/meson/pinctrl-amlogic-a4.c
View File

@ -292,7 +292,7 @@ static int aml_calc_reg_and_bit(struct pinctrl_gpio_range *range,
static int aml_pinconf_get_pull(struct aml_pinctrl *info, unsigned int pin)
{
struct pinctrl_gpio_range *range =
pinctrl_find_gpio_range_from_pin(info->pctl, pin);
pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin);
struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);
unsigned int reg, bit, val;
int ret, conf;
@ -326,7 +326,7 @@ static int aml_pinconf_get_drive_strength(struct aml_pinctrl *info,
u16 *drive_strength_ua)
{
struct pinctrl_gpio_range *range =
pinctrl_find_gpio_range_from_pin(info->pctl, pin);
pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin);
struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);
unsigned int reg, bit;
unsigned int val;
@ -365,7 +365,7 @@ static int aml_pinconf_get_gpio_bit(struct aml_pinctrl *info,
unsigned int reg_type)
{
struct pinctrl_gpio_range *range =
pinctrl_find_gpio_range_from_pin(info->pctl, pin);
pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin);
struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);
unsigned int reg, bit, val;
int ret;

35
drivers/pinctrl/pinctrl-amd.c
View File

@ -26,6 +26,7 @@
#include <linux/interrupt.h>
#include <linux/bitops.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/dmi.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/string_choices.h>
@ -39,6 +40,39 @@
static struct amd_gpio *pinctrl_dev;
#endif
static const struct dmi_system_id amd_gpio_quirk_yoga7_14agp11[] = {
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "83TD"),
DMI_MATCH(DMI_BOARD_NAME, "LNVNB161216"),
},
},
{ }
};
static void amd_gpio_apply_quirks(struct amd_gpio *gpio_dev)
{
const unsigned int pin = 157; /* WACF2200 GpioInt per ACPI _CRS */
unsigned long flags;
u32 reg;
if (!dmi_check_system(amd_gpio_quirk_yoga7_14agp11))
return;
if (pin >= gpio_dev->gc.ngpio)
return;
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
reg = readl(gpio_dev->base + pin * 4);
reg |= BIT(INTERRUPT_ENABLE_OFF) | BIT(INTERRUPT_MASK_OFF);
writel(reg, gpio_dev->base + pin * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dev_info(&gpio_dev->pdev->dev,
"Enabled IRQ for GPIO %u (Yoga 7 14AGP11 touchscreen)\n",
pin);
}
static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
{
unsigned long flags;
@ -1219,6 +1253,7 @@ static int amd_gpio_probe(struct platform_device *pdev)
/* Disable and mask interrupts */
amd_gpio_irq_init(gpio_dev);
amd_gpio_apply_quirks(gpio_dev);
girq = &gpio_dev->gc.irq;
gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip);

8
drivers/pinctrl/qcom/pinctrl-eliza.c
View File

@ -1340,7 +1340,7 @@ static const struct msm_pingroup eliza_groups[] = {
[51] = PINGROUP(51, _, _, _, _, _, _, _, _, _, _, _),
[52] = PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2, ddr_bist_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _),
[53] = PINGROUP(53, qup1_se2, qup1_se2, gcc_gp1, ddr_bist_stop, _, qdss_gpio_tracedata, _, _, _, _, _),
[54] = PINGROUP(54, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _),
[54] = PINGROUP(54, qup1_se2, qup1_se6, qdss_gpio_traceclk, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _),
[55] = PINGROUP(55, qup1_se2, dp0_hot, qup1_se6, _, gnss_adc0, atest_usb, ddr_pxi0, _, _, _, _),
[56] = PINGROUP(56, usb0_hs, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, _, _, _, _, _, _),
[57] = PINGROUP(57, sd_write_protect, _, _, _, _, _, _, _, _, _, _),
@ -1358,7 +1358,7 @@ static const struct msm_pingroup eliza_groups[] = {
[69] = PINGROUP(69, cam_mclk, audio_ext_mclk0, resout_gpio, prng_rosc1, _, _, _, _, _, _, _),
[70] = PINGROUP(70, cci_i2c_sda, tmess_prng2, _, phase_flag, atest_char, _, _, _, _, _, _),
[71] = PINGROUP(71, cci_i2c_scl, tmess_prng3, _, phase_flag, atest_char, _, _, _, _, _, _),
[72] = PINGROUP(72, cci_i2c_sda, tmess_prng1, qdss_gpio_tracedata, atest_char, _, _, _, _, _, _, _),
[72] = PINGROUP(72, cci_i2c_sda, tmess_prng1, qdss_gpio_tracectl, atest_char, _, _, _, _, _, _, _),
[73] = PINGROUP(73, cci_i2c_scl, tmess_prng0, qdss_cti, atest_char, _, _, _, _, _, _, _),
[74] = PINGROUP(74, cci_i2c_sda, prng_rosc3, qdss_cti, atest_char, _, _, _, _, _, _, _),
[75] = PINGROUP(75, cci_i2c_scl, _, phase_flag, _, _, _, _, _, _, _, _),
@ -1430,10 +1430,10 @@ static const struct msm_pingroup eliza_groups[] = {
[141] = PINGROUP(141, _, _, _, _, _, _, _, _, _, _, egpio),
[142] = PINGROUP(142, _, _, _, _, _, _, _, _, _, _, egpio),
[143] = PINGROUP(143, _, _, _, _, _, _, _, _, _, _, egpio),
[144] = PINGROUP(144, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, egpio),
[144] = PINGROUP(144, _, qdss_gpio_tracectl, _, _, _, _, _, _, _, _, egpio),
[145] = PINGROUP(145, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, _, egpio),
[146] = PINGROUP(146, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, egpio),
[147] = PINGROUP(147, ddr_bist_fail, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),
[147] = PINGROUP(147, ddr_bist_fail, _, qdss_gpio_traceclk, _, _, _, _, _, _, _, egpio),
[148] = PINGROUP(148, _, _, _, _, _, _, _, _, _, _, egpio),
[149] = PINGROUP(149, _, _, _, _, _, _, _, _, _, _, egpio),
[150] = PINGROUP(150, _, _, _, _, _, _, _, _, _, _, egpio),

2
drivers/pinctrl/qcom/pinctrl-ipq4019.c
View File

@ -479,7 +479,7 @@ static const struct pinfunction ipq4019_functions[] = {
QCA_PIN_FUNCTION(blsp_uart0),
QCA_PIN_FUNCTION(blsp_uart1),
QCA_PIN_FUNCTION(chip_rst),
QCA_PIN_FUNCTION(gpio),
QCA_GPIO_PIN_FUNCTION(gpio),
QCA_PIN_FUNCTION(i2s_rx),
QCA_PIN_FUNCTION(i2s_spdif_in),
QCA_PIN_FUNCTION(i2s_spdif_out),

5
drivers/pinctrl/qcom/pinctrl-msm.h
View File

@ -39,6 +39,11 @@ struct pinctrl_pin_desc;
fname##_groups, \
ARRAY_SIZE(fname##_groups))
#define QCA_GPIO_PIN_FUNCTION(fname) \
[qca_mux_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \
fname##_groups, \
ARRAY_SIZE(fname##_groups))
/**
* struct msm_pingroup - Qualcomm pingroup definition
* @grp: Generic data of the pin group (name and pins)

6
drivers/pinctrl/qcom/pinctrl-qcs615.c
View File

@ -1040,11 +1040,11 @@ static const struct msm_pingroup qcs615_groups[] = {
static const struct msm_gpio_wakeirq_map qcs615_pdc_map[] = {
{ 1, 45 }, { 3, 31 }, { 7, 55 }, { 9, 110 }, { 11, 34 },
{ 13, 33 }, { 14, 35 }, { 17, 46 }, { 19, 48 }, { 21, 83 },
{ 22, 36 }, { 26, 38 }, { 35, 37 }, { 39, 125 }, { 41, 47 },
{ 47, 49 }, { 48, 51 }, { 50, 52 }, { 51, 123 }, { 55, 56 },
{ 22, 36 }, { 26, 38 }, { 35, 37 }, { 39, 118 }, { 41, 47 },
{ 47, 49 }, { 48, 51 }, { 50, 52 }, { 51, 116 }, { 55, 56 },
{ 56, 57 }, { 57, 58 }, { 60, 60 }, { 71, 54 }, { 80, 73 },
{ 81, 64 }, { 82, 50 }, { 83, 65 }, { 84, 92 }, { 85, 99 },
{ 86, 67 }, { 87, 84 }, { 88, 124 }, { 89, 122 }, { 90, 69 },
{ 86, 67 }, { 87, 84 }, { 88, 117 }, { 89, 115 }, { 90, 69 },
{ 92, 88 }, { 93, 75 }, { 94, 91 }, { 95, 72 }, { 96, 82 },
{ 97, 74 }, { 98, 95 }, { 99, 94 }, { 100, 100 }, { 101, 40 },
{ 102, 93 }, { 103, 77 }, { 104, 78 }, { 105, 96 }, { 107, 97 },

8
drivers/pinctrl/qcom/pinctrl-sm8150.c
View File

@ -1493,18 +1493,18 @@ static const struct msm_gpio_wakeirq_map sm8150_pdc_map[] = {
{ 3, 31 }, { 5, 32 }, { 8, 33 }, { 9, 34 }, { 10, 100 },
{ 12, 104 }, { 24, 37 }, { 26, 38 }, { 27, 41 }, { 28, 42 },
{ 30, 39 }, { 36, 43 }, { 37, 44 }, { 38, 30 }, { 39, 118 },
{ 39, 125 }, { 41, 47 }, { 42, 48 }, { 46, 50 }, { 47, 49 },
{ 48, 51 }, { 49, 53 }, { 50, 52 }, { 51, 116 }, { 51, 123 },
{ 41, 47 }, { 42, 48 }, { 46, 50 }, { 47, 49 },
{ 48, 51 }, { 49, 53 }, { 50, 52 }, { 51, 116 },
{ 53, 54 }, { 54, 55 }, { 55, 56 }, { 56, 57 }, { 58, 58 },
{ 60, 60 }, { 61, 61 }, { 68, 62 }, { 70, 63 }, { 76, 71 },
{ 77, 66 }, { 81, 64 }, { 83, 65 }, { 86, 67 }, { 87, 84 },
{ 88, 117 }, { 88, 124 }, { 90, 69 }, { 91, 70 }, { 93, 75 },
{ 88, 117 }, { 90, 69 }, { 91, 70 }, { 93, 75 },
{ 95, 72 }, { 96, 73 }, { 97, 74 }, { 101, 40 }, { 103, 77 },
{ 104, 78 }, { 108, 79 }, { 112, 80 }, { 113, 81 }, { 114, 82 },
{ 117, 85 }, { 118, 101 }, { 119, 87 }, { 120, 88 }, { 121, 89 },
{ 122, 90 }, { 123, 91 }, { 124, 92 }, { 125, 93 }, { 129, 94 },
{ 132, 105 }, { 133, 83 }, { 134, 36 }, { 136, 97 }, { 142, 103 },
{ 144, 115 }, { 144, 122 }, { 147, 102 }, { 150, 107 },
{ 144, 115 }, { 147, 102 }, { 150, 107 },
{ 152, 108 }, { 153, 109 }
};

23
drivers/pinctrl/renesas/pinctrl-rzg2l.c
View File

@ -335,7 +335,7 @@ struct rzg2l_pinctrl_reg_cache {
u32 *iolh[2];
u32 *ien[2];
u32 *pupd[2];
u32 *smt;
u32 *smt[2];
u8 sd_ch[2];
u8 eth_poc[2];
u8 oen;
@ -2737,10 +2737,6 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)
if (!cache->pfc)
return -ENOMEM;
cache->smt = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->smt), GFP_KERNEL);
if (!cache->smt)
return -ENOMEM;
for (u8 i = 0; i < 2; i++) {
u32 n_dedicated_pins = pctrl->data->n_dedicated_pins;
@ -2759,6 +2755,11 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)
if (!cache->pupd[i])
return -ENOMEM;
cache->smt[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->smt[i]),
GFP_KERNEL);
if (!cache->smt[i])
return -ENOMEM;
/* Allocate dedicated cache. */
dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,
sizeof(*dedicated_cache->iolh[i]),
@ -3049,7 +3050,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off),
cache->pupd[0][port]);
if (pincnt >= 4) {
RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off),
RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off) + 4,
cache->pupd[1][port]);
}
}
@ -3066,8 +3067,14 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
}
}
if (has_smt)
RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off), cache->smt[port]);
if (has_smt) {
RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off),
cache->smt[0][port]);
if (pincnt >= 4) {
RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off) + 4,
cache->smt[1][port]);
}
}
}
}