perf/cxlpmu: Fix typos in cxl_pmu.c comments and documentation
Fix several minor typo errors in comments: - Remove duplicated word "a" in "a a VID / GroupID". - Correct "Opcopdes" to "Opcodes" in CXL spec reference. - Fix spelling of "implemnted" to "implemented". Improves code readability and documentation consistency. Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Link: https://lore.kernel.org/r/20250624194350.109790-4-alok.a.tiwari@oracle.com Signed-off-by: Will Deacon <will@kernel.org>pull/1309/head
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3e870815cc
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0259de6331
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@ -113,7 +113,7 @@ struct cxl_pmu_info {
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/*
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* All CPMU counters are discoverable via the Event Capabilities Registers.
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* Each Event Capability register contains a a VID / GroupID.
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* Each Event Capability register contains a VID / GroupID.
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* A counter may then count any combination (by summing) of events in
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* that group which are in the Supported Events Bitmask.
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* However, there are some complexities to the scheme.
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@ -406,7 +406,7 @@ static struct attribute *cxl_pmu_event_attrs[] = {
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CXL_PMU_EVENT_CXL_ATTR(s2m_bisnp_curblk, CXL_PMU_GID_S2M_BISNP, BIT(4)),
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CXL_PMU_EVENT_CXL_ATTR(s2m_bisnp_datblk, CXL_PMU_GID_S2M_BISNP, BIT(5)),
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CXL_PMU_EVENT_CXL_ATTR(s2m_bisnp_invblk, CXL_PMU_GID_S2M_BISNP, BIT(6)),
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/* CXL rev 3.1 Table 3-50 S2M NDR Opcopdes */
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/* CXL rev 3.1 Table 3-50 S2M NDR Opcodes */
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CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmp, CXL_PMU_GID_S2M_NDR, BIT(0)),
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CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmps, CXL_PMU_GID_S2M_NDR, BIT(1)),
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CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmpe, CXL_PMU_GID_S2M_NDR, BIT(2)),
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@ -627,7 +627,7 @@ static void cxl_pmu_event_start(struct perf_event *event, int flags)
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hwc->state = 0;
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/*
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* Currently only hdm filter control is implemnted, this code will
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* Currently only hdm filter control is implemented, this code will
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* want generalizing when more filters are added.
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*/
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if (info->filter_hdm) {
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