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drm/amd/display: Adjust functions prefix for some of the dcn301 fpu functions 

Add dcn301_fpu prefix to some of the FPU function with the required
adjustments.

Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
pull/914/head
Rodrigo Siqueira 2024-04-18 14:06:45 -06:00 committed by Alex Deucher
parent b9f5fcef72
commit 033656afab
3 changed files with 18 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
View File

@ -320,7 +320,7 @@ static void calculate_wm_set_for_vlevel(int vlevel,
}
void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
{
struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;
struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool);
@ -409,7 +409,7 @@ void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info)
dcn3_01_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
}
void dcn301_calculate_wm_and_dlg_fp(struct dc *dc,
void dcn301_fpu_calculate_wm_and_dlg(struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int pipe_cnt,

7
drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h
View File

@ -26,15 +26,14 @@
#ifndef __DCN301_FPU_H__
#define __DCN301_FPU_H__
void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info);
void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
void dcn301_fpu_set_wm_ranges(int i,
struct pp_smu_wm_range_sets *ranges,
struct _vcs_dpi_soc_bounding_box_st *loaded_bb);
void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info);
void dcn301_calculate_wm_and_dlg_fp(struct dc *dc,
void dcn301_fpu_calculate_wm_and_dlg(struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int pipe_cnt,

19
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
View File

@ -1363,14 +1363,21 @@ static void set_wm_ranges(
pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges);
}
static void dcn301_calculate_wm_and_dlg(
struct dc *dc, struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int pipe_cnt,
int vlevel)
static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
{
DC_FP_START();
dcn301_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
dcn301_fpu_update_bw_bounding_box(dc, bw_params);
DC_FP_END();
}
static void dcn301_calculate_wm_and_dlg(struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int pipe_cnt,
int vlevel_req)
{
DC_FP_START();
dcn301_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel_req);
DC_FP_END();
}