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Qualcomm Arm64 DeviceTree updates for v6.14 

This adds support for the new Snapdragon 8 Elite platform with MTP and
 QRD boards, QCS615 platform with the Ride board, QCS8300 platform with
 its Ride board, IPQ5424 platform with the RDP466 board, MSM8917 platform
 with Xiaomi Redmi 5A, and the SAR2130P platform with the Snapdragon AR2
 Gen1 Smart Viewer Development Kit.
 
 On X Elite the HP Omnibook X laptop and the Snapdragon Devkit are added.
 The 8cx Gen3-based Huawaei Matebook E Go and Microsoft Windows Dev Kit
 2023 are introduced.
 
 IPQ9574 gains PCIe and TRNG descriptions, together with a few other
 smaller improvements. TRNG is also enabled on the IPQ5332 platform.
 
 On MSM8994, Huawei Nexus 6P gains power and volume keys support. USB
 interrupts are corrected.
 
 On QCM6490 the FairPhone 5 gains camera EEPROM and Rb3Gen2 development
 kit gains description of the onboard LEDs.
 
 On QRB4210 RB2 support for HDMI audio playback is added.
 
 SA8775P gains missing clock controllers, CPUs are tied to PSCI power
 domains, DisplayPort is introduced and enabled on the Ride board.
 
 On SDM670 the GPU components are described and enabled for Google Pixel
 3a, together with camera clock controller and flash LED.
 
 Xiaomi Mi Pad 5 Pro, on SM8250, gets WiFi and Bluetooth enabled.
 
 "global" IRQ for PCIe RC controllers are described on SM8550 and SM8650,
 to allow for hotplug events.
 
 Coresight support is added for SM8450, SM8650, X 1 Elite, QCS615,
 and QCS8300.
 
 The X Elite platform gains QUP power domains and OPPs, another PCIe
 controller, another UART, and its SDHCI controllers. The ASUS Vivobook S
 15 gets GPU and lid switch enabled. Microsoft Surface Laptop 7 gains
 audio configuration, SD card reader support, and USB retimers. The
 Lenovo Yoga Slim 7x gets its LID switch described. Dell XPS 13 gains
 retimers described. The Lenovo Thinkpad T14s has additional USB ports
 enabled, as well as sound and fingerprint sensor.
 
 USB U1/U2 entry is disabled across a variety of platforms, to improve
 USB stability.
 
 sleep clock frequencies are reviewed and corrected for a variety of
 platforms, so is also various remoteproc mmio address ranges.
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Merge tag 'qcom-arm64-for-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

Qualcomm Arm64 DeviceTree updates for v6.14

This adds support for the new Snapdragon 8 Elite platform with MTP and
QRD boards, QCS615 platform with the Ride board, QCS8300 platform with
its Ride board, IPQ5424 platform with the RDP466 board, MSM8917 platform
with Xiaomi Redmi 5A, and the SAR2130P platform with the Snapdragon AR2
Gen1 Smart Viewer Development Kit.

On X Elite the HP Omnibook X laptop and the Snapdragon Devkit are added.
The 8cx Gen3-based Huawaei Matebook E Go and Microsoft Windows Dev Kit
2023 are introduced.

IPQ9574 gains PCIe and TRNG descriptions, together with a few other
smaller improvements. TRNG is also enabled on the IPQ5332 platform.

On MSM8994, Huawei Nexus 6P gains power and volume keys support. USB
interrupts are corrected.

On QCM6490 the FairPhone 5 gains camera EEPROM and Rb3Gen2 development
kit gains description of the onboard LEDs.

On QRB4210 RB2 support for HDMI audio playback is added.

SA8775P gains missing clock controllers, CPUs are tied to PSCI power
domains, DisplayPort is introduced and enabled on the Ride board.

On SDM670 the GPU components are described and enabled for Google Pixel
3a, together with camera clock controller and flash LED.

Xiaomi Mi Pad 5 Pro, on SM8250, gets WiFi and Bluetooth enabled.

"global" IRQ for PCIe RC controllers are described on SM8550 and SM8650,
to allow for hotplug events.

Coresight support is added for SM8450, SM8650, X 1 Elite, QCS615,
and QCS8300.

The X Elite platform gains QUP power domains and OPPs, another PCIe
controller, another UART, and its SDHCI controllers. The ASUS Vivobook S
15 gets GPU and lid switch enabled. Microsoft Surface Laptop 7 gains
audio configuration, SD card reader support, and USB retimers. The
Lenovo Yoga Slim 7x gets its LID switch described. Dell XPS 13 gains
retimers described. The Lenovo Thinkpad T14s has additional USB ports
enabled, as well as sound and fingerprint sensor.

USB U1/U2 entry is disabled across a variety of platforms, to improve
USB stability.

sleep clock frequencies are reviewed and corrected for a variety of
platforms, so is also various remoteproc mmio address ranges.

* tag 'qcom-arm64-for-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (240 commits)
  arm64: dts: qcom: x1e80100-romulus: Update firmware nodes
  arm64: dts: qcom: msm8916-samsung-serranove: Add display panel
  arm64: dts: qcom: sm8650: Add 'global' interrupt to the PCIe RC nodes
  arm64: dts: qcom: sm8550: Add 'global' interrupt to the PCIe RC nodes
  arm64: dts: qcom: Remove unused and undocumented properties
  arm64: dts: qcom: sdm450-lenovo-tbx605f: add DSI panel nodes
  arm64: dts: qcom: pmi8950: add LAB-IBB nodes
  arm64: dts: qcom: ipq5424: enable the download mode support
  arm64: dts: qcom: ipq5424: add scm node
  arm64: dts: qcom: sm8250: Fix interrupt types of camss interrupts
  arm64: dts: qcom: sdm845: Fix interrupt types of camss interrupts
  arm64: dts: qcom: sc8280xp: Fix interrupt type of camss interrupts
  arm64: dts: qcom: qcs8300-ride: Enable USB controllers
  arm64: dts: qcom: qcs8300: Add support for usb nodes
  arm64: dts: qcom: qcs8300: Add support for clock controllers
  arm64: dts: qcom: sm8450: Add coresight nodes
  arm64: dts: qcom: sa8775p: Fix the size of 'addr_space' regions
  arm64: dts: qcom: qcs615-ride: Enable UFS node
  arm64: dts: qcom: qcs615: add UFS node
  arm64: dts: qcom: ipq5424: Add USB controller and phy nodes
  ...

Link: https://lore.kernel.org/r/20250111181025.394631-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
pull/1134/head
Arnd Bergmann 2025-01-16 15:31:25 +01:00
parent d1181e342b 983833061d
commit 116eda2ec9
121 changed files with 33932 additions and 1091 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
Documentation/devicetree/bindings/arm/qcom-soc.yaml
View File

@ -23,7 +23,7 @@ description: |
select:
properties:
compatible:
pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
required:
- compatible
@ -31,7 +31,8 @@ properties:
compatible:
oneOf:
# Preferred naming style for compatibles of SoC components:
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+(pro)?-.*$"
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+(pro)?-.*$"
- pattern: "^qcom,sar[0-9]+[a-z]?-.*$"
- pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
# Legacy namings - variations of existing patterns/compatibles are OK,
@ -39,9 +40,9 @@ properties:
- pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
- pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
- pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
- pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
- enum:
- qcom,dsi-ctrl-6g-qcm2290
- qcom,gpucc-sdm630

64
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@ -19,29 +19,42 @@ description: |
apq8016
apq8026
apq8064
apq8074
apq8084
apq8094
apq8096
ipq4018
ipq4019
ipq5018
ipq5332
ipq5424
ipq6018
ipq8064
ipq8074
ipq9574
mdm9615
msm8226
msm8660
msm8916
msm8917
msm8926
msm8929
msm8939
msm8953
msm8956
msm8960
msm8974
msm8974pro
msm8976
msm8992
msm8994
msm8996
msm8996pro
msm8998
qcs404
qcs615
qcs8300
qcs8550
qcm2290
qcm6490
@ -53,6 +66,7 @@ description: |
sa8155p
sa8540p
sa8775p
sar2130p
sc7180
sc7280
sc8180x
@ -84,7 +98,10 @@ description: |
sm8450
sm8550
sm8650
sm8750
x1e78100
x1e80100
x1p42100
There are many devices in the list below that run the standard ChromeOS
bootloader setup and use the open source depthcharge bootloader to boot the
@ -250,6 +267,11 @@ properties:
- yiming,uz801-v3
- const: qcom,msm8916
- items:
- enum:
- xiaomi,riva
- const: qcom,msm8917
- items:
- enum:
- motorola,potter
@ -352,6 +374,11 @@ properties:
- qcom,ipq5332-ap-mi01.9
- const: qcom,ipq5332
- items:
- enum:
- qcom,ipq5424-rdp466
- const: qcom,ipq5424
- items:
- enum:
- mikrotik,rb3011
@ -408,6 +435,12 @@ properties:
- qcom,qru1000-idp
- const: qcom,qru1000
- description: Qualcomm AR2 Gen1 platform
items:
- enum:
- qcom,qar2130p
- const: qcom,sar2130p
- items:
- enum:
- acer,aspire1
@ -822,8 +855,10 @@ properties:
- items:
- enum:
- huawei,gaokun3
- lenovo,thinkpad-x13s
- microsoft,arcata
- microsoft,blackrock
- qcom,sc8280xp-crd
- qcom,sc8280xp-qrd
- const: qcom,sc8280xp
@ -898,6 +933,16 @@ properties:
- const: qcom,qcs404-evb
- const: qcom,qcs404
- items:
- enum:
- qcom,qcs8300-ride
- const: qcom,qcs8300
- items:
- enum:
- qcom,qcs615-ride
- const: qcom,qcs615
- items:
- enum:
- qcom,sa8155p-adp
@ -1064,6 +1109,18 @@ properties:
- qcom,sm8650-qrd
- const: qcom,sm8650
- items:
- enum:
- qcom,sm8750-mtp
- qcom,sm8750-qrd
- const: qcom,sm8750
- items:
- enum:
- qcom,x1e001de-devkit
- const: qcom,x1e001de
- const: qcom,x1e80100
- items:
- enum:
- lenovo,thinkpad-t14s
@ -1074,6 +1131,7 @@ properties:
- enum:
- asus,vivobook-s15
- dell,xps13-9345
- hp,omnibook-x14
- lenovo,yoga-slim7x
- microsoft,romulus13
- microsoft,romulus15
@ -1081,6 +1139,11 @@ properties:
- qcom,x1e80100-qcp
- const: qcom,x1e80100
- items:
- enum:
- qcom,x1p42100-crd
- const: qcom,x1p42100
# Board compatibles go above
qcom,msm-id:
@ -1158,6 +1221,7 @@ allOf:
- qcom,apq8026
- qcom,apq8094
- qcom,apq8096
- qcom,msm8917
- qcom,msm8939
- qcom,msm8953
- qcom,msm8956

77
Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml Normal file
View File

@ -0,0 +1,77 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm CMN PLL Clock Controller on IPQ SoC
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Luo Jie <quic_luoj@quicinc.com>
description:
The CMN (or common) PLL clock controller expects a reference
input clock. This reference clock is from the on-board Wi-Fi.
The CMN PLL supplies a number of fixed rate output clocks to
the devices providing networking functions and to GCC. These
networking hardware include PPE (packet process engine), PCS
and the externally connected switch or PHY devices. The CMN
PLL block also outputs fixed rate clocks to GCC. The PLL's
primary function is to enable fixed rate output clocks for
networking hardware functions used with the IPQ SoC.
properties:
compatible:
enum:
- qcom,ipq9574-cmn-pll
reg:
maxItems: 1
clocks:
items:
- description: The reference clock. The supported clock rates include
25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.
- description: The AHB clock
- description: The SYS clock
description:
The reference clock is the source clock of CMN PLL, which is from the
Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL
clock registers.
clock-names:
items:
- const: ref
- const: ahb
- const: sys
"#clock-cells":
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- "#clock-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
cmn_pll: clock-controller@9b000 {
compatible = "qcom,ipq9574-cmn-pll";
reg = <0x0009b000 0x800>;
clocks = <&cmn_pll_ref_clk>,
<&gcc GCC_CMN_12GPLL_AHB_CLK>,
<&gcc GCC_CMN_12GPLL_SYS_CLK>;
clock-names = "ref", "ahb", "sys";
#clock-cells = <1>;
assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
};
...

59
Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml Normal file
View File

@ -0,0 +1,59 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on QCS615
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on QCS615.
See also: include/dt-bindings/clock/qcom,qcs615-gcc.h
properties:
compatible:
const: qcom,qcs615-gcc
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Sleep clock source
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: sleep_clk
required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,qcs615-gcc";
reg = <0x00100000 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

4
Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
View File

@ -12,11 +12,12 @@ maintainers:
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8550.
domains on SM8550, SM8650, SM8750 and few other platforms.
See also:
- include/dt-bindings/clock/qcom,sm8550-dispcc.h
- include/dt-bindings/clock/qcom,sm8650-dispcc.h
- include/dt-bindings/clock/qcom,sm8750-dispcc.h
- include/dt-bindings/clock/qcom,x1e80100-dispcc.h
properties:
@ -25,6 +26,7 @@ properties:
- qcom,sar2130p-dispcc
- qcom,sm8550-dispcc
- qcom,sm8650-dispcc
- qcom,sm8750-dispcc
- qcom,x1e80100-dispcc
clocks:

2
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
View File

@ -16,6 +16,7 @@ description: |
See also:
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
- include/dt-bindings/clock/qcom,sm8750-tcsr.h
properties:
compatible:
@ -24,6 +25,7 @@ properties:
- qcom,sar2130p-tcsr
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
- qcom,sm8750-tcsr
- qcom,x1e80100-tcsr
- const: syscon

62
Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml Normal file
View File

@ -0,0 +1,62 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8750-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SM8750
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8750
See also: include/dt-bindings/clock/qcom,sm8750-gcc.h
properties:
compatible:
const: qcom,sm8750-gcc
clocks:
items:
- description: Board XO source
- description: Board Always On XO source
- description: Sleep clock source
- description: PCIE 0 Pipe clock source
- description: UFS Phy Rx symbol 0 clock source
- description: UFS Phy Rx symbol 1 clock source
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,sm8750-gcc";
reg = <0x00100000 0x001f4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<&pcie0_phy>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
<&usb_1_qmpphy>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

136
Documentation/devicetree/bindings/interconnect/qcom,sm8750-rpmh.yaml Normal file
View File

@ -0,0 +1,136 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sm8750-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on SM8750
maintainers:
- Abel Vesa <abel.vesa@linaro.org>
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also:: include/dt-bindings/interconnect/qcom,sm8750-rpmh.h
properties:
compatible:
enum:
- qcom,sm8750-aggre1-noc
- qcom,sm8750-aggre2-noc
- qcom,sm8750-clk-virt
- qcom,sm8750-cnoc-main
- qcom,sm8750-config-noc
- qcom,sm8750-gem-noc
- qcom,sm8750-lpass-ag-noc
- qcom,sm8750-lpass-lpiaon-noc
- qcom,sm8750-lpass-lpicx-noc
- qcom,sm8750-mc-virt
- qcom,sm8750-mmss-noc
- qcom,sm8750-nsp-noc
- qcom,sm8750-pcie-anoc
- qcom,sm8750-system-noc
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8750-clk-virt
- qcom,sm8750-mc-virt
then:
properties:
reg: false
else:
required:
- reg
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8750-pcie-anoc
then:
properties:
clocks:
items:
- description: aggre-NOC PCIe AXI clock
- description: cfg-NOC PCIe a-NOC AHB clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8750-aggre1-noc
then:
properties:
clocks:
items:
- description: aggre UFS PHY AXI clock
- description: aggre USB3 PRIM AXI clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8750-aggre2-noc
then:
properties:
clocks:
items:
- description: RPMH CC IPA clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8750-aggre1-noc
- qcom,sm8750-aggre2-noc
- qcom,sm8750-pcie-anoc
then:
required:
- clocks
else:
properties:
clocks: false
unevaluatedProperties: false
examples:
- |
clk_virt: interconnect-0 {
compatible = "qcom,sm8750-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,sm8750-aggre1-noc";
reg = <0x016e0000 0x16400>;
#interconnect-cells = <2>;
clocks = <&gcc_phy_axi_clk>, <&gcc_prim_axi_clk>;
qcom,bcm-voters = <&apps_bcm_voter>;
};

12
arch/arm64/boot/dts/qcom/Makefile
View File

@ -3,6 +3,8 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
apq8016-sbc-usb-host-dtbs := apq8016-sbc.dtb apq8016-sbc-usb-host.dtbo
dtb-$(CONFIG_ARCH_QCOM) += sar2130p-qar2130p.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-usb-host.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-d3-camera-mezzanine.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8016-schneider-hmibsc.dtb
@ -16,6 +18,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp474.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5424-rdp466.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
@ -59,6 +62,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt86518.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt86528.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8917-xiaomi-riva.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8929-wingtech-wt82918hd.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8939-huawei-kiwi.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8939-longcheer-l9100.dtb
@ -110,7 +114,9 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb
@ -195,8 +201,10 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc8180x-lenovo-flex-5g.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc8180x-primus.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-huawei-gaokun3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-microsoft-arcata.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-microsoft-blackrock.dtb
dtb-$(CONFIG_ARCH_QCOM) += sda660-inforce-ifc6560.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm450-lenovo-tbx605f.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm450-motorola-ali.dtb
@ -278,10 +286,14 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8750-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8750-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e001de-devkit.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e78100-lenovo-thinkpad-t14s.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-asus-vivobook-s15.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-dell-xps13-9345.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-hp-omnibook-x14.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-lenovo-yoga-slim7x.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus13.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus15.dtb

2
arch/arm64/boot/dts/qcom/ipq5332.dtsi
View File

@ -180,7 +180,7 @@
};
rng: rng@e3000 {
compatible = "qcom,prng-ee";
compatible = "qcom,ipq5332-trng", "qcom,trng";
reg = <0x000e3000 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";

169
arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts Normal file
View File

@ -0,0 +1,169 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* IPQ5424 RDP466 board device tree source
*
* Copyright (c) 2024 The Linux Foundation. All rights reserved.
*/
/dts-v1/;
#include "ipq5424.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ5424 RDP466";
compatible = "qcom,ipq5424-rdp466", "qcom,ipq5424";
aliases {
serial0 = &uart1;
};
vreg_misc_3p3: regulator-usb-3p3 {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-name = "usb_hs_vdda_3p3";
};
vreg_misc_1p8: regulator-usb-1p8 {
compatible = "regulator-fixed";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
regulator-name = "vdda_1p8_usb";
};
vreg_misc_0p925: regulator-usb-0p925 {
compatible = "regulator-fixed";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <925000>;
regulator-boot-on;
regulator-always-on;
regulator-name = "vdd_core_usb";
};
};
&dwc_0 {
dr_mode = "host";
};
&dwc_1 {
dr_mode = "host";
};
&qusb_phy_0 {
vdd-supply = <&vreg_misc_0p925>;
vdda-pll-supply = <&vreg_misc_1p8>;
vdda-phy-dpdm-supply = <&vreg_misc_3p3>;
status = "okay";
};
&qusb_phy_1 {
vdd-supply = <&vreg_misc_0p925>;
vdda-pll-supply = <&vreg_misc_1p8>;
vdda-phy-dpdm-supply = <&vreg_misc_3p3>;
status = "okay";
};
&sleep_clk {
clock-frequency = <32000>;
};
&spi0 {
pinctrl-0 = <&spi0_default_state>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "micron,n25q128a11", "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
};
};
&ssphy_0 {
vdda-pll-supply = <&vreg_misc_1p8>;
vdda-phy-supply = <&vreg_misc_0p925>;
status = "okay";
};
&tlmm {
spi0_default_state: spi0-default-state {
clk-pins {
pins = "gpio6";
function = "spi0_clk";
drive-strength = <8>;
bias-pull-down;
};
cs-pins {
pins = "gpio7";
function = "spi0_cs";
drive-strength = <8>;
bias-pull-up;
};
miso-pins {
pins = "gpio8";
function = "spi0_miso";
drive-strength = <8>;
bias-pull-down;
};
mosi-pins {
pins = "gpio9";
function = "spi0_mosi";
drive-strength = <8>;
bias-pull-down;
};
};
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio5";
function = "sdc_clk";
drive-strength = <8>;
bias-disable;
};
cmd-pins {
pins = "gpio4";
function = "sdc_cmd";
drive-strength = <8>;
bias-pull-up;
};
data-pins {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "sdc_data";
drive-strength = <8>;
bias-pull-up;
};
};
};
&uart1 {
pinctrl-0 = <&uart1_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb2 {
status = "okay";
};
&usb3 {
status = "okay";
};
&xo_board {
clock-frequency = <24000000>;
};

519
arch/arm64/boot/dts/qcom/ipq5424.dtsi Normal file
View File

@ -0,0 +1,519 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* IPQ5424 device tree source
*
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&intc>;
clocks {
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
xo_board: xo-board-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&l2_0>;
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
enable-method = "psci";
reg = <0x100>;
next-level-cache = <&l2_100>;
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
enable-method = "psci";
reg = <0x200>;
next-level-cache = <&l2_200>;
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
enable-method = "psci";
reg = <0x300>;
next-level-cache = <&l2_300>;
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
};
firmware {
scm {
compatible = "qcom,scm-ipq5424", "qcom,scm";
qcom,dload-mode = <&tcsr 0x25100>;
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0x0 0x80000000 0x0 0x0>;
};
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
pmu-dsu {
compatible = "arm,dsu-pmu";
interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
tz@8a600000 {
reg = <0x0 0x8a600000 0x0 0x200000>;
no-map;
};
smem@8a800000 {
compatible = "qcom,smem";
reg = <0x0 0x8a800000 0x0 0x32000>;
no-map;
hwlocks = <&tcsr_mutex 3>;
};
};
soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0 0x10 0>;
rng: rng@4c3000 {
compatible = "qcom,ipq5424-trng", "qcom,trng";
reg = <0 0x004c3000 0 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
system-cache-controller@800000 {
compatible = "qcom,ipq5424-llcc";
reg = <0 0x00800000 0 0x200000>;
reg-names = "llcc0_base";
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
};
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5424-tlmm";
reg = <0 0x01000000 0 0x300000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 50>;
interrupt-controller;
#interrupt-cells = <2>;
uart1_pins: uart1-state {
pins = "gpio43", "gpio44";
function = "uart1";
drive-strength = <8>;
bias-pull-up;
};
};
gcc: clock-controller@1800000 {
compatible = "qcom,ipq5424-gcc";
reg = <0 0x01800000 0 0x40000>;
clocks = <&xo_board>,
<&sleep_clk>,
<0>,
<0>,
<0>,
<0>,
<0>;
#clock-cells = <1>;
#reset-cells = <1>;
#interconnect-cells = <1>;
};
tcsr_mutex: hwlock@1905000 {
compatible = "qcom,tcsr-mutex";
reg = <0 0x01905000 0 0x20000>;
#hwlock-cells = <1>;
};
tcsr: syscon@1937000 {
compatible = "qcom,tcsr-ipq5424", "syscon";
reg = <0 0x01937000 0 0x2a000>;
};
qupv3: geniqup@1ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x01ac0000 0 0x2000>;
ranges;
clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
<&gcc GCC_QUPV3_AHB_SLV_CLK>;
clock-names = "m-ahb", "s-ahb";
#address-cells = <2>;
#size-cells = <2>;
uart1: serial@1a84000 {
compatible = "qcom,geni-debug-uart";
reg = <0 0x01a84000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_UART1_CLK>;
clock-names = "se";
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
};
spi0: spi@1a90000 {
compatible = "qcom,geni-spi";
reg = <0 0x01a90000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_SPI0_CLK>;
clock-names = "se";
interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@1a94000 {
compatible = "qcom,geni-spi";
reg = <0 0x01a94000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_SPI1_CLK>;
clock-names = "se";
interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
sdhc: mmc@7804000 {
compatible = "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x07804000 0 0x1000>, <0 0x07805000 0 0x1000>;
reg-names = "hc", "cqhci";
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board>;
clock-names = "iface", "core", "xo";
status = "disabled";
};
intc: interrupt-controller@f200000 {
compatible = "arm,gic-v3";
reg = <0 0xf200000 0 0x10000>, /* GICD */
<0 0xf240000 0 0x80000>; /* GICR * 4 regions */
#interrupt-cells = <0x3>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
mbi-ranges = <672 128>;
msi-controller;
};
watchdog@f410000 {
compatible = "qcom,apss-wdt-ipq5424", "qcom,kpss-wdt";
reg = <0 0x0f410000 0 0x1000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
clocks = <&sleep_clk>;
};
qusb_phy_1: phy@71000 {
compatible = "qcom,ipq5424-qusb2-phy";
reg = <0 0x00071000 0 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
<&xo_board>;
clock-names = "cfg_ahb", "ref";
resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
status = "disabled";
};
usb2: usb2@1e00000 {
compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
reg = <0 0x01ef8800 0 0x400>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_USB1_MASTER_CLK>,
<&gcc GCC_USB1_SLEEP_CLK>,
<&gcc GCC_USB1_MOCK_UTMI_CLK>,
<&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
<&gcc GCC_CNOC_USB_CLK>;
clock-names = "core",
"sleep",
"mock_utmi",
"iface",
"cfg_noc";
assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
<&gcc GCC_USB1_MOCK_UTMI_CLK>;
assigned-clock-rates = <200000000>,
<24000000>;
interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"qusb2_phy",
"dm_hs_phy_irq",
"dp_hs_phy_irq";
resets = <&gcc GCC_USB1_BCR>;
qcom,select-utmi-as-pipe-clk;
status = "disabled";
dwc_1: usb@1e00000 {
compatible = "snps,dwc3";
reg = <0 0x01e00000 0 0xe000>;
clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>;
clock-names = "ref";
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_1>;
phy-names = "usb2-phy";
tx-fifo-resize;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
};
};
qusb_phy_0: phy@7b000 {
compatible = "qcom,ipq5424-qusb2-phy";
reg = <0 0x0007b000 0 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
<&xo_board>;
clock-names = "cfg_ahb", "ref";
resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
status = "disabled";
};
ssphy_0: phy@7d000 {
compatible = "qcom,ipq5424-qmp-usb3-phy";
reg = <0 0x0007d000 0 0xa00>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB0_AUX_CLK>,
<&xo_board>,
<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB0_PIPE_CLK>;
clock-names = "aux",
"ref",
"cfg_ahb",
"pipe";
resets = <&gcc GCC_USB0_PHY_BCR>,
<&gcc GCC_USB3PHY_0_PHY_BCR>;
reset-names = "phy",
"phy_phy";
#clock-cells = <0>;
clock-output-names = "usb0_pipe_clk";
status = "disabled";
};
usb3: usb3@8a00000 {
compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
reg = <0 0x08af8800 0 0x400>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_USB0_SLEEP_CLK>,
<&gcc GCC_USB0_MOCK_UTMI_CLK>,
<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
<&gcc GCC_CNOC_USB_CLK>;
clock-names = "core",
"sleep",
"mock_utmi",
"iface",
"cfg_noc";
assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
assigned-clock-rates = <200000000>,
<24000000>;
interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"qusb2_phy",
"dm_hs_phy_irq",
"dp_hs_phy_irq";
resets = <&gcc GCC_USB_BCR>;
status = "disabled";
dwc_0: usb@8a00000 {
compatible = "snps,dwc3";
reg = <0 0x08a00000 0 0xcd00>;
clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
clock-names = "ref";
interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_0>, <&ssphy_0>;
phy-names = "usb2-phy", "usb3-phy";
tx-fifo-resize;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
};
};
timer@f420000 {
compatible = "arm,armv7-timer-mem";
reg = <0 0xf420000 0 0x1000>;
ranges = <0 0 0 0x10000000>;
#address-cells = <1>;
#size-cells = <1>;
frame@f421000 {
reg = <0xf421000 0x1000>,
<0xf422000 0x1000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <0>;
};
frame@f423000 {
reg = <0xf423000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <1>;
status = "disabled";
};
frame@f425000 {
reg = <0xf425000 0x1000>,
<0xf426000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <2>;
status = "disabled";
};
frame@f427000 {
reg = <0xf427000 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <3>;
status = "disabled";
};
frame@f429000 {
reg = <0xf429000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <4>;
status = "disabled";
};
frame@f42b000 {
reg = <0xf42b000 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <5>;
status = "disabled";
};
frame@f42d000 {
reg = <0xf42d000 0x1000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <6>;
status = "disabled";
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
};

26
arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
View File

@ -3,7 +3,7 @@
* IPQ9574 RDP board common device tree source
*
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
@ -164,6 +164,26 @@
status = "okay";
};
&xo_board_clk {
clock-frequency = <24000000>;
/*
* The bootstrap pins for the board select the XO clock frequency
* (48 MHZ or 96 MHZ used for different RDP type board). This setting
* automatically enables the right dividers, to ensure the reference
* clock output from WiFi to the CMN PLL is 48 MHZ.
*/
&ref_48mhz_clk {
clock-div = <1>;
clock-mult = <1>;
};
/*
* The frequency of xo_board_clk is fixed to 24 MHZ, which is routed
* from WiFi output clock 48 MHZ divided by 2.
*/
&xo_board_clk {
clock-div = <2>;
clock-mult = <1>;
};
&xo_clk {
clock-frequency = <48000000>;
};

113
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
View File

@ -8,6 +8,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "ipq9574-rdp-common.dtsi"
/ {
@ -15,6 +16,45 @@
compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
};
&pcie1_phy {
status = "okay";
};
&pcie1 {
pinctrl-0 = <&pcie1_default>;
pinctrl-names = "default";
perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcie2_phy {
status = "okay";
};
&pcie2 {
pinctrl-0 = <&pcie2_default>;
pinctrl-names = "default";
perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcie3_phy {
status = "okay";
};
&pcie3 {
pinctrl-0 = <&pcie3_default>;
pinctrl-names = "default";
perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
status = "okay";
};
&sdhc_1 {
pinctrl-0 = <&sdc_default_state>;
pinctrl-names = "default";
@ -28,6 +68,79 @@
};
&tlmm {
pcie1_default: pcie1-default-state {
clkreq-n-pins {
pins = "gpio25";
function = "pcie1_clk";
drive-strength = <6>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio26";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
output-low;
};
wake-n-pins {
pins = "gpio27";
function = "pcie1_wake";
drive-strength = <6>;
bias-pull-up;
};
};
pcie2_default: pcie2-default-state {
clkreq-n-pins {
pins = "gpio28";
function = "pcie2_clk";
drive-strength = <6>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio29";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
output-low;
};
wake-n-pins {
pins = "gpio30";
function = "pcie2_wake";
drive-strength = <6>;
bias-pull-up;
};
};
pcie3_default: pcie3-default-state {
clkreq-n-pins {
pins = "gpio31";
function = "pcie3_clk";
drive-strength = <6>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio32";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
output-low;
};
wake-n-pins {
pins = "gpio33";
function = "pcie3_wake";
drive-strength = <6>;
bias-pull-up;
};
};
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio5";

449
arch/arm64/boot/dts/qcom/ipq9574.dtsi
View File

@ -3,10 +3,11 @@
* IPQ9574 SoC device tree source
*
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
#include <dt-bindings/interconnect/qcom,ipq9574.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -19,12 +20,24 @@
#size-cells = <2>;
clocks {
ref_48mhz_clk: ref-48mhz-clk {
compatible = "fixed-factor-clock";
clocks = <&xo_clk>;
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
xo_board_clk: xo-board-clk {
compatible = "fixed-factor-clock";
clocks = <&ref_48mhz_clk>;
#clock-cells = <0>;
};
xo_clk: xo-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
@ -226,8 +239,54 @@
reg = <0x00060000 0x6000>;
};
pcie0_phy: phy@84000 {
compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
reg = <0x00084000 0x1000>;
clocks = <&gcc GCC_PCIE0_AUX_CLK>,
<&gcc GCC_PCIE0_AHB_CLK>,
<&gcc GCC_PCIE0_PIPE_CLK>;
clock-names = "aux", "cfg_ahb", "pipe";
assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
assigned-clock-rates = <20000000>;
resets = <&gcc GCC_PCIE0_PHY_BCR>,
<&gcc GCC_PCIE0PHY_PHY_BCR>;
reset-names = "phy", "common";
#clock-cells = <0>;
clock-output-names = "gcc_pcie0_pipe_clk_src";
#phy-cells = <0>;
status = "disabled";
};
pcie2_phy: phy@8c000 {
compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
reg = <0x0008c000 0x2000>;
clocks = <&gcc GCC_PCIE2_AUX_CLK>,
<&gcc GCC_PCIE2_AHB_CLK>,
<&gcc GCC_PCIE2_PIPE_CLK>;
clock-names = "aux", "cfg_ahb", "pipe";
assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
assigned-clock-rates = <20000000>;
resets = <&gcc GCC_PCIE2_PHY_BCR>,
<&gcc GCC_PCIE2PHY_PHY_BCR>;
reset-names = "phy", "common";
#clock-cells = <0>;
clock-output-names = "gcc_pcie2_pipe_clk_src";
#phy-cells = <0>;
status = "disabled";
};
rng: rng@e3000 {
compatible = "qcom,prng-ee";
compatible = "qcom,ipq9574-trng", "qcom,trng";
reg = <0x000e3000 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
@ -243,6 +302,64 @@
status = "disabled";
};
pcie3_phy: phy@f4000 {
compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
reg = <0x000f4000 0x2000>;
clocks = <&gcc GCC_PCIE3_AUX_CLK>,
<&gcc GCC_PCIE3_AHB_CLK>,
<&gcc GCC_PCIE3_PIPE_CLK>;
clock-names = "aux", "cfg_ahb", "pipe";
assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
assigned-clock-rates = <20000000>;
resets = <&gcc GCC_PCIE3_PHY_BCR>,
<&gcc GCC_PCIE3PHY_PHY_BCR>;
reset-names = "phy", "common";
#clock-cells = <0>;
clock-output-names = "gcc_pcie3_pipe_clk_src";
#phy-cells = <0>;
status = "disabled";
};
pcie1_phy: phy@fc000 {
compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
reg = <0x000fc000 0x1000>;
clocks = <&gcc GCC_PCIE1_AUX_CLK>,
<&gcc GCC_PCIE1_AHB_CLK>,
<&gcc GCC_PCIE1_PIPE_CLK>;
clock-names = "aux", "cfg_ahb", "pipe";
assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
assigned-clock-rates = <20000000>;
resets = <&gcc GCC_PCIE1_PHY_BCR>,
<&gcc GCC_PCIE1PHY_PHY_BCR>;
reset-names = "phy", "common";
#clock-cells = <0>;
clock-output-names = "gcc_pcie1_pipe_clk_src";
#phy-cells = <0>;
status = "disabled";
};
cmn_pll: clock-controller@9b000 {
compatible = "qcom,ipq9574-cmn-pll";
reg = <0x0009b000 0x800>;
clocks = <&ref_48mhz_clk>,
<&gcc GCC_CMN_12GPLL_AHB_CLK>,
<&gcc GCC_CMN_12GPLL_SYS_CLK>;
clock-names = "ref", "ahb", "sys";
#clock-cells = <1>;
assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
};
qfprom: efuse@a4000 {
compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
reg = <0x000a4000 0x5a1>;
@ -309,10 +426,10 @@
clocks = <&xo_board_clk>,
<&sleep_clk>,
<0>,
<0>,
<0>,
<0>,
<0>,
<&pcie0_phy>,
<&pcie1_phy>,
<&pcie2_phy>,
<&pcie3_phy>,
<0>;
#clock-cells = <1>;
#reset-cells = <1>;
@ -756,6 +873,326 @@
status = "disabled";
};
};
pcie1: pcie@10000000 {
compatible = "qcom,pcie-ipq9574";
reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>,
<0x10001000 0x1000>,
<0x000f8000 0x4000>,
<0x10100000 0x1000>;
reg-names = "dbi", "elbi", "atu", "parf", "config";
device_type = "pci";
linux,pci-domain = <1>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>,
<0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 49 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 84 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
<&gcc GCC_PCIE1_AXI_S_CLK>,
<&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
<&gcc GCC_PCIE1_RCHNG_CLK>,
<&gcc GCC_PCIE1_AHB_CLK>,
<&gcc GCC_PCIE1_AUX_CLK>;
clock-names = "axi_m",
"axi_s",
"axi_bridge",
"rchng",
"ahb",
"aux";
resets = <&gcc GCC_PCIE1_PIPE_ARES>,
<&gcc GCC_PCIE1_CORE_STICKY_ARES>,
<&gcc GCC_PCIE1_AXI_S_STICKY_ARES>,
<&gcc GCC_PCIE1_AXI_S_ARES>,
<&gcc GCC_PCIE1_AXI_M_STICKY_ARES>,
<&gcc GCC_PCIE1_AXI_M_ARES>,
<&gcc GCC_PCIE1_AUX_ARES>,
<&gcc GCC_PCIE1_AHB_ARES>;
reset-names = "pipe",
"sticky",
"axi_s_sticky",
"axi_s",
"axi_m_sticky",
"axi_m",
"aux",
"ahb";
phys = <&pcie1_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
<&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
};
pcie3: pcie@18000000 {
compatible = "qcom,pcie-ipq9574";
reg = <0x18000000 0xf1d>,
<0x18000f20 0xa8>,
<0x18001000 0x1000>,
<0x000f0000 0x4000>,
<0x18100000 0x1000>;
reg-names = "dbi", "elbi", "atu", "parf", "config";
device_type = "pci";
linux,pci-domain = <3>;
bus-range = <0x00 0xff>;
num-lanes = <2>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>,
<0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 190 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 191 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 192 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE3_AXI_M_CLK>,
<&gcc GCC_PCIE3_AXI_S_CLK>,
<&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>,
<&gcc GCC_PCIE3_RCHNG_CLK>,
<&gcc GCC_PCIE3_AHB_CLK>,
<&gcc GCC_PCIE3_AUX_CLK>;
clock-names = "axi_m",
"axi_s",
"axi_bridge",
"rchng",
"ahb",
"aux";
resets = <&gcc GCC_PCIE3_PIPE_ARES>,
<&gcc GCC_PCIE3_CORE_STICKY_ARES>,
<&gcc GCC_PCIE3_AXI_S_STICKY_ARES>,
<&gcc GCC_PCIE3_AXI_S_ARES>,
<&gcc GCC_PCIE3_AXI_M_STICKY_ARES>,
<&gcc GCC_PCIE3_AXI_M_ARES>,
<&gcc GCC_PCIE3_AUX_ARES>,
<&gcc GCC_PCIE3_AHB_ARES>;
reset-names = "pipe",
"sticky",
"axi_s_sticky",
"axi_s",
"axi_m_sticky",
"axi_m",
"aux",
"ahb";
phys = <&pcie3_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>,
<&gcc MASTER_SNOC_PCIE3 &gcc SLAVE_SNOC_PCIE3>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
};
pcie2: pcie@20000000 {
compatible = "qcom,pcie-ipq9574";
reg = <0x20000000 0xf1d>,
<0x20000f20 0xa8>,
<0x20001000 0x1000>,
<0x00088000 0x4000>,
<0x20100000 0x1000>;
reg-names = "dbi", "elbi", "atu", "parf", "config";
device_type = "pci";
linux,pci-domain = <2>;
bus-range = <0x00 0xff>;
num-lanes = <2>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x100000>,
<0x02000000 0x0 0x20300000 0x20300000 0x0 0x7d00000>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 186 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE2_AXI_M_CLK>,
<&gcc GCC_PCIE2_AXI_S_CLK>,
<&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>,
<&gcc GCC_PCIE2_RCHNG_CLK>,
<&gcc GCC_PCIE2_AHB_CLK>,
<&gcc GCC_PCIE2_AUX_CLK>;
clock-names = "axi_m",
"axi_s",
"axi_bridge",
"rchng",
"ahb",
"aux";
resets = <&gcc GCC_PCIE2_PIPE_ARES>,
<&gcc GCC_PCIE2_CORE_STICKY_ARES>,
<&gcc GCC_PCIE2_AXI_S_STICKY_ARES>,
<&gcc GCC_PCIE2_AXI_S_ARES>,
<&gcc GCC_PCIE2_AXI_M_STICKY_ARES>,
<&gcc GCC_PCIE2_AXI_M_ARES>,
<&gcc GCC_PCIE2_AUX_ARES>,
<&gcc GCC_PCIE2_AHB_ARES>;
reset-names = "pipe",
"sticky",
"axi_s_sticky",
"axi_s",
"axi_m_sticky",
"axi_m",
"aux",
"ahb";
phys = <&pcie2_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>,
<&gcc MASTER_SNOC_PCIE2 &gcc SLAVE_SNOC_PCIE2>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
};
pcie0: pci@28000000 {
compatible = "qcom,pcie-ipq9574";
reg = <0x28000000 0xf1d>,
<0x28000f20 0xa8>,
<0x28001000 0x1000>,
<0x00080000 0x4000>,
<0x28100000 0x1000>;
reg-names = "dbi", "elbi", "atu", "parf", "config";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x28200000 0x0 0x100000>,
<0x02000000 0x0 0x28300000 0x28300000 0x0 0x7d00000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE0_AXI_M_CLK>,
<&gcc GCC_PCIE0_AXI_S_CLK>,
<&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
<&gcc GCC_PCIE0_RCHNG_CLK>,
<&gcc GCC_PCIE0_AHB_CLK>,
<&gcc GCC_PCIE0_AUX_CLK>;
clock-names = "axi_m",
"axi_s",
"axi_bridge",
"rchng",
"ahb",
"aux";
resets = <&gcc GCC_PCIE0_PIPE_ARES>,
<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
<&gcc GCC_PCIE0_AXI_S_STICKY_ARES>,
<&gcc GCC_PCIE0_AXI_S_ARES>,
<&gcc GCC_PCIE0_AXI_M_STICKY_ARES>,
<&gcc GCC_PCIE0_AXI_M_ARES>,
<&gcc GCC_PCIE0_AUX_ARES>,
<&gcc GCC_PCIE0_AHB_ARES>;
reset-names = "pipe",
"sticky",
"axi_s_sticky",
"axi_s",
"axi_m_sticky",
"axi_m",
"aux",
"ahb";
phys = <&pcie0_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>,
<&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
};
};
thermal-zones {

58
arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts
View File

@ -321,6 +321,41 @@
status = "okay";
};
&gpu {
status = "okay";
};
&mdss {
status = "okay";
};
&mdss_dsi0 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mdss_default>;
pinctrl-1 = <&mdss_sleep>;
panel@0 {
compatible = "samsung,s6e88a0-ams427ap24";
reg = <0>;
vdd3-supply = <&pm8916_l17>;
vci-supply = <&pm8916_l6>;
reset-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
flip-horizontal;
port {
panel_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
&mdss_dsi0_out {
data-lanes = <0 1>;
remote-endpoint = <&panel_in>;
};
&mpss_mem {
reg = <0x0 0x86800000 0x0 0x5a00000>;
};
@ -330,6 +365,13 @@
linux,code = <KEY_VOLUMEDOWN>;
};
&pm8916_rpm_regulators {
pm8916_l17: l17 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
};
&pm8916_vib {
status = "okay";
};
@ -425,6 +467,22 @@
bias-disable;
};
mdss_default: mdss-default-state {
pins = "gpio25";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
mdss_sleep: mdss-sleep-state {
pins = "gpio25";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
muic_i2c_default: muic-i2c-default-state {
pins = "gpio105", "gpio106";
function = "gpio";

2
arch/arm64/boot/dts/qcom/msm8916.dtsi
View File

@ -125,7 +125,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-frequency = <32764>;
};
};

333
arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts Normal file
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@ -0,0 +1,333 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023, Barnabas Czeman
*/
/dts-v1/;
#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/gpio/gpio.h>
#include "msm8917.dtsi"
#include "pm8937.dtsi"
/delete-node/ &qseecom_mem;
/ {
model = "Xiaomi Redmi 5A (riva)";
compatible = "xiaomi,riva", "qcom,msm8917";
chassis-type = "handset";
qcom,msm-id = <QCOM_ID_MSM8917 0>;
qcom,board-id = <0x1000b 2>, <0x2000b 2>;
battery: battery {
compatible = "simple-battery";
charge-full-design-microamp-hours = <3000000>;
energy-full-design-microwatt-hours = <11500000>;
constant-charge-current-max-microamp = <1000000>;
constant-charge-voltage-max-microvolt = <4400000>;
precharge-current-microamp = <256000>;
charge-term-current-microamp = <60000>;
voltage-min-design-microvolt = <3400000>;
};
chosen {
#address-cells = <2>;
#size-cells = <2>;
ranges;
stdout-path = "framebuffer0";
framebuffer0: framebuffer@90001000 {
compatible = "simple-framebuffer";
reg = <0x0 0x90001000 0x0 (720 * 1280 * 3)>;
width = <720>;
height = <1280>;
stride = <(720 * 3)>;
format = "r8g8b8";
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_VSYNC_CLK>,
<&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_BYTE0_CLK>,
<&gcc GCC_MDSS_PCLK0_CLK>,
<&gcc GCC_MDSS_ESC0_CLK>;
power-domains = <&gcc MDSS_GDSC>;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&gpio_keys_default>;
pinctrl-names = "default";
key-volup {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
debounce-interval = <15>;
};
};
vph_pwr: regulator-vph-pwr {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-boot-on;
};
reserved-memory {
qseecom_mem: qseecom@84a00000 {
reg = <0x0 0x84a00000 0x0 0x1900000>;
no-map;
};
framebuffer_mem: memory@90001000 {
reg = <0x0 0x90001000 0x0 (720 * 1280 * 3)>;
no-map;
};
};
};
&blsp1_i2c3 {
status = "okay";
touchscreen@38 {
compatible = "edt,edt-ft5306";
reg = <0x38>;
interrupts-extended = <&tlmm 65 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&tsp_int_rst_default>;
pinctrl-names = "default";
vcc-supply = <&pm8937_l10>;
iovcc-supply = <&pm8937_l5>;
touchscreen-size-x = <720>;
touchscreen-size-y = <1280>;
};
};
&blsp2_i2c1 {
status = "okay";
bq27426@55 {
compatible = "ti,bq27426";
reg = <0x55>;
monitored-battery = <&battery>;
};
bq25601@6b{
compatible = "ti,bq25601";
reg = <0x6b>;
interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&bq25601_int_default>;
pinctrl-names = "default";
input-voltage-limit-microvolt = <4400000>;
input-current-limit-microamp = <1000000>;
monitored-battery = <&battery>;
};
};
&pm8937_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&rpm_requests {
regulators-0 {
compatible = "qcom,rpm-pm8937-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_s2-supply = <&vph_pwr>;
vdd_s3-supply = <&vph_pwr>;
vdd_s4-supply = <&vph_pwr>;
vdd_l1_l19-supply = <&pm8937_s3>;
vdd_l2_l23-supply = <&pm8937_s3>;
vdd_l3-supply = <&pm8937_s3>;
vdd_l4_l5_l6_l7_l16-supply = <&pm8937_s4>;
vdd_l8_l11_l12_l17_l22-supply = <&vph_pwr>;
vdd_l9_l10_l13_l14_l15_l18-supply = <&vph_pwr>;
pm8937_s1: s1 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1225000>;
};
pm8937_s3: s3 {
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
};
pm8937_s4: s4 {
regulator-min-microvolt = <2050000>;
regulator-max-microvolt = <2050000>;
};
pm8937_l2: l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
pm8937_l5: l5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8937_l6: l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8937_l7: l7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8937_l8: l8 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2900000>;
};
pm8937_l9: l9 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
};
pm8937_l10: l10 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3000000>;
};
pm8937_l11: l11 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
regulator-system-load = <200000>;
};
pm8937_l12: l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
pm8937_l13: l13 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
};
pm8937_l14: l14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
pm8937_l15: l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
pm8937_l16: l16 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8937_l17: l17 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2900000>;
};
pm8937_l19: l19 {
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1350000>;
};
pm8937_l22: l22 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
pm8937_l23: l23 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
};
};
&sdhc_1 {
vmmc-supply = <&pm8937_l8>;
vqmmc-supply = <&pm8937_l5>;
status = "okay";
};
&sdhc_2 {
cd-gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
vmmc-supply = <&pm8937_l11>;
vqmmc-supply = <&pm8937_l12>;
pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
pinctrl-names = "default", "sleep";
status = "okay";
};
&sleep_clk {
clock-frequency = <32768>;
};
&tlmm {
bq25601_int_default: bq25601-int-default-state {
pins = "gpio61";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
gpio_keys_default: gpio-keys-default-state {
pins = "gpio91";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
sdc2_cd_default: sdc2-cd-default-state {
pins = "gpio67";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tsp_int_rst_default: tsp-int-rst-default-state {
pins = "gpio64", "gpio65";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
&wcnss {
vddpx-supply = <&pm8937_l5>;
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
vddxo-supply = <&pm8937_l7>;
vddrfa-supply = <&pm8937_l19>;
vddpa-supply = <&pm8937_l9>;
vdddig-supply = <&pm8937_l5>;
};
&wcnss_mem {
status = "okay";
};
&xo_board {
clock-frequency = <19200000>;
};

1954
arch/arm64/boot/dts/qcom/msm8917.dtsi Normal file
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File diff suppressed because it is too large Load Diff

2
arch/arm64/boot/dts/qcom/msm8939.dtsi
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@ -34,7 +34,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-frequency = <32764>;
};
};

21
arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts
View File

@ -2,12 +2,13 @@
/*
* Copyright (c) 2015, Huawei Inc. All rights reserved.
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2023, Petr Vorel <petr.vorel@gmail.com>
* Copyright (c) 2021-2024, Petr Vorel <petr.vorel@gmail.com>
*/
/dts-v1/;
#include "msm8994.dtsi"
#include "pm8994.dtsi"
/ {
model = "Huawei Nexus 6P";
@ -46,6 +47,24 @@
no-map;
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
button-vol-up {
label = "volume up";
gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
wakeup-source;
debounce-interval = <15>;
};
};
};
&pm8994_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&blsp1_uart2 {

5
arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi
View File

@ -387,11 +387,6 @@
interrupts = <&tlmm 96 IRQ_TYPE_EDGE_FALLING>;
button_num = <8>;
touchpad_num = <0>;
wheel_num = <0>;
slider_num = <0>;
vcc-supply = <&vreg_l18a_2p85>;
};

11
arch/arm64/boot/dts/qcom/msm8994.dtsi
View File

@ -34,7 +34,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-frequency = <32764>;
clock-output-names = "sleep_clk";
};
};
@ -437,6 +437,15 @@
#size-cells = <1>;
ranges;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"qusb2_phy",
"hs_phy_irq",
"ss_phy_irq";
clocks = <&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
<&gcc GCC_USB30_SLEEP_CLK>,

2
arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts
View File

@ -64,7 +64,7 @@
};
led@1 {
reg = <0>;
reg = <1>;
chan-name = "button-backlight1";
led-cur = /bits/ 8 <0x32>;
max-cur = /bits/ 8 <0xc8>;

9
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@ -3065,9 +3065,14 @@
#size-cells = <1>;
ranges;
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq";
interrupt-names = "pwr_event",
"qusb2_phy",
"hs_phy_irq",
"ss_phy_irq";
clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>,

6
arch/arm64/boot/dts/qcom/pm660l.dtsi
View File

@ -70,6 +70,12 @@
status = "disabled";
};
pm660l_flash: led-controller@d300 {
compatible = "qcom,pm660l-flash-led", "qcom,spmi-flash-led";
reg = <0xd300>;
status = "disabled";
};
pm660l_wled: leds@d800 {
compatible = "qcom,pm660l-wled";
reg = <0xd800>, <0xd900>;

2
arch/arm64/boot/dts/qcom/pm8150.dtsi
View File

@ -49,8 +49,6 @@
pon: pon@800 {
compatible = "qcom,pm8998-pon";
reg = <0x0800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pon_pwrkey: pwrkey {
compatible = "qcom,pm8941-pwrkey";

150
arch/arm64/boot/dts/qcom/pm8937.dtsi Normal file
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@ -0,0 +1,150 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023, Dang Huynh <danct12@riseup.net>
*/
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pm8937-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm8937_temp>;
trips {
trip0 {
temperature = <105000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <125000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pmic@0 {
compatible = "qcom,pm8937", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pm8937_pwrkey: pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_POWER>;
};
pm8937_resin: resin {
compatible = "qcom,pm8941-resin";
interrupts = <0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
status = "disabled";
};
};
pm8937_gpios: gpio@c000 {
compatible = "qcom,pm8937-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pm8937_gpios 0 0 8>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pm8937_mpps: mpps@a000 {
compatible = "qcom,pm8937-mpp", "qcom,spmi-mpp";
reg = <0xa000>;
gpio-controller;
gpio-ranges = <&pm8937_mpps 0 0 4>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pm8937_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
io-channels = <&pm8937_vadc VADC_DIE_TEMP>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
pm8937_vadc: adc@3100 {
compatible = "qcom,spmi-vadc";
reg = <0x3100>;
interrupts = <0 0x31 0 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@8 {
reg = <VADC_DIE_TEMP>;
};
channel@9 {
reg = <VADC_REF_625MV>;
};
channel@a {
reg = <VADC_REF_1250MV>;
};
channel@c {
reg = <VADC_SPARE1>;
};
channel@e {
reg = <VADC_GND_REF>;
};
channel@f {
reg = <VADC_VDD_VADC>;
};
};
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>, <0x6100>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
};
pmic@1 {
compatible = "qcom,pm8937", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8937_spmi_regulators: regulators {
compatible = "qcom,pm8937-regulators";
};
};
};

62
arch/arm64/boot/dts/qcom/pmd8028.dtsi Normal file
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@ -0,0 +1,62 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pmd8028-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmd8028_temp_alarm>;
trips {
pmd8028_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pmd8028_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
pmd8028_trip2: trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pmd8028: pmic@4 {
compatible = "qcom,pmd8028", "qcom,spmi-pmic";
reg = <0x4 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmd8028_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmd8028_gpios: gpio@8800 {
compatible = "qcom,pmd8028-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmd8028_gpios 0 0 4>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

17
arch/arm64/boot/dts/qcom/pmi8950.dtsi
View File

@ -84,6 +84,23 @@
#address-cells = <1>;
#size-cells = <0>;
labibb {
compatible = "qcom,pmi8950-lab-ibb",
"qcom,pmi8998-lab-ibb";
ibb: ibb {
interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>,
<0x3 0xdc 0x0 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sc-err", "ocp";
};
lab: lab {
interrupts = <0x3 0xde 0x1 IRQ_TYPE_EDGE_RISING>,
<0x3 0xde 0x0 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sc-err", "ocp";
};
};
pmi8950_pwm: pwm {
compatible = "qcom,pmi8950-pwm";
#pwm-cells = <2>;

68
arch/arm64/boot/dts/qcom/pmih0108.dtsi Normal file
View File

@ -0,0 +1,68 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pmih0108-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmih0108_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pmih0108: pmic@7 {
compatible = "qcom,pmih0108", "qcom,spmi-pmic";
reg = <0x7 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmih0108_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmih0108_gpios: gpio@8800 {
compatible = "qcom,pmih0108-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmih0108_gpios 0 0 18>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pmih0108_eusb2_repeater: phy@fd00 {
compatible = "qcom,pm8550b-eusb2-repeater";
reg = <0xfd00>;
#phy-cells = <0>;
};
};
};

72
arch/arm64/boot/dts/qcom/pmk8350.dtsi
View File

@ -76,6 +76,14 @@
status = "disabled";
};
pmk8350_sdam_1: nvram@7000 {
compatible = "qcom,spmi-sdam";
reg = <0x7000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x7000 0x100>;
};
pmk8350_sdam_2: nvram@7100 {
compatible = "qcom,spmi-sdam";
reg = <0x7100>;
@ -89,6 +97,70 @@
};
};
pmk8350_sdam_5: nvram@7400 {
compatible = "qcom,spmi-sdam";
reg = <0x7400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x7400 0x100>;
};
pmk8350_sdam_13: nvram@7c00 {
compatible = "qcom,spmi-sdam";
reg = <0x7c00>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x7c00 0x100>;
};
pmk8350_sdam_14: nvram@7d00 {
compatible = "qcom,spmi-sdam";
reg = <0x7d00>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x7d00 0x100>;
};
pmk8350_sdam_21: nvram@8400 {
compatible = "qcom,spmi-sdam";
reg = <0x8400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8400 0x100>;
};
pmk8350_sdam_22: nvram@8500 {
compatible = "qcom,spmi-sdam";
reg = <0x8500>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8500 0x100>;
};
pmk8350_sdam_23: nvram@8600 {
compatible = "qcom,spmi-sdam";
reg = <0x8600>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8600 0x100>;
};
pmk8350_sdam_41: nvram@9800 {
compatible = "qcom,spmi-sdam";
reg = <0x9800>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x9800 0x100>;
};
pmk8350_sdam_46: nvram@9d00 {
compatible = "qcom,spmi-sdam";
reg = <0x9d00>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x9d00 0x100>;
};
pmk8350_gpios: gpio@b000 {
compatible = "qcom,pmk8350-gpio", "qcom,spmi-gpio";
reg = <0xb000>;

101
arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
View File

@ -108,6 +108,36 @@
};
};
vreg_afvdd_2p8: regulator-afvdd-2p8 {
compatible = "regulator-fixed";
regulator-name = "AFVDD_2P8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&tlmm 68 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vreg_bob>;
};
vreg_ois_avdd0_1p8: regulator-ois-avdd0-1p8 {
compatible = "regulator-fixed";
regulator-name = "OIS_AVDD0_1P8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&tlmm 157 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vreg_bob>;
};
vreg_ois_dvdd_1p1: regulator-ois-dvdd-1p1 {
compatible = "regulator-fixed";
regulator-name = "OIS_DVDD_1P1";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
gpio = <&tlmm 97 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vreg_s8b>;
};
reserved-memory {
cont_splash_mem: cont-splash@e1000000 {
reg = <0x0 0xe1000000 0x0 0x2300000>;
@ -134,36 +164,6 @@
};
};
ois_avdd0_1p8: regulator-ois-avdd0-1p8 {
compatible = "regulator-fixed";
regulator-name = "OIS_AVDD0_1P8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&tlmm 157 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vreg_bob>;
};
ois_dvdd_1p1: regulator-ois-dvdd-1p1 {
compatible = "regulator-fixed";
regulator-name = "OIS_DVDD_1P1";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
gpio = <&tlmm 97 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vreg_s8b>;
};
afvdd_2p8: regulator-afvdd-2p8 {
compatible = "regulator-fixed";
regulator-name = "AFVDD_2P8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&tlmm 68 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vreg_bob>;
};
thermal-zones {
camera-thermal {
polling-delay-passive = <0>;
@ -556,6 +556,47 @@
};
};
&cci0 {
status = "okay";
};
&cci0_i2c0 {
/* IMX800 @ 1a */
eeprom@50 {
compatible = "puya,p24c256c", "atmel,24c256";
reg = <0x50>;
vcc-supply = <&vreg_l6p>;
read-only;
};
};
&cci0_i2c1 {
/* IMX858 @ 29 */
eeprom@54 {
compatible = "giantec,gt24p128f", "atmel,24c128";
reg = <0x54>;
vcc-supply = <&vreg_l6p>;
read-only;
};
};
&cci1 {
status = "okay";
};
&cci1_i2c1 {
/* S5KJN1SQ03 @ 10 */
eeprom@51 {
compatible = "giantec,gt24p128f", "atmel,24c128";
reg = <0x51>;
vcc-supply = <&vreg_l6p>;
read-only;
};
};
&dispcc {
/* Disable for now so simple-framebuffer continues working */
status = "disabled";

8
arch/arm64/boot/dts/qcom/qcm6490-idp.dts
View File

@ -258,6 +258,8 @@
regulator-name = "vreg_l6b_1p2";
regulator-min-microvolt = <1140000>;
regulator-max-microvolt = <1260000>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
@ -265,6 +267,8 @@
regulator-name = "vreg_l7b_2p952";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3544000>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
@ -279,6 +283,8 @@
regulator-name = "vreg_l9b_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1304000>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
@ -467,6 +473,8 @@
regulator-name = "vreg_l10c_0p88";
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <1050000>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};

2
arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts
View File

@ -942,8 +942,6 @@
qcom,squelch-detector-bp = <(-2090)>;
orientation-switch;
status = "okay";
};

6
arch/arm64/boot/dts/qcom/qcs404.dtsi
View File

@ -28,7 +28,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-frequency = <32764>;
};
};
@ -694,6 +694,8 @@
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
snps,usb3_lpm_capable;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
dr_mode = "otg";
};
};
@ -731,6 +733,8 @@
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
snps,usb3_lpm_capable;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
dr_mode = "peripheral";
};
};

343
arch/arm64/boot/dts/qcom/qcs615-ride.dts Normal file
View File

@ -0,0 +1,343 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/gpio/gpio.h>
#include "qcs615.dtsi"
#include "pm8150.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QCS615 Ride";
compatible = "qcom,qcs615-ride", "qcom,qcs615";
chassis-type = "embedded";
aliases {
mmc0 = &sdhc_1;
mmc1 = &sdhc_2;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
clocks {
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
#clock-cells = <0>;
};
xo_board_clk: xo-board-clk {
compatible = "fixed-clock";
clock-frequency = <38400000>;
#clock-cells = <0>;
};
};
regulator-usb2-vbus {
compatible = "regulator-fixed";
regulator-name = "USB2_VBUS";
gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&usb2_en>;
pinctrl-names = "default";
enable-active-high;
regulator-always-on;
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pm8150-rpmh-regulators";
qcom,pmic-id = "a";
vreg_s3a: smps3 {
regulator-name = "vreg_s3a";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <650000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s4a: smps4 {
regulator-name = "vreg_s4a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1829000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s5a: smps5 {
regulator-name = "vreg_s5a";
regulator-min-microvolt = <1896000>;
regulator-max-microvolt = <2040000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s6a: smps6 {
regulator-name = "vreg_s6a";
regulator-min-microvolt = <1304000>;
regulator-max-microvolt = <1404000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1a: ldo1 {
regulator-name = "vreg_l1a";
regulator-min-microvolt = <488000>;
regulator-max-microvolt = <852000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2a: ldo2 {
regulator-name = "vreg_l2a";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <3100000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3a: ldo3 {
regulator-name = "vreg_l3a";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1248000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5a: ldo5 {
regulator-name = "vreg_l5a";
regulator-min-microvolt = <875000>;
regulator-max-microvolt = <975000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a: ldo7 {
regulator-name = "vreg_l7a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1900000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8a: ldo8 {
regulator-name = "vreg_l8a";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1350000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10a: ldo10 {
regulator-name = "vreg_l10a";
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11a: ldo11 {
regulator-name = "vreg_l11a";
regulator-min-microvolt = <1232000>;
regulator-max-microvolt = <1260000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12a: ldo12 {
regulator-name = "vreg_l12a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1890000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13a: ldo13 {
regulator-name = "vreg_l13a";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3230000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l15a: ldo15 {
regulator-name = "vreg_l15a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1904000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l16a: ldo16 {
regulator-name = "vreg_l16a";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l17a: ldo17 {
regulator-name = "vreg_l17a";
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
};
&gcc {
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
};
&pm8150_gpios {
usb2_en: usb2-en-state {
pins = "gpio10";
function = "normal";
output-enable;
power-source = <0>;
};
};
&pon_pwrkey {
status = "okay";
};
&pon_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&qupv3_id_0 {
status = "okay";
};
&rpmhcc {
clocks = <&xo_board_clk>;
};
&sdhc_1 {
pinctrl-0 = <&sdc1_state_on>;
pinctrl-1 = <&sdc1_state_off>;
pinctrl-names = "default", "sleep";
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
vmmc-supply = <&vreg_l17a>;
vqmmc-supply = <&vreg_s4a>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
&sdhc_2 {
pinctrl-0 = <&sdc2_state_on>;
pinctrl-1 = <&sdc2_state_off>;
pinctrl-names = "default", "sleep";
bus-width = <4>;
cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vreg_l10a>;
vqmmc-supply = <&vreg_s4a>;
status = "okay";
};
&uart0 {
status = "okay";
};
&usb_1_hsphy {
vdd-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l12a>;
vdda-phy-dpdm-supply = <&vreg_l13a>;
status = "okay";
};
&usb_qmpphy {
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l12a>;
status = "okay";
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "peripheral";
};
&usb_hsphy_2 {
vdd-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l12a>;
vdda-phy-dpdm-supply = <&vreg_l13a>;
status = "okay";
};
&usb_2 {
status = "okay";
};
&usb_2_dwc3 {
dr_mode = "host";
};
&ufs_mem_hc {
reset-gpios = <&tlmm 123 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l17a>;
vcc-max-microamp = <600000>;
vccq2-supply = <&vreg_s4a>;
vccq2-max-microamp = <600000>;
status = "okay";
};
&ufs_mem_phy {
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l12a>;
status = "okay";
};
&watchdog {
clocks = <&sleep_clk>;
};

3670
arch/arm64/boot/dts/qcom/qcs615.dtsi Normal file
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File diff suppressed because it is too large Load Diff

41
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
View File

@ -9,6 +9,7 @@
#define PM7250B_SID 8
#define PM7250B_SID1 9
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sc7280.dtsi"
@ -744,6 +745,46 @@
};
};
&pm8350c_pwm {
nvmem = <&pmk8350_sdam_21>,
<&pmk8350_sdam_22>;
nvmem-names = "lpg_chan_sdam",
"lut_sdam";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <3>;
linux,default-trigger = "none";
default-state = "off";
panic-indicator;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <2>;
linux,default-trigger = "none";
default-state = "off";
};
led@3 {
reg = <3>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <1>;
linux,default-trigger = "none";
default-state = "off";
};
};
&pmk8350_rtc {
status = "okay";
};

370
arch/arm64/boot/dts/qcom/qcs8300-ride.dts Normal file
View File

@ -0,0 +1,370 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "qcs8300.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QCS8300 Ride";
compatible = "qcom,qcs8300-ride", "qcom,qcs8300";
chassis-type = "embedded";
aliases {
serial0 = &uart7;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "a";
vreg_s4a: smps4 {
regulator-name = "vreg_s4a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s9a: smps9 {
regulator-name = "vreg_s9a";
regulator-min-microvolt = <1352000>;
regulator-max-microvolt = <1352000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3a: ldo3 {
regulator-name = "vreg_l3a";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4a: ldo4 {
regulator-name = "vreg_l4a";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5a: ldo5 {
regulator-name = "vreg_l5a";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6a: ldo6 {
regulator-name = "vreg_l6a";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a: ldo7 {
regulator-name = "vreg_l7a";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8a: ldo8 {
regulator-name = "vreg_l8a";
regulator-min-microvolt = <2504000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9a: ldo9 {
regulator-name = "vreg_l9a";
regulator-min-microvolt = <2970000>;
regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-1 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "c";
vreg_s5c: smps5 {
regulator-name = "vreg_s5c";
regulator-min-microvolt = <1104000>;
regulator-max-microvolt = <1104000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1c: ldo1 {
regulator-name = "vreg_l1c";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <500000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2c: ldo2 {
regulator-name = "vreg_l2c";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <904000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4c: ldo4 {
regulator-name = "vreg_l4c";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6c: ldo6 {
regulator-name = "vreg_l6c";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c: ldo7 {
regulator-name = "vreg_l7c";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8c: ldo8 {
regulator-name = "vreg_l8c";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9c: ldo9 {
regulator-name = "vreg_l9c";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
};
};
&ethernet0 {
phy-mode = "2500base-x";
phy-handle = <&phy0>;
pinctrl-0 = <&ethernet0_default>;
pinctrl-names = "default";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,ps-speed = <1000>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@8 {
compatible = "ethernet-phy-id31c3.1c33";
reg = <0x8>;
device_type = "ethernet-phy";
interrupts-extended = <&tlmm 4 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
snps,route-ptp;
};
queue2 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x2>;
snps,route-avcp;
};
queue3 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x3>;
snps,priority = <0xc>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <4>;
snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
queue3 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
};
};
&qupv3_id_0 {
status = "okay";
};
&remoteproc_adsp {
firmware-name = "qcom/qcs8300/adsp.mbn";
status = "okay";
};
&remoteproc_cdsp {
firmware-name = "qcom/qcs8300/cdsp0.mbn";
status = "okay";
};
&remoteproc_gpdsp {
firmware-name = "qcom/qcs8300/gpdsp0.mbn";
status = "okay";
};
&serdes0 {
phy-supply = <&vreg_l5a>;
status = "okay";
};
&tlmm {
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {
pins = "gpio5";
function = "emac0_mdc";
drive-strength = <16>;
bias-pull-up;
};
ethernet0_mdio: ethernet0-mdio-pins {
pins = "gpio6";
function = "emac0_mdio";
drive-strength = <16>;
bias-pull-up;
};
};
};
&uart7 {
status = "okay";
};
&ufs_mem_hc {
reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l8a>;
vcc-max-microamp = <1100000>;
vccq-supply = <&vreg_l4c>;
vccq-max-microamp = <1200000>;
status = "okay";
};
&ufs_mem_phy {
vdda-phy-supply = <&vreg_l4a>;
vdda-pll-supply = <&vreg_l5a>;
status = "okay";
};
&usb_1_hsphy {
vdda-pll-supply = <&vreg_l7a>;
vdda18-supply = <&vreg_l7c>;
vdda33-supply = <&vreg_l9a>;
status = "okay";
};
&usb_qmpphy {
vdda-phy-supply = <&vreg_l7a>;
vdda-pll-supply = <&vreg_l5a>;
status = "okay";
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "peripheral";
};

3548
arch/arm64/boot/dts/qcom/qcs8300.dtsi Normal file
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File diff suppressed because it is too large Load Diff

2
arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
View File

@ -367,7 +367,7 @@
};
&sleep_clk {
clock-frequency = <32000>;
clock-frequency = <32764>;
};
&ufs_mem_hc {

19
arch/arm64/boot/dts/qcom/qdu1000-idp.dts
View File

@ -22,20 +22,6 @@
stdout-path = "serial0:115200n8";
};
clocks {
xo_board: xo-board-clk {
compatible = "fixed-clock";
clock-frequency = <19200000>;
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
#clock-cells = <0>;
};
};
ppvar_sys: ppvar-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "ppvar_sys";
@ -239,6 +225,11 @@
};
};
&pon {
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
};
&qup_i2c1_data_clk {
drive-strength = <2>;
bias-pull-up;

16
arch/arm64/boot/dts/qcom/qdu1000.dtsi
View File

@ -21,6 +21,20 @@
chosen: chosen { };
clocks {
xo_board: xo-board-clk {
compatible = "fixed-clock";
clock-frequency = <19200000>;
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32764>;
#clock-cells = <0>;
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
@ -1009,6 +1023,8 @@
iommus = <&apps_smmu 0xc0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_1_hsphy>,
<&usb_1_qmpphy>;
phy-names = "usb2-phy",

61
arch/arm64/boot/dts/qcom/qrb4210-rb2.dts
View File

@ -6,6 +6,8 @@
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
#include <dt-bindings/usb/pd.h>
#include "sm4250.dtsi"
#include "pm6125.dtsi"
@ -103,6 +105,55 @@
};
};
sound {
compatible = "qcom,qrb4210-rb2-sndcard";
pinctrl-0 = <&lpi_i2s2_active>;
pinctrl-names = "default";
model = "Qualcomm-RB2-WSA8815-Speakers-DMIC0";
audio-routing = "MM_DL1", "MultiMedia1 Playback",
"MM_DL2", "MultiMedia2 Playback";
mm1-dai-link {
link-name = "MultiMedia1";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
};
};
mm2-dai-link {
link-name = "MultiMedia2";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
};
};
mm3-dai-link {
link-name = "MultiMedia3";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
};
};
hdmi-dai-link {
link-name = "HDMI Playback";
cpu {
sound-dai = <&q6afedai SECONDARY_MI2S_RX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&lt9611_codec 0>;
};
};
};
vreg_hdmi_out_1p2: regulator-hdmi-out-1p2 {
compatible = "regulator-fixed";
regulator-name = "VREG_HDMI_OUT_1P2";
@ -318,6 +369,14 @@
status = "okay";
};
/* SECONDARY I2S uses 1 I2S SD Line for audio on LT9611UXC HDMI Bridge */
&q6afedai {
dai@20 {
reg = <SECONDARY_MI2S_RX>;
qcom,sd-lines = <0>;
};
};
&qupv3_id_0 {
status = "okay";
};
@ -545,7 +604,7 @@
};
&sleep_clk {
clock-frequency = <32000>;
clock-frequency = <32764>;
};
&tlmm {

5
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
View File

@ -964,6 +964,11 @@
};
};
&pon {
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
};
&pon_pwrkey {
status = "okay";
};

19
arch/arm64/boot/dts/qcom/qru1000-idp.dts
View File

@ -22,20 +22,6 @@
stdout-path = "serial0:115200n8";
};
clocks {
xo_board: xo-board-clk {
compatible = "fixed-clock";
clock-frequency = <19200000>;
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
#clock-cells = <0>;
};
};
ppvar_sys: ppvar-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "ppvar_sys";
@ -239,6 +225,11 @@
};
};
&pon {
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
};
&qup_i2c1_data_clk {
drive-strength = <2>;
bias-pull-up;

82
arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi
View File

@ -104,6 +104,30 @@
};
};
};
dp0-connector {
compatible = "dp-connector";
label = "eDP0";
type = "full-size";
port {
dp0_connector_in: endpoint {
remote-endpoint = <&mdss0_dp0_out>;
};
};
};
dp1-connector {
compatible = "dp-connector";
label = "eDP1";
type = "full-size";
port {
dp1_connector_in: endpoint {
remote-endpoint = <&mdss0_dp1_out>;
};
};
};
};
&apps_rsc {
@ -498,6 +522,50 @@
status = "okay";
};
&mdss0 {
status = "okay";
};
&mdss0_dp0 {
pinctrl-0 = <&dp0_hot_plug_det>;
pinctrl-names = "default";
status = "okay";
};
&mdss0_dp0_out {
data-lanes = <0 1 2 3>;
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
remote-endpoint = <&dp0_connector_in>;
};
&mdss0_dp0_phy {
vdda-phy-supply = <&vreg_l1c>;
vdda-pll-supply = <&vreg_l4a>;
status = "okay";
};
&mdss0_dp1 {
pinctrl-0 = <&dp1_hot_plug_det>;
pinctrl-names = "default";
status = "okay";
};
&mdss0_dp1_out {
data-lanes = <0 1 2 3>;
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
remote-endpoint = <&dp1_connector_in>;
};
&mdss0_dp1_phy {
vdda-phy-supply = <&vreg_l1c>;
vdda-pll-supply = <&vreg_l4a>;
status = "okay";
};
&pmm8654au_0_gpios {
gpio-line-names = "DS_EN",
"POFF_COMPLETE",
@ -608,7 +676,7 @@
};
&sleep_clk {
clock-frequency = <32764>;
clock-frequency = <32000>;
};
&spi16 {
@ -618,6 +686,18 @@
};
&tlmm {
dp0_hot_plug_det: dp0-hot-plug-det-state {
pins = "gpio101";
function = "edp0_hot";
bias-disable;
};
dp1_hot_plug_det: dp1-hot-plug-det-state {
pins = "gpio102";
function = "edp1_hot";
bias-disable;
};
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {
pins = "gpio8";

406
arch/arm64/boot/dts/qcom/sa8775p.dtsi
View File

@ -7,6 +7,7 @@
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
#include <dt-bindings/dma/qcom-gpi.h>
@ -44,6 +45,8 @@
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <1024>;
@ -66,6 +69,8 @@
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
@ -83,6 +88,8 @@
compatible = "qcom,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&l2_2>;
capacity-dmips-mhz = <1024>;
@ -100,6 +107,8 @@
compatible = "qcom,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&l2_3>;
capacity-dmips-mhz = <1024>;
@ -117,6 +126,8 @@
compatible = "qcom,kryo";
reg = <0x0 0x10000>;
enable-method = "psci";
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&l2_4>;
capacity-dmips-mhz = <1024>;
@ -140,6 +151,8 @@
compatible = "qcom,kryo";
reg = <0x0 0x10100>;
enable-method = "psci";
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&l2_5>;
capacity-dmips-mhz = <1024>;
@ -157,6 +170,8 @@
compatible = "qcom,kryo";
reg = <0x0 0x10200>;
enable-method = "psci";
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&l2_6>;
capacity-dmips-mhz = <1024>;
@ -174,6 +189,8 @@
compatible = "qcom,kryo";
reg = <0x0 0x10300>;
enable-method = "psci";
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&l2_7>;
capacity-dmips-mhz = <1024>;
@ -854,8 +871,8 @@
#mbox-cells = <2>;
};
gpi_dma2: qcom,gpi-dma@800000 {
compatible = "qcom,sm6350-gpi-dma";
gpi_dma2: dma-controller@800000 {
compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x00800000 0x0 0x60000>;
#dma-cells = <3>;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
@ -1345,8 +1362,8 @@
};
gpi_dma0: qcom,gpi-dma@900000 {
compatible = "qcom,sm6350-gpi-dma";
gpi_dma0: dma-controller@900000 {
compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x00900000 0x0 0x60000>;
#dma-cells = <3>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
@ -1770,8 +1787,8 @@
};
};
gpi_dma1: qcom,gpi-dma@a00000 {
compatible = "qcom,sm6350-gpi-dma";
gpi_dma1: dma-controller@a00000 {
compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x00a00000 0x0 0x60000>;
#dma-cells = <3>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
@ -2225,8 +2242,8 @@
};
};
gpi_dma3: qcom,gpi-dma@b00000 {
compatible = "qcom,sm6350-gpi-dma";
gpi_dma3: dma-controller@b00000 {
compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x00b00000 0x0 0x58000>;
#dma-cells = <3>;
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
@ -3411,6 +3428,8 @@
iommus = <&apps_smmu 0x080 0x0>;
phys = <&usb_0_hsphy>, <&usb_0_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
};
};
@ -3500,6 +3519,8 @@
iommus = <&apps_smmu 0x0a0 0x0>;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
};
};
@ -3563,6 +3584,8 @@
iommus = <&apps_smmu 0x020 0x0>;
phys = <&usb_2_hsphy>;
phy-names = "usb2-phy";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
};
};
@ -3759,6 +3782,353 @@
interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
};
videocc: clock-controller@abf0000 {
compatible = "qcom,sa8775p-videocc";
reg = <0x0 0x0abf0000 0x0 0x10000>;
clocks = <&gcc GCC_VIDEO_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
power-domains = <&rpmhpd SA8775P_MMCX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
camcc: clock-controller@ade0000 {
compatible = "qcom,sa8775p-camcc";
reg = <0x0 0x0ade0000 0x0 0x20000>;
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
power-domains = <&rpmhpd SA8775P_MMCX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
mdss0: display-subsystem@ae00000 {
compatible = "qcom,sa8775p-mdss";
reg = <0x0 0x0ae00000 0x0 0x1000>;
reg-names = "mdss";
/* same path used twice */
interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "mdp0-mem",
"mdp1-mem",
"cpu-cfg";
resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>;
power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>;
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
iommus = <&apps_smmu 0x1000 0x402>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
mdss0_mdp: display-controller@ae01000 {
compatible = "qcom,sa8775p-dpu";
reg = <0x0 0x0ae01000 0x0 0x8f000>,
<0x0 0x0aeb0000 0x0 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus",
"iface",
"lut",
"core",
"vsync";
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdss0_mdp_opp_table>;
power-domains = <&rpmhpd SA8775P_MMCX>;
interrupt-parent = <&mdss0>;
interrupts = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf0_out: endpoint {
remote-endpoint = <&mdss0_dp0_in>;
};
};
port@1 {
reg = <1>;
dpu_intf4_out: endpoint {
remote-endpoint = <&mdss0_dp1_in>;
};
};
};
mdss0_mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-375000000 {
opp-hz = /bits/ 64 <375000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
required-opps = <&rpmhpd_opp_nom>;
};
opp-575000000 {
opp-hz = /bits/ 64 <575000000>;
required-opps = <&rpmhpd_opp_turbo>;
};
opp-650000000 {
opp-hz = /bits/ 64 <650000000>;
required-opps = <&rpmhpd_opp_turbo_l1>;
};
};
};
mdss0_dp0_phy: phy@aec2a00 {
compatible = "qcom,sa8775p-edp-phy";
reg = <0x0 0x0aec2a00 0x0 0x200>,
<0x0 0x0aec2200 0x0 0xd0>,
<0x0 0x0aec2600 0x0 0xd0>,
<0x0 0x0aec2000 0x0 0x1c8>;
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
clock-names = "aux",
"cfg_ahb";
#clock-cells = <1>;
#phy-cells = <0>;
status = "disabled";
};
mdss0_dp1_phy: phy@aec5a00 {
compatible = "qcom,sa8775p-edp-phy";
reg = <0x0 0x0aec5a00 0x0 0x200>,
<0x0 0x0aec5200 0x0 0xd0>,
<0x0 0x0aec5600 0x0 0xd0>,
<0x0 0x0aec5000 0x0 0x1c8>;
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
clock-names = "aux",
"cfg_ahb";
#clock-cells = <1>;
#phy-cells = <0>;
status = "disabled";
};
mdss0_dp0: displayport-controller@af54000 {
compatible = "qcom,sa8775p-dp";
reg = <0x0 0x0af54000 0x0 0x104>,
<0x0 0x0af54200 0x0 0x0c0>,
<0x0 0x0af55000 0x0 0x770>,
<0x0 0x0af56000 0x0 0x09c>,
<0x0 0x0af57000 0x0 0x09c>;
interrupt-parent = <&mdss0>;
interrupts = <12>;
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
phys = <&mdss0_dp0_phy>;
phy-names = "dp";
operating-points-v2 = <&dp_opp_table>;
power-domains = <&rpmhpd SA8775P_MMCX>;
#sound-dai-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss0_dp0_in: endpoint {
remote-endpoint = <&dpu_intf0_out>;
};
};
port@1 {
reg = <1>;
mdss0_dp0_out: endpoint { };
};
};
dp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-270000000 {
opp-hz = /bits/ 64 <270000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-810000000 {
opp-hz = /bits/ 64 <810000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
mdss0_dp1: displayport-controller@af5c000 {
compatible = "qcom,sa8775p-dp";
reg = <0x0 0x0af5c000 0x0 0x104>,
<0x0 0x0af5c200 0x0 0x0c0>,
<0x0 0x0af5d000 0x0 0x770>,
<0x0 0x0af5e000 0x0 0x09c>,
<0x0 0x0af5f000 0x0 0x09c>;
interrupt-parent = <&mdss0>;
interrupts = <13>;
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>;
phys = <&mdss0_dp1_phy>;
phy-names = "dp";
operating-points-v2 = <&dp1_opp_table>;
power-domains = <&rpmhpd SA8775P_MMCX>;
#sound-dai-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss0_dp1_in: endpoint {
remote-endpoint = <&dpu_intf4_out>;
};
};
port@1 {
reg = <1>;
mdss0_dp1_out: endpoint { };
};
};
dp1_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-270000000 {
opp-hz = /bits/ 64 <270000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-810000000 {
opp-hz = /bits/ 64 <810000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
};
dispcc0: clock-controller@af00000 {
compatible = "qcom,sa8775p-dispcc0";
reg = <0x0 0x0af00000 0x0 0x20000>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>,
<&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>,
<0>, <0>, <0>, <0>;
power-domains = <&rpmhpd SA8775P_MMCX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sa8775p-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x30000>,
@ -4381,6 +4751,22 @@
};
};
dispcc1: clock-controller@22100000 {
compatible = "qcom,sa8775p-dispcc1";
reg = <0x0 0x22100000 0x0 0x20000>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<0>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>;
power-domains = <&rpmhpd SA8775P_MMCX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
status = "disabled";
};
ethernet1: ethernet@23000000 {
compatible = "qcom,sa8775p-ethqos";
reg = <0x0 0x23000000 0x0 0x10000>,
@ -6092,7 +6478,7 @@
<0x0 0x40000000 0x0 0xf20>,
<0x0 0x40000f20 0x0 0xa8>,
<0x0 0x40001000 0x0 0x4000>,
<0x0 0x40200000 0x0 0x100000>,
<0x0 0x40200000 0x0 0x1fe00000>,
<0x0 0x01c03000 0x0 0x1000>,
<0x0 0x40005000 0x0 0x2000>;
reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
@ -6250,7 +6636,7 @@
<0x0 0x60000000 0x0 0xf20>,
<0x0 0x60000f20 0x0 0xa8>,
<0x0 0x60001000 0x0 0x4000>,
<0x0 0x60200000 0x0 0x100000>,
<0x0 0x60200000 0x0 0x1fe00000>,
<0x0 0x01c13000 0x0 0x1000>,
<0x0 0x60005000 0x0 0x2000>;
reg-names = "parf", "dbi", "elbi", "atu", "addr_space",

558
arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts Normal file
View File

@ -0,0 +1,558 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024, Linaro Limited
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sar2130p.dtsi"
#include "pm8150.dtsi"
/ {
model = "Qualcomm Snapdragon AR2 Gen1 Smart Viewer Development Kit";
compatible = "qcom,qar2130p", "qcom,sar2130p";
chassis-type = "embedded";
aliases {
serial0 = &uart11;
serial1 = &uart7;
i2c0 = &i2c8;
i2c1 = &i2c10;
mmc1 = &sdhc_1;
spi0 = &spi0;
};
chosen {
stdout-path = "serial0:115200n8";
};
vph_pwr: regulator-vph-pwr {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
};
/* pm3003a on I2C0, should not be controlled */
vreg_ext_1p3: regulator-ext-1p3 {
compatible = "regulator-fixed";
regulator-name = "vph_ext_1p3";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
vin-supply = <&vph_pwr>;
};
/* EBI rail, used as LDO input, can not be part of PMIC config */
vreg_s10a_0p89: regulator-s10a-0p89 {
compatible = "regulator-fixed";
regulator-name = "vph_s10a_0p89";
regulator-min-microvolt = <890000>;
regulator-max-microvolt = <890000>;
regulator-always-on;
vin-supply = <&vph_pwr>;
};
thermal-zones {
sar2130p-thermal {
thermal-sensors = <&pm8150_adc_tm 1>;
trips {
active-config0 {
temperature = <100000>;
hysteresis = <1000>;
type = "critical";
};
};
};
wifi-thermal {
thermal-sensors = <&pm8150_adc_tm 2>;
trips {
active-config0 {
temperature = <52000>;
hysteresis = <4000>;
type = "passive";
};
};
};
xo-thermal {
thermal-sensors = <&pm8150_adc_tm 0>;
trips {
active-config0 {
temperature = <50000>;
hysteresis = <4000>;
type = "passive";
};
};
};
};
wcn7850-pmu {
compatible = "qcom,wcn7850-pmu";
pinctrl-0 = <&wlan_en_state>, <&bt_en_state>;
pinctrl-names = "default";
wlan-enable-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
bt-enable-gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
vdd-supply = <&vreg_s4a_0p95>;
vddio-supply = <&vreg_l15a_1p8>;
vddaon-supply = <&vreg_s4a_0p95>;
vdddig-supply = <&vreg_s4a_0p95>;
vddrfa1p2-supply = <&vreg_s4a_0p95>;
vddrfa1p8-supply = <&vreg_s5a_1p88>;
regulators {
vreg_pmu_rfa_cmn: ldo0 {
regulator-name = "vreg_pmu_rfa_cmn";
};
vreg_pmu_aon_0p59: ldo1 {
regulator-name = "vreg_pmu_aon_0p59";
};
vreg_pmu_wlcx_0p8: ldo2 {
regulator-name = "vreg_pmu_wlcx_0p8";
};
vreg_pmu_wlmx_0p85: ldo3 {
regulator-name = "vreg_pmu_wlmx_0p85";
};
vreg_pmu_btcmx_0p85: ldo4 {
regulator-name = "vreg_pmu_btcmx_0p85";
};
vreg_pmu_rfa_0p8: ldo5 {
regulator-name = "vreg_pmu_rfa_0p8";
};
vreg_pmu_rfa_1p2: ldo6 {
regulator-name = "vreg_pmu_rfa_1p2";
};
vreg_pmu_rfa_1p8: ldo7 {
regulator-name = "vreg_pmu_rfa_1p8";
};
vreg_pmu_pcie_0p9: ldo8 {
regulator-name = "vreg_pmu_pcie_0p9";
};
vreg_pmu_pcie_1p8: ldo9 {
regulator-name = "vreg_pmu_pcie_1p8";
};
};
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pm8150-rpmh-regulators";
qcom,pmic-id = "a";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-s9-supply = <&vph_pwr>;
vdd-s10-supply = <&vph_pwr>;
vdd-l1-l8-l11-supply = <&vreg_s4a_0p95>;
vdd-l3-l4-l5-l18-supply = <&vreg_ext_1p3>;
vdd-l6-l9-supply = <&vreg_s10a_0p89>;
vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p88>;
vreg_s4a_0p95: smps6 {
regulator-name = "vreg_s4a_0p95";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1170000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s5a_1p88: smps5 {
regulator-name = "vreg_s5a_1p88";
regulator-min-microvolt = <1856000>;
regulator-max-microvolt = <2040000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1a_0p91: ldo1 {
regulator-name = "vreg_l1a_0p91";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <920000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2a_3p1: ldo2 {
regulator-name = "vreg_l2a_3p1";
regulator-min-microvolt = <3080000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3a_1p2: ldo3 {
regulator-name = "vreg_l3a_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
/* ldo4 1.26 - system ? */
vreg_l5a_1p13: ldo5 {
regulator-name = "vreg_l5a_1p13";
regulator-min-microvolt = <1128000>;
regulator-max-microvolt = <1170000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6a_0p6: ldo6 {
regulator-name = "vreg_l6a_0p6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <650000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a_1p8: ldo7 {
regulator-name = "vreg_l7a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8a_0p88: ldo8 {
regulator-name = "vreg_l8a_0p88";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
/* ldo9 - LCX */
vreg_l10a_2p95: ldo10 {
regulator-name = "vreg_l10a_2p95";
regulator-min-microvolt = <2952000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
/* ldo11 - LMX */
vreg_l12a_1p8: ldo12 {
regulator-name = "vreg_l12a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
/* no ldo13 */
vreg_l14a_1p8: ldo14 {
regulator-name = "vreg_l14a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l15a_1p8: ldo15 {
regulator-name = "vreg_l15a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
/* no ldo16 - system */
vreg_l17a_3p26: ldo17 {
regulator-name = "vreg_l17a_3p26";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l18a_1p2: ldo18 {
regulator-name = "vreg_l18a_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
};
&gpi_dma0 {
status = "okay";
};
&gpi_dma1 {
status = "okay";
};
&gpu {
status = "okay";
};
&gpu_zap_shader {
firmware-name = "qcom/sar2130p/a620_zap.mbn";
};
&pon_pwrkey {
status = "okay";
};
&pon_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&qupv3_id_0 {
status = "okay";
};
&qupv3_id_1 {
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
status = "okay";
};
&i2c8 {
clock-frequency = <400000>;
status = "okay";
ptn3222: redriver@4f {
compatible = "nxp,ptn3222";
reg = <0x4f>;
reset-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
vdd3v3-supply = <&vreg_l2a_3p1>;
vdd1v8-supply = <&vreg_l15a_1p8>;
#phy-cells = <0>;
};
};
&i2c10 {
clock-frequency = <400000>;
status = "okay";
};
&pcie0 {
perst-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
status = "okay";
};
&pcieport0 {
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
vddaon-supply = <&vreg_pmu_aon_0p59>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
};
};
&pcie0_phy {
vdda-phy-supply = <&vreg_l8a_0p88>;
vdda-pll-supply = <&vreg_l3a_1p2>;
status = "okay";
};
&pm8150_adc {
channel@4c {
reg = <ADC5_XO_THERM_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "xo_therm";
};
channel@4d {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "skin_therm";
};
channel@4e {
/* msm-5.10 uses ADC5_AMUX_THM2 / 0x0e, although there is a pullup */
reg = <ADC5_AMUX_THM2_100K_PU>;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "wifi_therm";
};
};
&pm8150_adc_tm {
status = "okay";
xo-therm@0 {
reg = <0>;
io-channels = <&pm8150_adc ADC5_XO_THERM_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
skin-therm@1 {
reg = <1>;
io-channels = <&pm8150_adc ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
wifi-therm@2 {
reg = <2>;
/* msm-5.10 uses ADC5_AMUX_THM2, although there is a pullup */
io-channels = <&pm8150_adc ADC5_AMUX_THM2_100K_PU>;
qcom,hw-settle-time-us = <200>;
};
};
&remoteproc_adsp {
firmware-name = "qcom/sar2130p/adsp.mbn";
status = "okay";
};
&sdhc_1 {
vmmc-supply = <&vreg_l10a_2p95>;
vqmmc-supply = <&vreg_l7a_1p8>;
status = "okay";
};
&tlmm {
bt_en_state: bt-enable-state {
pins = "gpio46";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
pcie0_default_state: pcie0-default-state {
perst-pins {
pins = "gpio55";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq-pins {
pins = "gpio56";
function = "pcie0_clkreqn";
drive-strength = <2>;
bias-pull-up;
};
wake-pins {
pins = "gpio57";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie1_default_state: pcie1-default-state {
perst-pins {
pins = "gpio58";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq-pins {
pins = "gpio59";
function = "pcie1_clkreqn";
drive-strength = <2>;
bias-pull-up;
};
wake-pins {
pins = "gpio60";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
wlan_en_state: wlan-enable-state {
pins = "gpio45";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
};
&uart7 {
status = "okay";
bluetooth {
compatible = "qcom,wcn7850-bt";
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
vddaon-supply = <&vreg_pmu_aon_0p59>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
max-speed = <3200000>;
};
};
&uart11 {
status = "okay";
};
&usb_1 {
status = "okay";
};
&usb_1_hsphy {
vdd-supply = <&vreg_l8a_0p88>;
vdda12-supply = <&vreg_l3a_1p2>;
phys = <&ptn3222>;
status = "okay";
};
&usb_dp_qmpphy {
vdda-phy-supply = <&vreg_l3a_1p2>;
vdda-pll-supply = <&vreg_l1a_0p91>;
status = "okay";
};

3123
arch/arm64/boot/dts/qcom/sar2130p.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

4
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi
View File

@ -12,11 +12,11 @@
/ {
thermal-zones {
5v-choke-thermal {
choke-5v-thermal {
thermal-sensors = <&pm6150_adc_tm 1>;
trips {
5v-choke-crit {
choke-5v-crit {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";

1
arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi
View File

@ -78,6 +78,7 @@
pinctrl-names = "default";
pinctrl-0 = <&lcd_rst>;
avdd-supply = <&ppvar_lcd>;
avee-supply = <&ppvar_lcd>;
pp1800-supply = <&v1p8_disp>;
pp3300-supply = <&pp3300_dx_edp>;
backlight = <&backlight>;

20
arch/arm64/boot/dts/qcom/sc7180.dtsi
View File

@ -580,55 +580,55 @@
compatible = "arm,psci-1.0";
method = "smc";
cpu_pd0: cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
cpu_pd1: cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
cpu_pd2: cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
cpu_pd3: cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
cpu_pd4: cpu4 {
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
cpu_pd5: cpu5 {
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
cpu_pd6: cpu6 {
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
};
cpu_pd7: cpu7 {
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
};
cluster_pd: cpu-cluster0 {
cluster_pd: power-domain-cluster {
#power-domain-cells = <0>;
domain-idle-states = <&cluster_sleep_pc
&cluster_sleep_cx_ret
@ -3064,6 +3064,8 @@
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,parkmode-disable-ss-quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
maximum-speed = "super-speed";

6
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@ -83,7 +83,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-frequency = <32764>;
#clock-cells = <0>;
};
};
@ -3715,6 +3715,8 @@
iommus = <&apps_smmu 0xa0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_2_hsphy>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
@ -4244,6 +4246,8 @@
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,parkmode-disable-ss-quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
maximum-speed = "super-speed";

4
arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
View File

@ -681,10 +681,6 @@
status = "okay";
};
&xo_board_clk {
clock-frequency = <38400000>;
};
/* PINCTRL */
&pmc8180c_gpios {

4
arch/arm64/boot/dts/qcom/sc8180x-primus.dts
View File

@ -773,10 +773,6 @@
status = "okay";
};
&xo_board_clk {
clock-frequency = <38400000>;
};
/* PINCTRL */
&pmc8180c_gpios {

6
arch/arm64/boot/dts/qcom/sc8180x.dtsi
View File

@ -2762,6 +2762,8 @@
iommus = <&apps_smmu 0x60 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_mp_hsphy0>,
<&usb_mp_qmpphy0>,
<&usb_mp_hsphy1>,
@ -2825,6 +2827,8 @@
iommus = <&apps_smmu 0x140 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
@ -2902,6 +2906,8 @@
iommus = <&apps_smmu 0x160 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";

1318
arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts Normal file
View File

File diff suppressed because it is too large Load Diff

1325
arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts Normal file
View File

File diff suppressed because it is too large Load Diff

52
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View File

@ -2743,7 +2743,7 @@
remoteproc_adsp: remoteproc@3000000 {
compatible = "qcom,sc8280xp-adsp-pas";
reg = <0 0x03000000 0 0x100>;
reg = <0 0x03000000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
@ -3536,6 +3536,8 @@
"usb2-2",
"usb2-3";
dr_mode = "host";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
};
};
@ -3593,6 +3595,8 @@
iommus = <&apps_smmu 0x820 0x0>;
phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
ports {
#address-cells = <1>;
@ -3670,6 +3674,8 @@
iommus = <&apps_smmu 0x860 0x0>;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
ports {
#address-cells = <1>;
@ -3900,26 +3906,26 @@
"vfe3",
"csid3";
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 762 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 764 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csid1_lite",
"vfe_lite1",
"csiphy3",
@ -5254,7 +5260,7 @@
remoteproc_nsp0: remoteproc@1b300000 {
compatible = "qcom,sc8280xp-nsp0-pas";
reg = <0 0x1b300000 0 0x100>;
reg = <0 0x1b300000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
@ -5385,7 +5391,7 @@
remoteproc_nsp1: remoteproc@21300000 {
compatible = "qcom,sc8280xp-nsp1-pas";
reg = <0 0x21300000 0 0x100>;
reg = <0 0x21300000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,

97
arch/arm64/boot/dts/qcom/sdm450-lenovo-tbx605f.dts
View File

@ -46,6 +46,18 @@
};
};
backlight: gpio-backlight {
compatible = "gpio-backlight";
gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
default-on;
pinctrl-names = "default";
pinctrl-0 = <&backlight_enable_active>;
pinctrl-1 = <&backlight_enable_sleep>;
};
gpio-keys {
compatible = "gpio-keys";
key-volume-up {
@ -63,6 +75,49 @@
};
};
&mdss {
status = "okay";
};
&mdss_dsi0 {
vdda-supply = <&pm8953_s3>;
vddio-supply = <&pm8953_l6>;
status = "okay";
panel@0 {
compatible = "boe,tv101wum-ll2";
reg = <0>;
vsp-supply = <&lab>;
vsn-supply = <&ibb>;
reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
backlight = <&backlight>;
pinctrl-names = "default";
pinctrl-0 = <&panel_reset_active>;
pinctrl-1 = <&panel_reset_sleep>;
port {
panel_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
&mdss_dsi0_out {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi0_phy {
vcca-supply = <&pm8953_l3>;
status = "okay";
};
&hsusb_phy {
vdd-supply = <&pm8953_l3>;
vdda-pll-supply = <&pm8953_l7>;
@ -90,6 +145,18 @@
};
};
&ibb {
regulator-min-microvolt = <4600000>;
regulator-max-microvolt = <6000000>;
qcom,discharge-resistor-kohms = <32>;
};
&lab {
regulator-min-microvolt = <4600000>;
regulator-max-microvolt = <6000000>;
qcom,soft-start-us = <800>;
};
&pm8953_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
@ -237,6 +304,36 @@
&tlmm {
gpio-reserved-ranges = <0 4>, <135 4>;
backlight_enable_active: backlight-enable-active-state {
pins = "gpio16";
function = "gpio";
drive-strength = <8>;
bias-disable;
output-high;
};
backlight_enable_sleep: backlight-enable-sleep-state {
pins = "gpio16";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
panel_reset_active: panel-reset-active-state {
pins = "gpio61";
function = "gpio";
drive-strength = <8>;
bias-disable;
output-high;
};
panel_reset_sleep: panel-reset-sleep-state {
pins = "gpio61";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
ts_int_active: ts-int-active-state {
pins = "gpio65";
function = "gpio";

4
arch/arm64/boot/dts/qcom/sdm630.dtsi
View File

@ -1300,6 +1300,8 @@
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,parkmode-disable-ss-quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&qusb2phy0>, <&usb3_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
@ -1505,6 +1507,8 @@
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
/* This is the HS-only host */
maximum-speed = "high-speed";

37
arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
View File

@ -10,6 +10,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include "sdm670.dtsi"
@ -49,20 +50,6 @@
};
};
clocks {
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32764>;
};
xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <38400000>;
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
@ -407,6 +394,15 @@
status = "okay";
};
&gpu {
status = "okay";
zap-shader {
memory-region = <&gpu_mem>;
firmware-name = "qcom/sdm670/sargo/a615_zap.mbn";
};
};
&i2c9 {
clock-frequency = <100000>;
status = "okay";
@ -482,6 +478,19 @@
status = "okay";
};
&pm660l_flash {
status = "okay";
led-0 {
function = LED_FUNCTION_FLASH;
color = <LED_COLOR_ID_WHITE>;
led-sources = <1>, <2>;
led-max-microamp = <500000>;
flash-max-microamp = <1500000>;
flash-max-timeout-us = <1280000>;
};
};
&pm660l_gpios {
vol_up_pin: vol-up-state {
pins = "gpio7";

204
arch/arm64/boot/dts/qcom/sdm670.dtsi
View File

@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
@ -28,6 +29,20 @@
chosen { };
clocks {
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32764>;
};
xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <38400000>;
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
@ -617,6 +632,11 @@
#address-cells = <1>;
#size-cells = <1>;
gpu_speed_bin: gpu_speed_bin@1a2 {
reg = <0x1a2 0x2>;
bits = <5 8>;
};
qusb2_hstx_trim: hstx-trim@1eb {
reg = <0x1eb 0x1>;
bits = <1 4>;
@ -1299,6 +1319,180 @@
};
};
gpu: gpu@5000000 {
compatible = "qcom,adreno-615.0", "qcom,adreno";
reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x10>;
reg-names = "kgsl_3d0_reg_memory", "cx_mem";
/*
* Look ma, no clocks! The GPU clocks and power are
* controlled entirely by the GMU
*/
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&adreno_smmu 0>;
operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
interconnects = <&mem_noc MASTER_GRAPHICS_3D 0 &mem_noc SLAVE_EBI_CH0 0>;
interconnect-names = "gfx-mem";
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
status = "disabled";
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-780000000 {
opp-hz = /bits/ 64 <780000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
opp-peak-kBps = <7216000>;
opp-supported-hw = <0x8>;
};
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
opp-peak-kBps = <7216000>;
opp-supported-hw = <0x8>;
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
opp-peak-kBps = <7216000>;
opp-supported-hw = <0x4>;
};
opp-650000000 {
opp-hz = /bits/ 64 <650000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
opp-peak-kBps = <7216000>;
opp-supported-hw = <0xc>;
};
opp-565000000 {
opp-hz = /bits/ 64 <565000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
opp-peak-kBps = <7216000>;
opp-supported-hw = <0xc>;
};
opp-504000000 {
opp-hz = /bits/ 64 <504000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
opp-peak-kBps = <7216000>;
opp-supported-hw = <0x2>;
};
opp-430000000 {
opp-hz = /bits/ 64 <430000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <7216000>;
opp-supported-hw = <0xf>;
};
opp-355000000 {
opp-hz = /bits/ 64 <355000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <6220000>;
opp-supported-hw = <0xf>;
};
opp-267000000 {
opp-hz = /bits/ 64 <267000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-peak-kBps = <4068000>;
opp-supported-hw = <0xf>;
};
opp-180000000 {
opp-hz = /bits/ 64 <180000000>;
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
opp-peak-kBps = <1804000>;
opp-supported-hw = <0xf>;
};
};
};
adreno_smmu: iommu@5040000 {
compatible = "qcom,sdm670-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
reg = <0 0x05040000 0 0x10000>;
#iommu-cells = <1>;
#global-interrupts = <2>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "bus", "iface";
power-domains = <&gpucc GPU_CX_GDSC>;
};
gmu: gmu@506a000 {
compatible = "qcom,adreno-gmu-615.0", "qcom,adreno-gmu";
reg = <0 0x0506a000 0 0x30000>,
<0 0x0b280000 0 0x10000>,
<0 0x0b480000 0 0x10000>;
reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hfi", "gmu";
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
<&gpucc GPU_CC_CXO_CLK>,
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
clock-names = "gmu", "cxo", "axi", "memnoc";
power-domains = <&gpucc GPU_CX_GDSC>,
<&gpucc GPU_GX_GDSC>;
power-domain-names = "cx", "gx";
iommus = <&adreno_smmu 5>;
operating-points-v2 = <&gmu_opp_table>;
gmu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
};
};
};
gpucc: clock-controller@5090000 {
compatible = "qcom,sdm845-gpucc";
reg = <0 0x05090000 0 0x9000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
clock-names = "bi_tcxo",
"gcc_gpu_gpll0_clk_src",
"gcc_gpu_gpll0_div_clk_src";
};
usb_1_hsphy: phy@88e2000 {
compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy";
reg = <0 0x088e2000 0 0x400>;
@ -1400,6 +1594,16 @@
#interrupt-cells = <4>;
};
camcc: clock-controller@ad00000 {
compatible = "qcom,sdm670-camcc", "qcom,sdm845-camcc";
reg = <0 0x0ad00000 0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "bi_tcxo";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
mdss: display-subsystem@ae00000 {
compatible = "qcom,sdm670-mdss";
reg = <0 0x0ae00000 0 0x1000>;

42
arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso
View File

@ -79,45 +79,3 @@
};
};
};
&cci_i2c1 {
#address-cells = <1>;
#size-cells = <0>;
camera@60 {
compatible = "ovti,ov7251";
/* I2C address as per ov7251.txt linux documentation */
reg = <0x60>;
/* CAM3_RST_N */
enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam3_default>;
clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
clock-names = "xclk";
clock-frequency = <24000000>;
/*
* The &vreg_s4a_1p8 trace always powered on.
*
* The 2.8V vdda-supply regulator is enabled when the
* vreg_s4a_1p8 trace is pulled high.
* It too is represented by a fixed regulator.
*
* No 1.2V vddd-supply regulator is used.
*/
vdddo-supply = <&vreg_lvs1a_1p8>;
vdda-supply = <&cam3_avdd_2v8>;
status = "disabled";
port {
ov7251_ep: endpoint {
data-lanes = <0 1>;
/* remote-endpoint = <&csiphy3_ep>; */
};
};
};
};

1
arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
View File

@ -452,7 +452,6 @@
irq-gpio = <&tlmm 125 GPIO_TRANSITORY>;
touchscreen-size-x = <1080>;
touchscreen-size-y = <2160>;
focaltech,max-touch-number = <5>;
};
};

24
arch/arm64/boot/dts/qcom/sdm845.dtsi
View File

@ -4139,6 +4139,8 @@
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,parkmode-disable-ss-quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
@ -4215,6 +4217,8 @@
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,parkmode-disable-ss-quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};
@ -4326,16 +4330,16 @@
"vfe1",
"vfe_lite";
interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csid0",
"csid1",
"csid2",

6
arch/arm64/boot/dts/qcom/sdx75.dtsi
View File

@ -34,7 +34,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-frequency = <32764>;
#clock-cells = <0>;
};
};
@ -893,7 +893,7 @@
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sdx75-mpss-pas";
reg = <0 0x04080000 0 0x4040>;
reg = <0 0x04080000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
@ -1037,6 +1037,8 @@
iommus = <&apps_smmu 0x80 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_hsphy>,
<&usb_qmpphy>;
phy-names = "usb2-phy",

39
arch/arm64/boot/dts/qcom/sm4250.dtsi
View File

@ -36,3 +36,42 @@
&cpu7 {
compatible = "qcom,kryo240";
};
&lpass_tlmm {
compatible = "qcom,sm4250-lpass-lpi-pinctrl";
gpio-ranges = <&lpass_tlmm 0 0 27>;
lpi_i2s2_active: lpi-i2s2-active-state {
sck-pins {
pins = "gpio10";
function = "i2s2_clk";
bias-disable;
drive-strength = <8>;
output-high;
};
ws-pins {
pins = "gpio11";
function = "i2s2_ws";
bias-disable;
drive-strength = <8>;
output-high;
};
data-pins {
pins = "gpio12";
function = "i2s2_data";
bias-disable;
drive-strength = <8>;
output-high;
};
ext-mclk1-pins {
pins = "gpio18";
function = "ext_mclk1_a";
bias-disable;
drive-strength = <16>;
output-high;
};
};
};

2
arch/arm64/boot/dts/qcom/sm4450.dtsi
View File

@ -29,7 +29,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-frequency = <32764>;
#clock-cells = <0>;
};

95
arch/arm64/boot/dts/qcom/sm6115.dtsi
View File

@ -14,6 +14,9 @@
#include <dt-bindings/interconnect/qcom,sm6115.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/sound/qcom,q6asm.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@ -808,6 +811,20 @@
};
};
lpass_tlmm: pinctrl@a7c0000 {
compatible = "qcom,sm6115-lpass-lpi-pinctrl";
reg = <0x0 0x0a7c0000 0x0 0x20000>,
<0x0 0x0a950000 0x0 0x10000>;
clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "audio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 19>;
};
gcc: clock-controller@1400000 {
compatible = "qcom,gcc-sm6115";
reg = <0x0 0x01400000 0x0 0x1f0000>;
@ -2027,7 +2044,7 @@
remoteproc_mpss: remoteproc@6080000 {
compatible = "qcom,sm6115-mpss-pas";
reg = <0x0 0x06080000 0x0 0x100>;
reg = <0x0 0x06080000 0x0 0x10000>;
interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
@ -2670,9 +2687,9 @@
};
};
remoteproc_adsp: remoteproc@ab00000 {
remoteproc_adsp: remoteproc@a400000 {
compatible = "qcom,sm6115-adsp-pas";
reg = <0x0 0x0ab00000 0x0 0x100>;
reg = <0x0 0x0a400000 0x0 0x4040>;
interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
@ -2701,6 +2718,76 @@
qcom,remote-pid = <2>;
mboxes = <&apcs_glb 8>;
apr {
compatible = "qcom,apr-v2";
qcom,glink-channels = "apr_audio_svc";
qcom,domain = <APR_DOMAIN_ADSP>;
#address-cells = <1>;
#size-cells = <0>;
service@3 {
reg = <APR_SVC_ADSP_CORE>;
compatible = "qcom,q6core";
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
};
q6afe: service@4 {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6afedai: dais {
compatible = "qcom,q6afe-dais";
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
};
q6afecc: clock-controller {
compatible = "qcom,q6afe-clocks";
#clock-cells = <2>;
};
};
q6asm: service@7 {
compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6asmdai: dais {
compatible = "qcom,q6asm-dais";
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
iommus = <&apps_smmu 0x1c1 0x0>;
dai@0 {
reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>;
};
dai@1 {
reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>;
};
dai@2 {
reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>;
};
};
};
q6adm: service@8 {
compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6routing: routing {
compatible = "qcom,q6adm-routing";
#sound-dai-cells = <0>;
};
};
};
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
@ -2744,7 +2831,7 @@
remoteproc_cdsp: remoteproc@b300000 {
compatible = "qcom,sm6115-cdsp-pas";
reg = <0x0 0x0b300000 0x0 0x100000>;
reg = <0x0 0x0b300000 0x0 0x4040>;
interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,

4
arch/arm64/boot/dts/qcom/sm6125.dtsi
View File

@ -28,7 +28,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
clock-frequency = <32764>;
clock-output-names = "sleep_clk";
};
};
@ -1209,6 +1209,8 @@
phy-names = "usb2-phy";
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
maximum-speed = "high-speed";
dr_mode = "peripheral";
};

8
arch/arm64/boot/dts/qcom/sm6350.dtsi
View File

@ -936,7 +936,7 @@
power-domains = <&rpmhpd SM6350_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@ -1283,7 +1283,7 @@
adsp: remoteproc@3000000 {
compatible = "qcom,sm6350-adsp-pas";
reg = <0 0x03000000 0 0x100>;
reg = <0x0 0x03000000 0x0 0x10000>;
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
@ -1503,7 +1503,7 @@
mpss: remoteproc@4080000 {
compatible = "qcom,sm6350-mpss-pas";
reg = <0x0 0x04080000 0x0 0x4040>;
reg = <0x0 0x04080000 0x0 0x10000>;
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
@ -1924,6 +1924,8 @@
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
snps,parkmode-disable-ss-quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
usb-role-switch;

12
arch/arm64/boot/dts/qcom/sm6375.dtsi
View File

@ -29,7 +29,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-frequency = <32764>;
#clock-cells = <0>;
};
};
@ -1516,9 +1516,9 @@
#power-domain-cells = <1>;
};
remoteproc_mss: remoteproc@6000000 {
remoteproc_mss: remoteproc@6080000 {
compatible = "qcom,sm6375-mpss-pas";
reg = <0 0x06000000 0 0x4040>;
reg = <0x0 0x06080000 0x0 0x10000>;
interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
@ -1559,7 +1559,7 @@
remoteproc_adsp: remoteproc@a400000 {
compatible = "qcom,sm6375-adsp-pas";
reg = <0 0x0a400000 0 0x100>;
reg = <0 0x0a400000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
@ -1595,9 +1595,9 @@
};
};
remoteproc_cdsp: remoteproc@b000000 {
remoteproc_cdsp: remoteproc@b300000 {
compatible = "qcom,sm6375-cdsp-pas";
reg = <0x0 0x0b000000 0x0 0x100000>;
reg = <0x0 0x0b300000 0x0 0x10000>;
interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,

2
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
View File

@ -32,7 +32,7 @@
chassis-type = "handset";
/* required for bootloader to select correct board */
qcom,msm-id = <434 0x10000>, <459 0x10000>;
qcom,msm-id = <459 0x10000>;
qcom,board-id = <8 32>;
aliases {

5
arch/arm64/boot/dts/qcom/sm8150-hdk.dts
View File

@ -578,6 +578,11 @@
};
};
&pon {
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
};
&pon_pwrkey {
status = "okay";
};

9
arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
View File

@ -376,8 +376,8 @@
pinctrl-0 = <&da7280_intr_default>;
dlg,actuator-type = "LRA";
dlg,dlg,const-op-mode = <1>;
dlg,dlg,periodic-op-mode = <1>;
dlg,const-op-mode = <1>;
dlg,periodic-op-mode = <1>;
dlg,nom-microvolt = <2000000>;
dlg,abs-max-microvolt = <2000000>;
dlg,imax-microamp = <129000>;
@ -430,6 +430,11 @@
/* MAX34417 @ 0x1e */
};
&pon {
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
};
&pon_pwrkey {
status = "okay";
};

5
arch/arm64/boot/dts/qcom/sm8150-mtp.dts
View File

@ -358,6 +358,11 @@
status = "okay";
};
&pon {
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
};
&pon_pwrkey {
status = "okay";
};

5
arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi
View File

@ -601,6 +601,11 @@
};
};
&pon {
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
};
&pon_pwrkey {
status = "okay";
};

4
arch/arm64/boot/dts/qcom/sm8150.dtsi
View File

@ -3658,6 +3658,8 @@
iommus = <&apps_smmu 0x140 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
@ -3735,6 +3737,8 @@
iommus = <&apps_smmu 0x160 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};

5
arch/arm64/boot/dts/qcom/sm8250-hdk.dts
View File

@ -373,6 +373,11 @@
status = "okay";
};
&pon {
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
};
&pon_pwrkey {
status = "okay";
};

5
arch/arm64/boot/dts/qcom/sm8250-mtp.dts
View File

@ -627,6 +627,11 @@
};
};
&pon {
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
};
&qupv3_id_0 {
status = "okay";
};

5
arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi
View File

@ -591,6 +591,11 @@
};
};
&pon {
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
};
&pon_pwrkey {
status = "okay";
};

120
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi
View File

@ -30,6 +30,10 @@
qcom,msm-id = <QCOM_ID_SM8250 0x20001>; /* SM8250 v2.1 */
qcom,board-id = <0x10008 0>;
aliases {
serial0 = &uart6;
};
chosen {
#address-cells = <2>;
#size-cells = <2>;
@ -97,6 +101,67 @@
};
};
qca6390-pmu {
compatible = "qcom,qca6390-pmu";
pinctrl-names = "default";
pinctrl-0 = <&bt_en_state>, <&wlan_en_state>;
vddaon-supply = <&vreg_s6a_0p95>;
vddpmu-supply = <&vreg_s6a_0p95>;
vddrfa0p95-supply = <&vreg_s6a_0p95>;
vddrfa1p3-supply = <&vreg_s8c_1p35>;
vddrfa1p9-supply = <&vreg_s5a_1p9>;
vddpcie1p3-supply = <&vreg_s8c_1p35>;
vddpcie1p9-supply = <&vreg_s5a_1p9>;
vddio-supply = <&vreg_s4a_1p8>;
wlan-enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
bt-enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
regulators {
vreg_pmu_rfa_cmn: ldo0 {
regulator-name = "vreg_pmu_rfa_cmn";
};
vreg_pmu_aon_0p59: ldo1 {
regulator-name = "vreg_pmu_aon_0p59";
};
vreg_pmu_wlcx_0p8: ldo2 {
regulator-name = "vreg_pmu_wlcx_0p8";
};
vreg_pmu_wlmx_0p85: ldo3 {
regulator-name = "vreg_pmu_wlmx_0p85";
};
vreg_pmu_btcmx_0p85: ldo4 {
regulator-name = "vreg_pmu_btcmx_0p85";
};
vreg_pmu_rfa_0p8: ldo5 {
regulator-name = "vreg_pmu_rfa_0p8";
};
vreg_pmu_rfa_1p2: ldo6 {
regulator-name = "vreg_pmu_rfa_1p2";
};
vreg_pmu_rfa_1p7: ldo7 {
regulator-name = "vreg_pmu_rfa_1p7";
};
vreg_pmu_pcie_0p9: ldo8 {
regulator-name = "vreg_pmu_pcie_0p9";
};
vreg_pmu_pcie_1p8: ldo9 {
regulator-name = "vreg_pmu_pcie_1p8";
};
};
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
@ -619,6 +684,25 @@
status = "okay";
};
&pcieport0 {
wifi@0 {
compatible = "pci17cb,1101";
reg = <0x10000 0x0 0x0 0x0 0x0>;
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
vddaon-supply = <&vreg_pmu_aon_0p59>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>;
vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
qcom,ath11k-calibration-variant = "Xiaomi_Pad_5Pro";
};
};
&pm8150_gpios {
vol_up_n: vol-up-n-state {
pins = "gpio6";
@ -673,6 +757,11 @@
status = "okay";
};
&pon {
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
};
&pon_pwrkey {
status = "okay";
};
@ -701,6 +790,37 @@
&tlmm {
gpio-reserved-ranges = <40 4>;
bt_en_state: bt-default-state {
pins = "gpio21";
function = "gpio";
drive-strength = <16>;
output-low;
bias-pull-up;
};
wlan_en_state: wlan-default-state {
pins = "gpio20";
function = "gpio";
drive-strength = <16>;
output-low;
bias-pull-up;
};
};
&uart6 {
status = "okay";
bluetooth {
compatible = "qcom,qca6390-bt";
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
vddaon-supply = <&vreg_pmu_aon_0p59>;
vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>;
};
};
&usb_1 {

5
arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts
View File

@ -554,6 +554,11 @@
};
};
&pon {
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
};
&pon_pwrkey {
status = "okay";
};

34
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@ -84,7 +84,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-frequency = <32764>;
#clock-cells = <0>;
};
};
@ -4207,6 +4207,8 @@
iommus = <&apps_smmu 0x0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
@ -4294,6 +4296,8 @@
iommus = <&apps_smmu 0x20 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};
@ -4481,20 +4485,20 @@
"vfe_lite0",
"vfe_lite1";
interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy0",
"csiphy1",
"csiphy2",

7
arch/arm64/boot/dts/qcom/sm8350-hdk.dts
View File

@ -925,3 +925,10 @@
};
};
};
&ipa {
qcom,gsi-loader = "self";
memory-region = <&pil_ipa_fw_mem>;
status = "okay";
firmware-name = "qcom/sm8350/ipa_fws.mbn";
};

498
arch/arm64/boot/dts/qcom/sm8350.dtsi
View File

@ -42,7 +42,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-frequency = <32764>;
#clock-cells = <0>;
};
};
@ -1876,6 +1876,142 @@
reg = <0x0 0x1fc0000 0x0 0x30000>;
};
adsp: remoteproc@3000000 {
compatible = "qcom,sm8350-adsp-pas";
reg = <0x0 0x03000000 0x0 0x10000>;
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd RPMHPD_LCX>,
<&rpmhpd RPMHPD_LMX>;
power-domain-names = "lcx", "lmx";
memory-region = <&pil_adsp_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "lpass";
qcom,remote-pid = <2>;
apr {
compatible = "qcom,apr-v2";
qcom,glink-channels = "apr_audio_svc";
qcom,domain = <APR_DOMAIN_ADSP>;
#address-cells = <1>;
#size-cells = <0>;
service@3 {
reg = <APR_SVC_ADSP_CORE>;
compatible = "qcom,q6core";
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
};
q6afe: service@4 {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
q6afedai: dais {
compatible = "qcom,q6afe-dais";
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
};
q6afecc: clock-controller {
compatible = "qcom,q6afe-clocks";
#clock-cells = <2>;
};
};
q6asm: service@7 {
compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
q6asmdai: dais {
compatible = "qcom,q6asm-dais";
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
iommus = <&apps_smmu 0x1801 0x0>;
dai@0 {
reg = <0>;
};
dai@1 {
reg = <1>;
};
dai@2 {
reg = <2>;
};
};
};
q6adm: service@8 {
compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
q6routing: routing {
compatible = "qcom,q6adm-routing";
#sound-dai-cells = <0>;
};
};
};
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x1803 0x0>;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x1804 0x0>;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x1805 0x0>;
};
};
};
};
lpass_tlmm: pinctrl@33c0000 {
compatible = "qcom,sm8350-lpass-lpi-pinctrl";
reg = <0 0x033c0000 0 0x20000>,
@ -2078,7 +2214,7 @@
mpss: remoteproc@4080000 {
compatible = "qcom,sm8350-mpss-pas";
reg = <0x0 0x04080000 0x0 0x4040>;
reg = <0x0 0x04080000 0x0 0x10000>;
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
@ -2360,6 +2496,115 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
cdsp: remoteproc@a300000 {
compatible = "qcom,sm8350-cdsp-pas";
reg = <0x0 0x0a300000 0x0 0x10000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MXC>;
power-domain-names = "cx", "mxc";
interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
memory-region = <&pil_cdsp_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_cdsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "cdsp";
qcom,remote-pid = <5>;
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "cdsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@1 {
compatible = "qcom,fastrpc-compute-cb";
reg = <1>;
iommus = <&apps_smmu 0x2161 0x0400>,
<&apps_smmu 0x1181 0x0420>;
};
compute-cb@2 {
compatible = "qcom,fastrpc-compute-cb";
reg = <2>;
iommus = <&apps_smmu 0x2162 0x0400>,
<&apps_smmu 0x1182 0x0420>;
};
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x2163 0x0400>,
<&apps_smmu 0x1183 0x0420>;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x2164 0x0400>,
<&apps_smmu 0x1184 0x0420>;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x2165 0x0400>,
<&apps_smmu 0x1185 0x0420>;
};
compute-cb@6 {
compatible = "qcom,fastrpc-compute-cb";
reg = <6>;
iommus = <&apps_smmu 0x2166 0x0400>,
<&apps_smmu 0x1186 0x0420>;
};
compute-cb@7 {
compatible = "qcom,fastrpc-compute-cb";
reg = <7>;
iommus = <&apps_smmu 0x2167 0x0400>,
<&apps_smmu 0x1187 0x0420>;
};
compute-cb@8 {
compatible = "qcom,fastrpc-compute-cb";
reg = <8>;
iommus = <&apps_smmu 0x2168 0x0400>,
<&apps_smmu 0x1188 0x0420>;
};
/* note: secure cb9 in downstream */
};
};
};
usb_1: usb@a6f8800 {
compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
@ -2409,6 +2654,8 @@
iommus = <&apps_smmu 0x0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
@ -2485,6 +2732,8 @@
iommus = <&apps_smmu 0x20 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};
@ -3285,142 +3534,6 @@
dma-coherent;
};
adsp: remoteproc@17300000 {
compatible = "qcom,sm8350-adsp-pas";
reg = <0 0x17300000 0 0x100>;
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd RPMHPD_LCX>,
<&rpmhpd RPMHPD_LMX>;
power-domain-names = "lcx", "lmx";
memory-region = <&pil_adsp_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "lpass";
qcom,remote-pid = <2>;
apr {
compatible = "qcom,apr-v2";
qcom,glink-channels = "apr_audio_svc";
qcom,domain = <APR_DOMAIN_ADSP>;
#address-cells = <1>;
#size-cells = <0>;
service@3 {
reg = <APR_SVC_ADSP_CORE>;
compatible = "qcom,q6core";
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
};
q6afe: service@4 {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
q6afedai: dais {
compatible = "qcom,q6afe-dais";
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
};
q6afecc: clock-controller {
compatible = "qcom,q6afe-clocks";
#clock-cells = <2>;
};
};
q6asm: service@7 {
compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
q6asmdai: dais {
compatible = "qcom,q6asm-dais";
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
iommus = <&apps_smmu 0x1801 0x0>;
dai@0 {
reg = <0>;
};
dai@1 {
reg = <1>;
};
dai@2 {
reg = <2>;
};
};
};
q6adm: service@8 {
compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
q6routing: routing {
compatible = "qcom,q6adm-routing";
#sound-dai-cells = <0>;
};
};
};
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x1803 0x0>;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x1804 0x0>;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x1805 0x0>;
};
};
};
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
@ -3589,115 +3702,6 @@
#freq-domain-cells = <1>;
#clock-cells = <1>;
};
cdsp: remoteproc@98900000 {
compatible = "qcom,sm8350-cdsp-pas";
reg = <0 0x98900000 0 0x1400000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MXC>;
power-domain-names = "cx", "mxc";
interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
memory-region = <&pil_cdsp_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_cdsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "cdsp";
qcom,remote-pid = <5>;
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "cdsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@1 {
compatible = "qcom,fastrpc-compute-cb";
reg = <1>;
iommus = <&apps_smmu 0x2161 0x0400>,
<&apps_smmu 0x1181 0x0420>;
};
compute-cb@2 {
compatible = "qcom,fastrpc-compute-cb";
reg = <2>;
iommus = <&apps_smmu 0x2162 0x0400>,
<&apps_smmu 0x1182 0x0420>;
};
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x2163 0x0400>,
<&apps_smmu 0x1183 0x0420>;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x2164 0x0400>,
<&apps_smmu 0x1184 0x0420>;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x2165 0x0400>,
<&apps_smmu 0x1185 0x0420>;
};
compute-cb@6 {
compatible = "qcom,fastrpc-compute-cb";
reg = <6>;
iommus = <&apps_smmu 0x2166 0x0400>,
<&apps_smmu 0x1186 0x0420>;
};
compute-cb@7 {
compatible = "qcom,fastrpc-compute-cb";
reg = <7>;
iommus = <&apps_smmu 0x2167 0x0400>,
<&apps_smmu 0x1187 0x0420>;
};
compute-cb@8 {
compatible = "qcom,fastrpc-compute-cb";
reg = <8>;
iommus = <&apps_smmu 0x2168 0x0400>,
<&apps_smmu 0x1188 0x0420>;
};
/* note: secure cb9 in downstream */
};
};
};
};
thermal_zones: thermal-zones {

946
arch/arm64/boot/dts/qcom/sm8450.dtsi
View File

@ -43,7 +43,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
clock-frequency = <32764>;
};
};
@ -287,6 +287,192 @@
};
};
ete-0 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu0>;
out-ports {
port {
ete0_out_funnel_ete: endpoint {
remote-endpoint = <&funnel_ete_in_ete0>;
};
};
};
};
ete-1 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu1>;
out-ports {
port {
ete1_out_funnel_ete: endpoint {
remote-endpoint = <&funnel_ete_in_ete1>;
};
};
};
};
ete-2 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu2>;
out-ports {
port {
ete2_out_funnel_ete: endpoint {
remote-endpoint = <&funnel_ete_in_ete2>;
};
};
};
};
ete-3 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu3>;
out-ports {
port {
ete3_out_funnel_ete: endpoint {
remote-endpoint = <&funnel_ete_in_ete3>;
};
};
};
};
ete-4 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu4>;
out-ports {
port {
ete4_out_funnel_ete: endpoint {
remote-endpoint = <&funnel_ete_in_ete4>;
};
};
};
};
ete-5 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu5>;
out-ports {
port {
ete5_out_funnel_ete: endpoint {
remote-endpoint = <&funnel_ete_in_ete5>;
};
};
};
};
ete-6 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu6>;
out-ports {
port {
ete6_out_funnel_ete: endpoint {
remote-endpoint = <&funnel_ete_in_ete6>;
};
};
};
};
ete-7 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu7>;
out-ports {
port {
ete7_out_funnel_ete: endpoint {
remote-endpoint = <&funnel_ete_in_ete7>;
};
};
};
};
funnel-ete {
compatible = "arm,coresight-static-funnel";
out-ports {
port {
funnel_ete_out_funnel_apss: endpoint {
remote-endpoint =
<&funnel_apss_in_funnel_ete>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_ete_in_ete0: endpoint {
remote-endpoint =
<&ete0_out_funnel_ete>;
};
};
port@1 {
reg = <1>;
funnel_ete_in_ete1: endpoint {
remote-endpoint =
<&ete1_out_funnel_ete>;
};
};
port@2 {
reg = <2>;
funnel_ete_in_ete2: endpoint {
remote-endpoint =
<&ete2_out_funnel_ete>;
};
};
port@3 {
reg = <3>;
funnel_ete_in_ete3: endpoint {
remote-endpoint =
<&ete3_out_funnel_ete>;
};
};
port@4 {
reg = <4>;
funnel_ete_in_ete4: endpoint {
remote-endpoint =
<&ete4_out_funnel_ete>;
};
};
port@5 {
reg = <5>;
funnel_ete_in_ete5: endpoint {
remote-endpoint =
<&ete5_out_funnel_ete>;
};
};
port@6 {
reg = <6>;
funnel_ete_in_ete6: endpoint {
remote-endpoint =
<&ete6_out_funnel_ete>;
};
};
port@7 {
reg = <7>;
funnel_ete_in_ete7: endpoint {
remote-endpoint =
<&ete7_out_funnel_ete>;
};
};
};
};
firmware {
scm: scm {
compatible = "qcom,scm-sm8450", "qcom,scm";
@ -2496,6 +2682,112 @@
};
};
remoteproc_adsp: remoteproc@3000000 {
compatible = "qcom,sm8450-adsp-pas";
reg = <0x0 0x03000000 0x0 0x10000>;
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd RPMHPD_LCX>,
<&rpmhpd RPMHPD_LMX>;
power-domain-names = "lcx", "lmx";
memory-region = <&adsp_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
remoteproc_adsp_glink: glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "lpass";
qcom,remote-pid = <2>;
gpr {
compatible = "qcom,gpr";
qcom,glink-channels = "adsp_apps";
qcom,domain = <GPR_DOMAIN_ID_ADSP>;
qcom,intents = <512 20>;
#address-cells = <1>;
#size-cells = <0>;
q6apm: service@1 {
compatible = "qcom,q6apm";
reg = <GPR_APM_MODULE_IID>;
#sound-dai-cells = <0>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6apmdai: dais {
compatible = "qcom,q6apm-dais";
iommus = <&apps_smmu 0x1801 0x0>;
};
q6apmbedai: bedais {
compatible = "qcom,q6apm-lpass-dais";
#sound-dai-cells = <1>;
};
};
q6prm: service@2 {
compatible = "qcom,q6prm";
reg = <GPR_PRM_MODULE_IID>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6prmcc: clock-controller {
compatible = "qcom,q6prm-lpass-clocks";
#clock-cells = <2>;
};
};
};
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x1803 0x0>;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x1804 0x0>;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x1805 0x0>;
};
};
};
};
wsa2macro: codec@31e0000 {
compatible = "qcom,sm8450-lpass-wsa-macro";
reg = <0 0x031e0000 0 0x1000>;
@ -2692,115 +2984,9 @@
status = "disabled";
};
remoteproc_adsp: remoteproc@30000000 {
compatible = "qcom,sm8450-adsp-pas";
reg = <0 0x30000000 0 0x100>;
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd RPMHPD_LCX>,
<&rpmhpd RPMHPD_LMX>;
power-domain-names = "lcx", "lmx";
memory-region = <&adsp_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
remoteproc_adsp_glink: glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "lpass";
qcom,remote-pid = <2>;
gpr {
compatible = "qcom,gpr";
qcom,glink-channels = "adsp_apps";
qcom,domain = <GPR_DOMAIN_ID_ADSP>;
qcom,intents = <512 20>;
#address-cells = <1>;
#size-cells = <0>;
q6apm: service@1 {
compatible = "qcom,q6apm";
reg = <GPR_APM_MODULE_IID>;
#sound-dai-cells = <0>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6apmdai: dais {
compatible = "qcom,q6apm-dais";
iommus = <&apps_smmu 0x1801 0x0>;
};
q6apmbedai: bedais {
compatible = "qcom,q6apm-lpass-dais";
#sound-dai-cells = <1>;
};
};
q6prm: service@2 {
compatible = "qcom,q6prm";
reg = <GPR_PRM_MODULE_IID>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6prmcc: clock-controller {
compatible = "qcom,q6prm-lpass-clocks";
#clock-cells = <2>;
};
};
};
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x1803 0x0>;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x1804 0x0>;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x1805 0x0>;
};
};
};
};
remoteproc_cdsp: remoteproc@32300000 {
compatible = "qcom,sm8450-cdsp-pas";
reg = <0 0x32300000 0 0x1400000>;
reg = <0 0x32300000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
@ -2907,7 +3093,7 @@
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sm8450-mpss-pas";
reg = <0x0 0x04080000 0x0 0x4040>;
reg = <0x0 0x04080000 0x0 0x10000>;
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
@ -4144,6 +4330,546 @@
};
};
stm@10002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x0 0x10002000 0x0 0x1000>,
<0x0 0x16280000 0x0 0x180000>;
reg-names = "stm-base", "stm-stimulus-base";
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
stm_out_funnel_in0: endpoint {
remote-endpoint =
<&funnel_in0_in_stm>;
};
};
};
};
funnel@10041000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x10041000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@7 {
reg = <7>;
funnel_in0_in_stm: endpoint {
remote-endpoint =
<&stm_out_funnel_in0>;
};
};
};
out-ports {
port {
funnel_in0_out_funnel_qdss: endpoint {
remote-endpoint =
<&funnel_qdss_in_funnel_in0>;
};
};
};
};
funnel@10042000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x10042000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@4 {
reg = <4>;
funnel_in1_in_funnel_apss: endpoint {
remote-endpoint =
<&funnel_apss_out_funnel_in1>;
};
};
port@6 {
reg = <6>;
funnel_in1_in_funnel_dl_center: endpoint {
remote-endpoint =
<&funnel_dl_center_out_funnel_in1>;
};
};
};
out-ports {
port {
funnel_in1_out_funnel_qdss: endpoint {
remote-endpoint =
<&funnel_qdss_in_funnel_in1>;
};
};
};
};
funnel@10045000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x10045000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_qdss_in_funnel_in0: endpoint {
remote-endpoint =
<&funnel_in0_out_funnel_qdss>;
};
};
port@1 {
reg = <1>;
funnel_qdss_in_funnel_in1: endpoint {
remote-endpoint =
<&funnel_in1_out_funnel_qdss>;
};
};
};
out-ports {
port {
funnel_qdss_out_funnel_aoss: endpoint {
remote-endpoint =
<&funnel_aoss_in_funnel_qdss>;
};
};
};
};
replicator@10046000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x0 0x10046000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
replicator_qdss_in_replicator_swao: endpoint {
remote-endpoint =
<&replicator_swao_out_replicator_qdss>;
};
};
};
out-ports {
port {
replicator_qdss_out_replicator_etr: endpoint {
remote-endpoint =
<&replicator_etr_in_replicator_qdss>;
};
};
};
};
tmc_etr: tmc@10048000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x0 0x10048000 0x0 0x1000>;
iommus = <&apps_smmu 0x0600 0>;
arm,buffer-size = <0x10000>;
arm,scatter-gather;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
tmc_etr_in_replicator_etr: endpoint {
remote-endpoint =
<&replicator_etr_out_tmc_etr>;
};
};
};
};
replicator@1004e000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x0 0x1004e000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
replicator_etr_in_replicator_qdss: endpoint {
remote-endpoint =
<&replicator_qdss_out_replicator_etr>;
};
};
};
out-ports {
port {
replicator_etr_out_tmc_etr: endpoint {
remote-endpoint =
<&tmc_etr_in_replicator_etr>;
};
};
};
};
funnel@10b04000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x10b04000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@6 {
reg = <6>;
funnel_aoss_in_tpda_aoss: endpoint {
remote-endpoint =
<&tpda_aoss_out_funnel_aoss>;
};
};
port@7 {
reg = <7>;
funnel_aoss_in_funnel_qdss: endpoint {
remote-endpoint =
<&funnel_qdss_out_funnel_aoss>;
};
};
};
out-ports {
port {
funnel_aoss_out_tmc_etf: endpoint {
remote-endpoint =
<&tmc_etf_in_funnel_aoss>;
};
};
};
};
tmc@10b05000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x0 0x10b05000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
tmc_etf_in_funnel_aoss: endpoint {
remote-endpoint =
<&funnel_aoss_out_tmc_etf>;
};
};
};
out-ports {
port {
tmc_etf_out_replicator_swao: endpoint {
remote-endpoint =
<&replicator_swao_in_tmc_etf>;
};
};
};
};
replicator@10b06000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x0 0x10b06000 0x0 0x1000>;
qcom,replicator-loses-context;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
replicator_swao_in_tmc_etf: endpoint {
remote-endpoint =
<&tmc_etf_out_replicator_swao>;
};
};
};
out-ports {
port {
replicator_swao_out_replicator_qdss: endpoint {
remote-endpoint =
<&replicator_qdss_in_replicator_swao>;
};
};
};
};
tpda@10b08000 {
compatible = "qcom,coresight-tpda", "arm,primecell";
reg = <0x0 0x10b08000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpda_aoss_in_tpdm_swao_prio_0: endpoint {
remote-endpoint =
<&tpdm_swao_prio_0_out_tpda_aoss>;
};
};
port@4 {
reg = <4>;
tpda_aoss_in_tpdm_swao: endpoint {
remote-endpoint =
<&tpdm_swao_out_tpda_aoss>;
};
};
};
out-ports {
port {
tpda_aoss_out_funnel_aoss: endpoint {
remote-endpoint =
<&funnel_aoss_in_tpda_aoss>;
};
};
};
};
tpdm@10b09000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x10b09000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
tpdm_swao_prio_0_out_tpda_aoss: endpoint {
remote-endpoint =
<&tpda_aoss_in_tpdm_swao_prio_0>;
};
};
};
};
tpdm@10b0d000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x10b0d000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
tpdm_swao_out_tpda_aoss: endpoint {
remote-endpoint =
<&tpda_aoss_in_tpdm_swao>;
};
};
};
};
tpdm@10c28000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x10c28000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
tpdm_dlct_out_tpda_dl_center_26: endpoint {
remote-endpoint =
<&tpda_dl_center_26_in_tpdm_dlct>;
};
};
};
};
tpdm@10c29000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x10c29000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
tpdm_ipcc_out_tpda_dl_center_27: endpoint {
remote-endpoint =
<&tpda_dl_center_27_in_tpdm_ipcc>;
};
};
};
};
cti@10c2a000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x10c2a000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@10c2b000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x10c2b000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
tpda@10c2e000 {
compatible = "qcom,coresight-tpda", "arm,primecell";
reg = <0x0 0x10c2e000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@1a {
reg = <26>;
tpda_dl_center_26_in_tpdm_dlct: endpoint {
remote-endpoint =
<&tpdm_dlct_out_tpda_dl_center_26>;
};
};
port@1b {
reg = <27>;
tpda_dl_center_27_in_tpdm_ipcc: endpoint {
remote-endpoint =
<&tpdm_ipcc_out_tpda_dl_center_27>;
};
};
};
out-ports {
port {
tpda_dl_center_out_funnel_dl_center: endpoint {
remote-endpoint =
<&funnel_dl_center_in_tpda_dl_center>;
};
};
};
};
funnel@10c2f000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x10c2f000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
funnel_dl_center_in_tpda_dl_center: endpoint {
remote-endpoint =
<&tpda_dl_center_out_funnel_dl_center>;
};
};
};
out-ports {
port {
funnel_dl_center_out_funnel_in1: endpoint {
remote-endpoint =
<&funnel_in1_in_funnel_dl_center>;
};
};
};
};
funnel@13810000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x13810000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
funnel_apss_in_funnel_ete: endpoint {
remote-endpoint =
<&funnel_ete_out_funnel_apss>;
};
};
};
out-ports {
port {
funnel_apss_out_funnel_in1: endpoint {
remote-endpoint =
<&funnel_in1_in_funnel_apss>;
};
};
};
};
cti@138e0000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x138e0000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@138f0000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x138f0000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@13900000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x13900000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
sram@146aa000 {
compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
reg = <0 0x146aa000 0 0x1000>;
@ -4672,6 +5398,8 @@
iommus = <&apps_smmu 0x0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";

2
arch/arm64/boot/dts/qcom/sm8550-hdk.dts
View File

@ -1172,7 +1172,7 @@
};
&sleep_clk {
clock-frequency = <32000>;
clock-frequency = <32764>;
};
&swr0 {

2
arch/arm64/boot/dts/qcom/sm8550-mtp.dts
View File

@ -825,7 +825,7 @@
};
&sleep_clk {
clock-frequency = <32000>;
clock-frequency = <32764>;
};
&swr0 {

2
arch/arm64/boot/dts/qcom/sm8550-qrd.dts
View File

@ -1005,7 +1005,7 @@
};
&sleep_clk {
clock-frequency = <32000>;
clock-frequency = <32764>;
};
&swr0 {

2
arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
View File

@ -565,7 +565,7 @@
};
&sleep_clk {
clock-frequency = <32000>;
clock-frequency = <32764>;
};
&tlmm {

2
arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
View File

@ -722,7 +722,7 @@
};
&sleep_clk {
clock-frequency = <32000>;
clock-frequency = <32764>;
};
&tlmm {

296
arch/arm64/boot/dts/qcom/sm8550.dtsi
View File

@ -14,6 +14,7 @@
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
@ -1734,7 +1735,8 @@
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
@ -1742,7 +1744,8 @@
"msi4",
"msi5",
"msi6",
"msi7";
"msi7",
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -1850,7 +1853,8 @@
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
@ -1858,7 +1862,8 @@
"msi4",
"msi5",
"msi6",
"msi7";
"msi7",
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -2114,6 +2119,10 @@
qcom,gmu = <&gmu>;
#cooling-cells = <2>;
interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "gfx-mem";
status = "disabled";
zap-shader {
@ -2127,41 +2136,49 @@
opp-680000000 {
opp-hz = /bits/ 64 <680000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <16500000>;
};
opp-615000000 {
opp-hz = /bits/ 64 <615000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
opp-peak-kBps = <12449218>;
};
opp-550000000 {
opp-hz = /bits/ 64 <550000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <10687500>;
};
opp-475000000 {
opp-hz = /bits/ 64 <475000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
opp-peak-kBps = <6074218>;
};
opp-401000000 {
opp-hz = /bits/ 64 <401000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-peak-kBps = <6074218>;
};
opp-348000000 {
opp-hz = /bits/ 64 <348000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
opp-peak-kBps = <6074218>;
};
opp-295000000 {
opp-hz = /bits/ 64 <295000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
opp-peak-kBps = <6074218>;
};
opp-220000000 {
opp-hz = /bits/ 64 <220000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
opp-peak-kBps = <2136718>;
};
};
};
@ -2314,7 +2331,7 @@
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sm8550-mpss-pas";
reg = <0x0 0x04080000 0x0 0x4040>;
reg = <0x0 0x04080000 0x0 0x10000>;
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
@ -2354,6 +2371,137 @@
};
};
remoteproc_adsp: remoteproc@6800000 {
compatible = "qcom,sm8550-adsp-pas";
reg = <0x0 0x06800000 0x0 0x10000>;
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd RPMHPD_LCX>,
<&rpmhpd RPMHPD_LMX>;
power-domain-names = "lcx", "lmx";
interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
remoteproc_adsp_glink: glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "lpass";
qcom,remote-pid = <2>;
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x1003 0x80>,
<&apps_smmu 0x1063 0x0>;
dma-coherent;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x1004 0x80>,
<&apps_smmu 0x1064 0x0>;
dma-coherent;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x1005 0x80>,
<&apps_smmu 0x1065 0x0>;
dma-coherent;
};
compute-cb@6 {
compatible = "qcom,fastrpc-compute-cb";
reg = <6>;
iommus = <&apps_smmu 0x1006 0x80>,
<&apps_smmu 0x1066 0x0>;
dma-coherent;
};
compute-cb@7 {
compatible = "qcom,fastrpc-compute-cb";
reg = <7>;
iommus = <&apps_smmu 0x1007 0x80>,
<&apps_smmu 0x1067 0x0>;
dma-coherent;
};
};
gpr {
compatible = "qcom,gpr";
qcom,glink-channels = "adsp_apps";
qcom,domain = <GPR_DOMAIN_ID_ADSP>;
qcom,intents = <512 20>;
#address-cells = <1>;
#size-cells = <0>;
q6apm: service@1 {
compatible = "qcom,q6apm";
reg = <GPR_APM_MODULE_IID>;
#sound-dai-cells = <0>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6apmdai: dais {
compatible = "qcom,q6apm-dais";
iommus = <&apps_smmu 0x1001 0x80>,
<&apps_smmu 0x1061 0x0>;
};
q6apmbedai: bedais {
compatible = "qcom,q6apm-lpass-dais";
#sound-dai-cells = <1>;
};
};
q6prm: service@2 {
compatible = "qcom,q6prm";
reg = <GPR_PRM_MODULE_IID>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6prmcc: clock-controller {
compatible = "qcom,q6prm-lpass-clocks";
#clock-cells = <2>;
};
};
};
};
};
lpass_wsa2macro: codec@6aa0000 {
compatible = "qcom,sm8550-lpass-wsa-macro";
reg = <0 0x06aa0000 0 0x1000>;
@ -2872,9 +3020,8 @@
power-domains = <&dispcc MDSS_GDSC>;
interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
<&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "mdp0-mem", "mdp1-mem";
interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "mdp0-mem";
iommus = <&apps_smmu 0x1c00 0x2>;
@ -4576,137 +4723,6 @@
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
};
remoteproc_adsp: remoteproc@30000000 {
compatible = "qcom,sm8550-adsp-pas";
reg = <0x0 0x30000000 0x0 0x100>;
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd RPMHPD_LCX>,
<&rpmhpd RPMHPD_LMX>;
power-domain-names = "lcx", "lmx";
interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
remoteproc_adsp_glink: glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "lpass";
qcom,remote-pid = <2>;
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x1003 0x80>,
<&apps_smmu 0x1063 0x0>;
dma-coherent;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x1004 0x80>,
<&apps_smmu 0x1064 0x0>;
dma-coherent;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x1005 0x80>,
<&apps_smmu 0x1065 0x0>;
dma-coherent;
};
compute-cb@6 {
compatible = "qcom,fastrpc-compute-cb";
reg = <6>;
iommus = <&apps_smmu 0x1006 0x80>,
<&apps_smmu 0x1066 0x0>;
dma-coherent;
};
compute-cb@7 {
compatible = "qcom,fastrpc-compute-cb";
reg = <7>;
iommus = <&apps_smmu 0x1007 0x80>,
<&apps_smmu 0x1067 0x0>;
dma-coherent;
};
};
gpr {
compatible = "qcom,gpr";
qcom,glink-channels = "adsp_apps";
qcom,domain = <GPR_DOMAIN_ID_ADSP>;
qcom,intents = <512 20>;
#address-cells = <1>;
#size-cells = <0>;
q6apm: service@1 {
compatible = "qcom,q6apm";
reg = <GPR_APM_MODULE_IID>;
#sound-dai-cells = <0>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6apmdai: dais {
compatible = "qcom,q6apm-dais";
iommus = <&apps_smmu 0x1001 0x80>,
<&apps_smmu 0x1061 0x0>;
};
q6apmbedai: bedais {
compatible = "qcom,q6apm-lpass-dais";
#sound-dai-cells = <1>;
};
};
q6prm: service@2 {
compatible = "qcom,q6prm";
reg = <GPR_PRM_MODULE_IID>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6prmcc: clock-controller {
compatible = "qcom,q6prm-lpass-clocks";
#clock-cells = <2>;
};
};
};
};
};
nsp_noc: interconnect@320c0000 {
compatible = "qcom,sm8550-nsp-noc";
reg = <0 0x320c0000 0 0xe080>;
@ -4716,7 +4732,7 @@
remoteproc_cdsp: remoteproc@32300000 {
compatible = "qcom,sm8550-cdsp-pas";
reg = <0x0 0x32300000 0x0 0x1400000>;
reg = <0x0 0x32300000 0x0 0x10000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,

2
arch/arm64/boot/dts/qcom/sm8650-hdk.dts
View File

@ -1113,7 +1113,7 @@
};
&sleep_clk {
clock-frequency = <32000>;
clock-frequency = <32764>;
};
&swr0 {

2
arch/arm64/boot/dts/qcom/sm8650-mtp.dts
View File

@ -730,7 +730,7 @@
};
&sleep_clk {
clock-frequency = <32000>;
clock-frequency = <32764>;
};
&swr0 {

2
arch/arm64/boot/dts/qcom/sm8650-qrd.dts
View File

@ -1041,7 +1041,7 @@
};
&sleep_clk {
clock-frequency = <32000>;
clock-frequency = <32764>;
};
&spi4 {

504
arch/arm64/boot/dts/qcom/sm8650.dtsi
View File

@ -365,6 +365,40 @@
};
};
ete0 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu0>;
out-ports {
port {
ete0_out_funnel_ete: endpoint {
remote-endpoint = <&funnel_ete_in_ete0>;
};
};
};
};
funnel-ete {
compatible = "arm,coresight-static-funnel";
in-ports {
port {
funnel_ete_in_ete0: endpoint {
remote-endpoint = <&ete0_out_funnel_ete>;
};
};
};
out-ports {
port {
funnel_ete_out_funnel_apss: endpoint {
remote-endpoint = <&funnel_apss_in_funnel_ete>;
};
};
};
};
firmware {
scm: scm {
compatible = "qcom,scm-sm8650", "qcom,scm";
@ -2233,7 +2267,8 @@
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
@ -2241,7 +2276,8 @@
"msi4",
"msi5",
"msi6",
"msi7";
"msi7",
"global";
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
@ -2365,7 +2401,8 @@
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
@ -2373,7 +2410,8 @@
"msi4",
"msi5",
"msi6",
"msi7";
"msi7",
"global";
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
@ -2636,6 +2674,10 @@
qcom,gmu = <&gmu>;
#cooling-cells = <2>;
interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "gfx-mem";
status = "disabled";
zap-shader {
@ -2649,56 +2691,67 @@
opp-231000000 {
opp-hz = /bits/ 64 <231000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
opp-peak-kBps = <2136718>;
};
opp-310000000 {
opp-hz = /bits/ 64 <310000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
opp-peak-kBps = <2136718>;
};
opp-366000000 {
opp-hz = /bits/ 64 <366000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
opp-peak-kBps = <6074218>;
};
opp-422000000 {
opp-hz = /bits/ 64 <422000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-peak-kBps = <8171875>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
opp-peak-kBps = <8171875>;
};
opp-578000000 {
opp-hz = /bits/ 64 <578000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <8171875>;
};
opp-629000000 {
opp-hz = /bits/ 64 <629000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
opp-peak-kBps = <10687500>;
};
opp-680000000 {
opp-hz = /bits/ 64 <680000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <12449218>;
};
opp-720000000 {
opp-hz = /bits/ 64 <720000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
opp-peak-kBps = <12449218>;
};
opp-770000000 {
opp-hz = /bits/ 64 <770000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
opp-peak-kBps = <12449218>;
};
opp-834000000 {
opp-hz = /bits/ 64 <834000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
opp-peak-kBps = <14398437>;
};
};
};
@ -2853,7 +2906,7 @@
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sm8650-mpss-pas";
reg = <0 0x04080000 0 0x4040>;
reg = <0x0 0x04080000 0x0 0x10000>;
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
@ -2904,6 +2957,154 @@
};
};
remoteproc_adsp: remoteproc@6800000 {
compatible = "qcom,sm8650-adsp-pas";
reg = <0x0 0x06800000 0x0 0x10000>;
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
power-domains = <&rpmhpd RPMHPD_LCX>,
<&rpmhpd RPMHPD_LMX>;
power-domain-names = "lcx",
"lmx";
memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
remoteproc_adsp_glink: glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
qcom,remote-pid = <2>;
label = "lpass";
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x1003 0x80>,
<&apps_smmu 0x1043 0x20>;
dma-coherent;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x1004 0x80>,
<&apps_smmu 0x1044 0x20>;
dma-coherent;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x1005 0x80>,
<&apps_smmu 0x1045 0x20>;
dma-coherent;
};
compute-cb@6 {
compatible = "qcom,fastrpc-compute-cb";
reg = <6>;
iommus = <&apps_smmu 0x1006 0x80>,
<&apps_smmu 0x1046 0x20>;
dma-coherent;
};
compute-cb@7 {
compatible = "qcom,fastrpc-compute-cb";
reg = <7>;
iommus = <&apps_smmu 0x1007 0x40>,
<&apps_smmu 0x1067 0x0>,
<&apps_smmu 0x1087 0x0>;
dma-coherent;
};
};
gpr {
compatible = "qcom,gpr";
qcom,glink-channels = "adsp_apps";
qcom,domain = <GPR_DOMAIN_ID_ADSP>;
qcom,intents = <512 20>;
#address-cells = <1>;
#size-cells = <0>;
q6apm: service@1 {
compatible = "qcom,q6apm";
reg = <GPR_APM_MODULE_IID>;
#sound-dai-cells = <0>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6apmbedai: bedais {
compatible = "qcom,q6apm-lpass-dais";
#sound-dai-cells = <1>;
};
q6apmdai: dais {
compatible = "qcom,q6apm-dais";
iommus = <&apps_smmu 0x1001 0x80>,
<&apps_smmu 0x1061 0x0>;
};
};
q6prm: service@2 {
compatible = "qcom,q6prm";
reg = <GPR_PRM_MODULE_IID>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6prmcc: clock-controller {
compatible = "qcom,q6prm-lpass-clocks";
#clock-cells = <2>;
};
};
};
};
};
lpass_wsa2macro: codec@6aa0000 {
compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
reg = <0 0x06aa0000 0 0x1000>;
@ -3455,11 +3656,8 @@
resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "mdp0-mem",
"mdp1-mem";
interconnect-names = "mdp0-mem";
power-domains = <&dispcc MDSS_GDSC>;
@ -4854,6 +5052,138 @@
};
};
funnel@10042000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x10042000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@4 {
reg = <4>;
funnel_in1_in_funnel_apss: endpoint {
remote-endpoint = <&funnel_apss_out_funnel_in1>;
};
};
};
out-ports {
port {
funnel_in1_out_funnel_qdss: endpoint {
remote-endpoint = <&funnel_qdss_in_funnel_in1>;
};
};
};
};
funnel@10045000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x10045000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
funnel_qdss_in_funnel_in1: endpoint {
remote-endpoint = <&funnel_in1_out_funnel_qdss>;
};
};
};
out-ports {
port {
funnel_qdss_out_funnel_aoss: endpoint {
remote-endpoint = <&funnel_aoss_in_funnel_qdss>;
};
};
};
};
funnel@10b04000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x10b04000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@7 {
reg = <7>;
funnel_aoss_in_funnel_qdss: endpoint {
remote-endpoint = <&funnel_qdss_out_funnel_aoss>;
};
};
};
out-ports {
port {
funnel_aoss_out_tmc_etf: endpoint {
remote-endpoint = <&tmc_etf_in_funnel_aoss>;
};
};
};
};
tmc@10b05000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x0 0x10b05000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
tmc_etf_in_funnel_aoss: endpoint {
remote-endpoint = <&funnel_aoss_out_tmc_etf>;
};
};
};
};
funnel@13810000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x13810000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
funnel_apss_in_funnel_ete: endpoint {
remote-endpoint = <&funnel_ete_out_funnel_apss>;
};
};
};
out-ports {
port {
funnel_apss_out_funnel_in1: endpoint {
remote-endpoint = <&funnel_in1_in_funnel_apss>;
};
};
};
};
apps_smmu: iommu@15000000 {
compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
@ -5322,154 +5652,6 @@
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
};
remoteproc_adsp: remoteproc@30000000 {
compatible = "qcom,sm8650-adsp-pas";
reg = <0 0x30000000 0 0x100>;
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
power-domains = <&rpmhpd RPMHPD_LCX>,
<&rpmhpd RPMHPD_LMX>;
power-domain-names = "lcx",
"lmx";
memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
remoteproc_adsp_glink: glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
qcom,remote-pid = <2>;
label = "lpass";
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x1003 0x80>,
<&apps_smmu 0x1043 0x20>;
dma-coherent;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x1004 0x80>,
<&apps_smmu 0x1044 0x20>;
dma-coherent;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x1005 0x80>,
<&apps_smmu 0x1045 0x20>;
dma-coherent;
};
compute-cb@6 {
compatible = "qcom,fastrpc-compute-cb";
reg = <6>;
iommus = <&apps_smmu 0x1006 0x80>,
<&apps_smmu 0x1046 0x20>;
dma-coherent;
};
compute-cb@7 {
compatible = "qcom,fastrpc-compute-cb";
reg = <7>;
iommus = <&apps_smmu 0x1007 0x40>,
<&apps_smmu 0x1067 0x0>,
<&apps_smmu 0x1087 0x0>;
dma-coherent;
};
};
gpr {
compatible = "qcom,gpr";
qcom,glink-channels = "adsp_apps";
qcom,domain = <GPR_DOMAIN_ID_ADSP>;
qcom,intents = <512 20>;
#address-cells = <1>;
#size-cells = <0>;
q6apm: service@1 {
compatible = "qcom,q6apm";
reg = <GPR_APM_MODULE_IID>;
#sound-dai-cells = <0>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6apmbedai: bedais {
compatible = "qcom,q6apm-lpass-dais";
#sound-dai-cells = <1>;
};
q6apmdai: dais {
compatible = "qcom,q6apm-dais";
iommus = <&apps_smmu 0x1001 0x80>,
<&apps_smmu 0x1061 0x0>;
};
};
q6prm: service@2 {
compatible = "qcom,q6prm";
reg = <GPR_PRM_MODULE_IID>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6prmcc: clock-controller {
compatible = "qcom,q6prm-lpass-clocks";
#clock-cells = <2>;
};
};
};
};
};
nsp_noc: interconnect@320c0000 {
compatible = "qcom,sm8650-nsp-noc";
reg = <0 0x320c0000 0 0xf080>;
@ -5481,7 +5663,7 @@
remoteproc_cdsp: remoteproc@32300000 {
compatible = "qcom,sm8650-cdsp-pas";
reg = <0 0x32300000 0 0x1400000>;
reg = <0x0 0x32300000 0x0 0x10000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
@ -5622,7 +5804,7 @@
/* note: secure cb9 in downstream */
compute-cb@10 {
compute-cb@12 {
compatible = "qcom,fastrpc-compute-cb";
reg = <12>;
@ -5632,7 +5814,7 @@
dma-coherent;
};
compute-cb@11 {
compute-cb@13 {
compatible = "qcom,fastrpc-compute-cb";
reg = <13>;
@ -5642,7 +5824,7 @@
dma-coherent;
};
compute-cb@12 {
compute-cb@14 {
compatible = "qcom,fastrpc-compute-cb";
reg = <14>;

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