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drm/msm/dpu: get rid of DPU_CTL_FETCH_ACTIVE 

Continue migration to the MDSS-revision based checks and replace
DPU_CTL_FETCH_ACTIVE feature bit with the core_major_ver >= 7 check.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655379/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-10-3b2085a07884@oss.qualcomm.com
pull/1309/head
Dmitry Baryshkov 2025-05-22 22:03:29 +03:00 committed by Dmitry Baryshkov
parent ef31cf538b
commit 2287f32e32
3 changed files with 2 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
View File

@ -105,8 +105,7 @@
(BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
#define CTL_SC7280_MASK \
(BIT(DPU_CTL_FETCH_ACTIVE) | \
BIT(DPU_CTL_VM_CFG) | \
(BIT(DPU_CTL_VM_CFG) | \
BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
#define INTF_SC7180_MASK \

2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
View File

@ -132,14 +132,12 @@ enum {
/**
* CTL sub-blocks
* @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
* @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs)
* @DPU_CTL_VM_CFG: CTL config to support multiple VMs
* @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush
* @DPU_CTL_MAX
*/
enum {
DPU_CTL_SPLIT_DISPLAY = 0x1,
DPU_CTL_FETCH_ACTIVE,
DPU_CTL_VM_CFG,
DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
DPU_CTL_MAX

2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
View File

@ -809,7 +809,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
else
c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp;
if (c->caps->features & BIT(DPU_CTL_FETCH_ACTIVE))
if (mdss_ver->core_major_ver >= 7)
c->ops.set_active_fetch_pipes = dpu_hw_ctl_set_active_fetch_pipes;
c->idx = cfg->id;