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arm64: dts: freescale: Minor whitespace cleanup 

The DTS code coding style expects exactly one space around '=' or '{'
characters.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
pull/1354/merge
Krzysztof Kozlowski 2025-08-19 15:18:02 +02:00 committed by Shawn Guo
parent 3d25ef32f1
commit 22df6943dc
13 changed files with 36 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
View File

@ -256,7 +256,7 @@
};
&asrc0 {
fsl,asrc-rate = <48000>;
fsl,asrc-rate = <48000>;
};
&adc0 {

2
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
View File

@ -652,7 +652,7 @@
status = "okay";
};
&pcie0_ep{
&pcie0_ep {
phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pcieb>;

2
arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts
View File

@ -333,7 +333,7 @@
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp{
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4

2
arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso
View File

@ -20,7 +20,7 @@
pwms = <&pwm4 0 50000 0>;
power-supply = <&reg_vdd_3v3_s>;
enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
brightness-levels= <0 4 8 16 32 64 128 255>;
brightness-levels = <0 4 8 16 32 64 128 255>;
};
panel {

2
arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dts
View File

@ -36,7 +36,7 @@
max-speed = <100>;
};
&ecspi1{
&ecspi1 {
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
};

6
arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi
View File

@ -167,7 +167,7 @@
<&clk IMX8MP_VIDEO_PLL1>;
};
&ecspi1{
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs2>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW &gpio1 6 GPIO_ACTIVE_LOW>;
@ -565,7 +565,7 @@
status = "disabled";
};
&pcie{
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio4 20 GPIO_ACTIVE_LOW>;
@ -574,7 +574,7 @@
status = "okay";
};
&pcie_phy{
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
clocks = <&pcie0_refclk>;
clock-names = "ref";

2
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
View File

@ -309,7 +309,7 @@
};
&easrc {
fsl,asrc-rate = <48000>;
fsl,asrc-rate = <48000>;
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts
View File

@ -83,7 +83,7 @@
compatible = "ti,tsc2046e-adc";
reg = <0>;
pinctrl-0 = <&pinctrl_touch>;
pinctrl-names ="default";
pinctrl-names = "default";
spi-max-frequency = <1000000>;
interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
#io-channel-cells = <1>;

2
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
View File

@ -407,7 +407,7 @@
audio-cpu = <&sai1>;
audio-codec = <&wm8960>;
hp-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
audio-routing = "Headphone Jack", "HP_L",
audio-routing = "Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",

4
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
View File

@ -462,11 +462,11 @@
/* VPU Mailboxes */
&mu_m0 {
status="okay";
status = "okay";
};
&mu1_m0 {
status="okay";
status = "okay";
};
/* TODO MIPI CSI */

4
arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts
View File

@ -276,7 +276,7 @@
regulator-ramp-delay = <3125>;
};
buck4: BUCK4{
buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3400000>;
@ -284,7 +284,7 @@
regulator-always-on;
};
buck5: BUCK5{
buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3400000>;

2
arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
View File

@ -692,7 +692,7 @@
};
&scmi_iomuxc {
pinctrl_emdio: emdiogrp{
pinctrl_emdio: emdiogrp {
fsl,pins = <
IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x50e
IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e

40
arch/arm64/boot/dts/freescale/imx95.dtsi
View File

@ -260,35 +260,35 @@
sai1_mclk: clock-sai-mclk1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <0>;
clock-frequency = <0>;
clock-output-names = "sai1_mclk";
};
sai2_mclk: clock-sai-mclk2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <0>;
clock-frequency = <0>;
clock-output-names = "sai2_mclk";
};
sai3_mclk: clock-sai-mclk3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <0>;
clock-frequency = <0>;
clock-output-names = "sai3_mclk";
};
sai4_mclk: clock-sai-mclk4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <0>;
clock-frequency = <0>;
clock-output-names = "sai4_mclk";
};
sai5_mclk: clock-sai-mclk5 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <0>;
clock-frequency = <0>;
clock-output-names = "sai5_mclk";
};
@ -1212,7 +1212,7 @@
assigned-clock-rates = <400000000>;
bus-width = <8>;
fsl,tuning-start-tap = <1>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
status = "disabled";
};
@ -1229,7 +1229,7 @@
assigned-clock-rates = <400000000>;
bus-width = <4>;
fsl,tuning-start-tap = <1>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
status = "disabled";
};
@ -1246,7 +1246,7 @@
assigned-clock-rates = <400000000>;
bus-width = <4>;
fsl,tuning-start-tap = <1>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
status = "disabled";
};
};
@ -1846,9 +1846,9 @@
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
<&hsio_blk_ctl 0>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
assigned-clock-parents = <0>, <0>,
<&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
@ -1880,9 +1880,9 @@
<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
assigned-clock-parents = <0>, <0>,
<&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
@ -1920,9 +1920,9 @@
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
<&hsio_blk_ctl 0>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
assigned-clock-parents = <0>, <0>,
<&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
@ -1956,9 +1956,9 @@
<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
assigned-clock-parents = <0>, <0>,
<&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;