Merge branch 'pci/resources'
- Restore VF resizable BAR state after reset (Michał Winiarski) - Add pci_resource_num_to_vf_bar() and pci_resource_num_from_vf_bar() to convert between VF BAR number and the dev->resource[] index (Michał Winiarski) - Allow IOV resources (VF BARs) to be resized (Michał Winiarski) - Add pci_iov_vf_bar_set_size() so drivers can control VF BAR size (Michał Winiarski) * pci/resources: PCI/IOV: Allow drivers to control VF BAR size PCI/IOV: Check that VF BAR fits within the reservation PCI/IOV: Allow IOV resources to be resized in pci_resize_resource() PCI/IOV: Add pci_resource_num_to_vf_bar() to convert VF BAR number to/from IOV resource PCI/IOV: Restore VF resizable BAR state after resetpull/1320/head
Bjorn Helgaas
commit
29ccb7b97e
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@ -7,11 +7,16 @@
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* Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/log2.h>
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#include <linux/pci.h>
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#include <linux/sizes.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include <asm/div64.h>
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#include "pci.h"
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#define VIRTFN_ID_LEN 17 /* "virtfn%u\0" for 2^32 - 1 */
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@ -150,7 +155,28 @@ resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
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if (!dev->is_physfn)
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return 0;
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return dev->sriov->barsz[resno - PCI_IOV_RESOURCES];
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return dev->sriov->barsz[pci_resource_num_to_vf_bar(resno)];
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}
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void pci_iov_resource_set_size(struct pci_dev *dev, int resno,
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resource_size_t size)
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{
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if (!pci_resource_is_iov(resno)) {
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pci_warn(dev, "%s is not an IOV resource\n",
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pci_resource_name(dev, resno));
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return;
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}
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dev->sriov->barsz[pci_resource_num_to_vf_bar(resno)] = size;
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}
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bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev)
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{
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u16 cmd;
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pci_read_config_word(dev, dev->sriov->pos + PCI_SRIOV_CTRL, &cmd);
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return cmd & PCI_SRIOV_CTRL_MSE;
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}
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static void pci_read_vf_config_common(struct pci_dev *virtfn)
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@ -341,12 +367,14 @@ int pci_iov_add_virtfn(struct pci_dev *dev, int id)
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virtfn->multifunction = 0;
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for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
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res = &dev->resource[i + PCI_IOV_RESOURCES];
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int idx = pci_resource_num_from_vf_bar(i);
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res = &dev->resource[idx];
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if (!res->parent)
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continue;
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virtfn->resource[i].name = pci_name(virtfn);
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virtfn->resource[i].flags = res->flags;
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size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
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size = pci_iov_resource_size(dev, idx);
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resource_set_range(&virtfn->resource[i],
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res->start + size * id, size);
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rc = request_resource(res, &virtfn->resource[i]);
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@ -643,8 +671,13 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
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nres = 0;
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for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
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bars |= (1 << (i + PCI_IOV_RESOURCES));
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res = &dev->resource[i + PCI_IOV_RESOURCES];
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int idx = pci_resource_num_from_vf_bar(i);
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resource_size_t vf_bar_sz = pci_iov_resource_size(dev, idx);
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bars |= (1 << idx);
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res = &dev->resource[idx];
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if (vf_bar_sz * nr_virtfn > resource_size(res))
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continue;
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if (res->parent)
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nres++;
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}
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@ -810,8 +843,10 @@ found:
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nres = 0;
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for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
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res = &dev->resource[i + PCI_IOV_RESOURCES];
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res_name = pci_resource_name(dev, i + PCI_IOV_RESOURCES);
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int idx = pci_resource_num_from_vf_bar(i);
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res = &dev->resource[idx];
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res_name = pci_resource_name(dev, idx);
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/*
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* If it is already FIXED, don't change it, something
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@ -850,6 +885,7 @@ found:
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pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
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if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END)
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iov->link = PCI_DEVFN(PCI_SLOT(dev->devfn), iov->link);
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iov->vf_rebar_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_VF_REBAR);
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if (pdev)
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iov->dev = pci_dev_get(pdev);
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@ -869,7 +905,7 @@ fail_max_buses:
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dev->is_physfn = 0;
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failed:
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for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
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res = &dev->resource[i + PCI_IOV_RESOURCES];
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res = &dev->resource[pci_resource_num_from_vf_bar(i)];
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res->flags = 0;
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}
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@ -888,6 +924,30 @@ static void sriov_release(struct pci_dev *dev)
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dev->sriov = NULL;
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}
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static void sriov_restore_vf_rebar_state(struct pci_dev *dev)
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{
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unsigned int pos, nbars, i;
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u32 ctrl;
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pos = pci_iov_vf_rebar_cap(dev);
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if (!pos)
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return;
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pci_read_config_dword(dev, pos + PCI_VF_REBAR_CTRL, &ctrl);
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nbars = FIELD_GET(PCI_VF_REBAR_CTRL_NBAR_MASK, ctrl);
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for (i = 0; i < nbars; i++, pos += 8) {
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int bar_idx, size;
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pci_read_config_dword(dev, pos + PCI_VF_REBAR_CTRL, &ctrl);
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bar_idx = FIELD_GET(PCI_VF_REBAR_CTRL_BAR_IDX, ctrl);
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size = pci_rebar_bytes_to_size(dev->sriov->barsz[bar_idx]);
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ctrl &= ~PCI_VF_REBAR_CTRL_BAR_SIZE;
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ctrl |= FIELD_PREP(PCI_VF_REBAR_CTRL_BAR_SIZE, size);
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pci_write_config_dword(dev, pos + PCI_VF_REBAR_CTRL, ctrl);
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}
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}
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static void sriov_restore_state(struct pci_dev *dev)
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{
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int i;
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@ -907,7 +967,7 @@ static void sriov_restore_state(struct pci_dev *dev)
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pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, ctrl);
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for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
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pci_update_resource(dev, i + PCI_IOV_RESOURCES);
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pci_update_resource(dev, pci_resource_num_from_vf_bar(i));
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pci_write_config_dword(dev, iov->pos + PCI_SRIOV_SYS_PGSIZE, iov->pgsz);
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pci_iov_set_numvfs(dev, iov->num_VFs);
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@ -973,7 +1033,7 @@ void pci_iov_update_resource(struct pci_dev *dev, int resno)
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{
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struct pci_sriov *iov = dev->is_physfn ? dev->sriov : NULL;
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struct resource *res = pci_resource_n(dev, resno);
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int vf_bar = resno - PCI_IOV_RESOURCES;
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int vf_bar = pci_resource_num_to_vf_bar(resno);
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struct pci_bus_region region;
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u16 cmd;
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u32 new;
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@ -1047,8 +1107,10 @@ resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno)
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*/
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void pci_restore_iov_state(struct pci_dev *dev)
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{
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if (dev->is_physfn)
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if (dev->is_physfn) {
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sriov_restore_vf_rebar_state(dev);
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sriov_restore_state(dev);
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}
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}
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/**
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@ -1255,3 +1317,72 @@ int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn)
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return nr_virtfn;
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}
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EXPORT_SYMBOL_GPL(pci_sriov_configure_simple);
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/**
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* pci_iov_vf_bar_set_size - set a new size for a VF BAR
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* @dev: the PCI device
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* @resno: the resource number
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* @size: new size as defined in the spec (0=1MB, 31=128TB)
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*
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* Set the new size of a VF BAR that supports VF resizable BAR capability.
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* Unlike pci_resize_resource(), this does not cause the resource that
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* reserves the MMIO space (originally up to total_VFs) to be resized, which
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* means that following calls to pci_enable_sriov() can fail if the resources
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* no longer fit.
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*
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* Return: 0 on success, or negative on failure.
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*/
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int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size)
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{
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u32 sizes;
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int ret;
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if (!pci_resource_is_iov(resno))
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return -EINVAL;
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if (pci_iov_is_memory_decoding_enabled(dev))
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return -EBUSY;
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sizes = pci_rebar_get_possible_sizes(dev, resno);
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if (!sizes)
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return -ENOTSUPP;
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if (!(sizes & BIT(size)))
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return -EINVAL;
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ret = pci_rebar_set_size(dev, resno, size);
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if (ret)
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return ret;
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pci_iov_resource_set_size(dev, resno, pci_rebar_size_to_bytes(size));
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return 0;
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}
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EXPORT_SYMBOL_GPL(pci_iov_vf_bar_set_size);
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/**
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* pci_iov_vf_bar_get_sizes - get VF BAR sizes allowing to create up to num_vfs
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* @dev: the PCI device
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* @resno: the resource number
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* @num_vfs: number of VFs
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*
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* Get the sizes of a VF resizable BAR that can accommodate @num_vfs within
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* the currently assigned size of the resource @resno.
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*
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* Return: A bitmask of sizes in format defined in the spec (bit 0=1MB,
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* bit 31=128TB).
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*/
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u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs)
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{
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u64 vf_len = pci_resource_len(dev, resno);
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u32 sizes;
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if (!num_vfs)
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return 0;
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do_div(vf_len, num_vfs);
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sizes = (roundup_pow_of_two(vf_len + 1) - 1) >> ilog2(SZ_1M);
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return sizes & pci_rebar_get_possible_sizes(dev, resno);
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}
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EXPORT_SYMBOL_GPL(pci_iov_vf_bar_get_sizes);
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@ -3756,7 +3756,13 @@ static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
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unsigned int pos, nbars, i;
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u32 ctrl;
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pos = pdev->rebar_cap;
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if (pci_resource_is_iov(bar)) {
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pos = pci_iov_vf_rebar_cap(pdev);
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bar = pci_resource_num_to_vf_bar(bar);
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} else {
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pos = pdev->rebar_cap;
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}
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if (!pos)
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return -ENOTSUPP;
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@ -492,6 +492,7 @@ struct pci_sriov {
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u16 subsystem_vendor; /* VF subsystem vendor */
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u16 subsystem_device; /* VF subsystem device */
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resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
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u16 vf_rebar_cap; /* VF Resizable BAR capability offset */
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bool drivers_autoprobe; /* Auto probing of VFs by driver */
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};
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@ -716,10 +717,28 @@ void pci_iov_update_resource(struct pci_dev *dev, int resno);
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resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
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void pci_restore_iov_state(struct pci_dev *dev);
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int pci_iov_bus_range(struct pci_bus *bus);
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void pci_iov_resource_set_size(struct pci_dev *dev, int resno,
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resource_size_t size);
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bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev);
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static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev)
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{
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if (!dev->is_physfn)
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return 0;
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return dev->sriov->vf_rebar_cap;
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}
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static inline bool pci_resource_is_iov(int resno)
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{
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return resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END;
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}
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static inline int pci_resource_num_from_vf_bar(int resno)
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{
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return resno + PCI_IOV_RESOURCES;
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}
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static inline int pci_resource_num_to_vf_bar(int resno)
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{
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return resno - PCI_IOV_RESOURCES;
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}
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extern const struct attribute_group sriov_pf_dev_attr_group;
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extern const struct attribute_group sriov_vf_dev_attr_group;
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#else
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@ -740,10 +759,30 @@ static inline int pci_iov_bus_range(struct pci_bus *bus)
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{
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return 0;
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}
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static inline void pci_iov_resource_set_size(struct pci_dev *dev, int resno,
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resource_size_t size) { }
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static inline bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev)
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{
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return false;
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}
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static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev)
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{
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return 0;
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}
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static inline bool pci_resource_is_iov(int resno)
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{
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return false;
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}
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static inline int pci_resource_num_from_vf_bar(int resno)
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{
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WARN_ON_ONCE(1);
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return -ENODEV;
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}
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static inline int pci_resource_num_to_vf_bar(int resno)
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{
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WARN_ON_ONCE(1);
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return -ENODEV;
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}
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#endif /* CONFIG_PCI_IOV */
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#ifdef CONFIG_PCIE_TPH
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@ -1888,7 +1888,8 @@ static int iov_resources_unassigned(struct pci_dev *dev, void *data)
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bool *unassigned = data;
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for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
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struct resource *r = &dev->resource[i + PCI_IOV_RESOURCES];
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int idx = pci_resource_num_from_vf_bar(i);
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struct resource *r = &dev->resource[idx];
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struct pci_bus_region region;
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/* Not assigned or rejected by kernel? */
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|
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@ -423,13 +423,39 @@ void pci_release_resource(struct pci_dev *dev, int resno)
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}
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EXPORT_SYMBOL(pci_release_resource);
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static bool pci_resize_is_memory_decoding_enabled(struct pci_dev *dev,
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int resno)
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{
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u16 cmd;
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if (pci_resource_is_iov(resno))
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return pci_iov_is_memory_decoding_enabled(dev);
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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return cmd & PCI_COMMAND_MEMORY;
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}
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static void pci_resize_resource_set_size(struct pci_dev *dev, int resno,
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int size)
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{
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resource_size_t res_size = pci_rebar_size_to_bytes(size);
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struct resource *res = pci_resource_n(dev, resno);
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if (!pci_resource_is_iov(resno)) {
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resource_set_size(res, res_size);
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} else {
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resource_set_size(res, res_size * pci_sriov_get_totalvfs(dev));
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pci_iov_resource_set_size(dev, resno, res_size);
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}
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}
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int pci_resize_resource(struct pci_dev *dev, int resno, int size)
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{
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struct resource *res = pci_resource_n(dev, resno);
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struct pci_host_bridge *host;
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int old, ret;
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u32 sizes;
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u16 cmd;
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/* Check if we must preserve the firmware's resource assignment */
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host = pci_find_host_bridge(dev->bus);
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@ -440,8 +466,7 @@ int pci_resize_resource(struct pci_dev *dev, int resno, int size)
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if (!(res->flags & IORESOURCE_UNSET))
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return -EBUSY;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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if (cmd & PCI_COMMAND_MEMORY)
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if (pci_resize_is_memory_decoding_enabled(dev, resno))
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return -EBUSY;
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sizes = pci_rebar_get_possible_sizes(dev, resno);
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|
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@ -459,7 +484,7 @@ int pci_resize_resource(struct pci_dev *dev, int resno, int size)
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if (ret)
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return ret;
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resource_set_size(res, pci_rebar_size_to_bytes(size));
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pci_resize_resource_set_size(dev, resno, size);
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/* Check if the new config works by trying to assign everything. */
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if (dev->bus->self) {
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|
@ -471,7 +496,7 @@ int pci_resize_resource(struct pci_dev *dev, int resno, int size)
|
|||
|
||||
error_resize:
|
||||
pci_rebar_set_size(dev, resno, old);
|
||||
resource_set_size(res, pci_rebar_size_to_bytes(old));
|
||||
pci_resize_resource_set_size(dev, resno, old);
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(pci_resize_resource);
|
||||
|
|
|
|||
|
|
@ -2459,6 +2459,8 @@ int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
|
|||
int pci_sriov_get_totalvfs(struct pci_dev *dev);
|
||||
int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
|
||||
resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
|
||||
int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size);
|
||||
u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs);
|
||||
void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
|
||||
|
||||
/* Arch may override these (weak) */
|
||||
|
|
@ -2511,6 +2513,10 @@ static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
|
|||
#define pci_sriov_configure_simple NULL
|
||||
static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
|
||||
{ return 0; }
|
||||
static inline int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size)
|
||||
{ return -ENODEV; }
|
||||
static inline u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs)
|
||||
{ return 0; }
|
||||
static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -745,6 +745,7 @@
|
|||
#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
|
||||
#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
|
||||
#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */
|
||||
#define PCI_EXT_CAP_ID_VF_REBAR 0x24 /* VF Resizable BAR */
|
||||
#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
|
||||
#define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */
|
||||
#define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */
|
||||
|
|
@ -1141,6 +1142,14 @@
|
|||
#define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */
|
||||
#define PCI_DVSEC_HEADER2_ID(x) ((x) & 0xffff)
|
||||
|
||||
/* VF Resizable BARs, same layout as PCI_REBAR */
|
||||
#define PCI_VF_REBAR_CAP PCI_REBAR_CAP
|
||||
#define PCI_VF_REBAR_CAP_SIZES PCI_REBAR_CAP_SIZES
|
||||
#define PCI_VF_REBAR_CTRL PCI_REBAR_CTRL
|
||||
#define PCI_VF_REBAR_CTRL_BAR_IDX PCI_REBAR_CTRL_BAR_IDX
|
||||
#define PCI_VF_REBAR_CTRL_NBAR_MASK PCI_REBAR_CTRL_NBAR_MASK
|
||||
#define PCI_VF_REBAR_CTRL_BAR_SIZE PCI_REBAR_CTRL_BAR_SIZE
|
||||
|
||||
/* Data Link Feature */
|
||||
#define PCI_DLF_CAP 0x04 /* Capabilities Register */
|
||||
#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */
|
||||
|
|
|
|||
Loading…
Reference in New Issue