arm64: dts: renesas: r8a779g0: Add WWDT nodes

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251215034715.3406-13-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
master
Wolfram Sang 2025-12-15 12:47:19 +09:00 committed by Geert Uytterhoeven
parent b7c182ff32
commit 2dc4f97074
1 changed files with 112 additions and 0 deletions

View File

@ -2544,6 +2544,118 @@
};
};
wwdt0: watchdog@ffc90000 {
compatible = "renesas,r8a779g0-wwdt",
"renesas,rcar-gen4-wwdt";
reg = <0 0xffc90000 0 0x10>;
interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pretimeout", "error";
clocks = <&cpg CPG_CORE R8A779G0_CLK_R>,
<&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>;
clock-names = "cnt", "bus";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 1200>;
reset-names = "cnt";
status = "disabled";
};
wwdt1: watchdog@ffca0000 {
compatible = "renesas,r8a779g0-wwdt",
"renesas,rcar-gen4-wwdt";
reg = <0 0xffca0000 0 0x10>;
interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pretimeout", "error";
clocks = <&cpg CPG_CORE R8A779G0_CLK_R>,
<&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>;
clock-names = "cnt", "bus";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 1201>;
reset-names = "cnt";
status = "disabled";
};
wwdt2: watchdog@ffcb0000 {
compatible = "renesas,r8a779g0-wwdt",
"renesas,rcar-gen4-wwdt";
reg = <0 0xffcb0000 0 0x10>;
interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pretimeout", "error";
clocks = <&cpg CPG_CORE R8A779G0_CLK_R>,
<&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>;
clock-names = "cnt", "bus";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 1202>;
reset-names = "cnt";
status = "disabled";
};
wwdt3: watchdog@ffcc0000 {
compatible = "renesas,r8a779g0-wwdt",
"renesas,rcar-gen4-wwdt";
reg = <0 0xffcc0000 0 0x10>;
interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pretimeout", "error";
clocks = <&cpg CPG_CORE R8A779G0_CLK_R>,
<&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>;
clock-names = "cnt", "bus";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 1203>;
reset-names = "cnt";
status = "disabled";
};
wwdt4: watchdog@ffcf0000 {
compatible = "renesas,r8a779g0-wwdt",
"renesas,rcar-gen4-wwdt";
reg = <0 0xffcf0000 0 0x10>;
interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pretimeout", "error";
clocks = <&cpg CPG_CORE R8A779G0_CLK_R>,
<&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>;
clock-names = "cnt", "bus";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 1204>;
reset-names = "cnt";
status = "disabled";
};
wwdt5: watchdog@ffef0000 {
compatible = "renesas,r8a779g0-wwdt",
"renesas,rcar-gen4-wwdt";
reg = <0 0xffef0000 0 0x10>;
interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pretimeout", "error";
clocks = <&cpg CPG_CORE R8A779G0_CLK_R>,
<&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>;
clock-names = "cnt", "bus";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 1205>;
reset-names = "cnt";
status = "disabled";
};
wwdt6: watchdog@fff10000 {
compatible = "renesas,r8a779g0-wwdt",
"renesas,rcar-gen4-wwdt";
reg = <0 0xfff10000 0 0x10>;
interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pretimeout", "error";
clocks = <&cpg CPG_CORE R8A779G0_CLK_R>,
<&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>;
clock-names = "cnt", "bus";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 1206>;
reset-names = "cnt";
status = "disabled";
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;