arm64: dts: imx8mp libra: add and update display overlays

Add imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtso
devicetree display overlay for the i.MX8MP Libra RDK platform.
The overlay enable LVDS display configuration.

To keep the consistent style of panel and backlight nodes and labels.
They are updated in imx8mp-libra base board devicetree and
etml1010g3dra display overlay.

Signed-off-by: Yashwanth Varakala <y.varakala@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
master
Yashwanth Varakala 2025-11-17 13:45:14 +01:00 committed by Shawn Guo
parent bfc1982c66
commit 3619c5b41e
4 changed files with 53 additions and 5 deletions

View File

@ -225,8 +225,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-dl.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-smarc-eval-carrier.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc.dtb
imx8mp-libra-rdk-fpsc-lvds-dtbs += imx8mp-libra-rdk-fpsc.dtb imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds.dtb
imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra-dtbs += imx8mp-libra-rdk-fpsc.dtb \
imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtbo
imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01-dtbs += imx8mp-libra-rdk-fpsc.dtb \
imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-enc-carrier-board.dtb

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@ -34,7 +34,7 @@
status = "okay";
};
&panel0_lvds {
&panel_lvds0 {
compatible = "edt,etml1010g3dra";
status = "okay";
};

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@ -0,0 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/imx8mp-clock.h>
/dts-v1/;
/plugin/;
&backlight_lvds0 {
brightness-levels = <0 8 16 32 64 128 255>;
default-brightness-level = <8>;
enable-gpios = <&gpio5 23 GPIO_ACTIVE_LOW>;
num-interpolated-steps = <2>;
pwms = <&pwm1 0 66667 0>;
status = "okay";
};
&lcdif2 {
status = "okay";
};
&lvds_bridge {
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
/*
* The LVDS panel uses 66.5 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to
* 66.5 * 7 = 465.5 MHz so the LDB serializer and LCDIFv3 scanout
* engine can reach accurate pixel clock of exactly 66.5 MHz.
*/
assigned-clock-rates = <0>, <465500000>;
status = "okay";
};
&panel_lvds0 {
compatible = "powertip,ph128800t006-zhc01";
status = "okay";
};
&pwm1 {
status = "okay";
};

View File

@ -15,7 +15,7 @@
"phytec,imx8mp-phycore-fpsc", "fsl,imx8mp";
model = "PHYTEC i.MX8MP Libra RDK FPSC";
backlight_lvds0: backlight0 {
backlight_lvds0: backlight-lvds0 {
compatible = "pwm-backlight";
pinctrl-0 = <&pinctrl_lvds0>;
pinctrl-names = "default";
@ -27,7 +27,7 @@
stdout-path = &uart4;
};
panel0_lvds: panel-lvds {
panel_lvds0: panel-lvds0 {
/* compatible panel in overlay */
backlight = <&backlight_lvds0>;
power-supply = <&reg_vdd_3v3>;