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Devicetree for v6.15: 

DT core:
 - Fix ref counting errors in interrupt parsing code
 
 - Allow "nonposted-mmio" property per device and on non-Apple h/w
 
 - Use typed accessors in platform driver code
 
 - Fix mismatch between DT MAX_PHANDLE_ARGS and NR_FWNODE_REFERENCE_ARGS
   and increase the maximum number args
 
 - Rework of_resolve_phandles() to use __free() cleanup and fix ref count
   error
 
 - Use of_prop_cmp() in a few more places
 
 - Improve make_fit.py script error handling
 
 DT bindings:
 - Update DT property ordering rules for properties within groups (i.e.
   common suffix)
 
 - Update DT submitting-patches doc to cover sending .dts patches and
   SoC maintainer rules on being warning free against linux-next
 
 - Add ti,tps53681, ti,tps53681, Maxim max15301, max15303, and
   max20751 to trivial devices
 
 - Add Renesas RZ/V2H(P) and Allwinner H616 support to Arm Mali Bifrost
   GPU. Add Samsung exynos7870 support to Arm Mail Midgard.
 
 - Rework qcom,ebi2 and samsung,exynos4210-sram memory controller
   bindings to split child node properties. Fix the LAN9115 binding to
   use the child node schema so all properties are documented.
 
 - Convert nxp,lpc3220-mic and Altera ECC manager bindings to schema
 
 - Fix some issues with LVDS display panels causing validation warnings
 
 - Drop some obsolete parts of Xilinx bindings
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Merge tag 'devicetree-for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree updates from Rob Herring:
 "DT core:

   - Fix ref counting errors in interrupt parsing code

   - Allow "nonposted-mmio" property per device and on non-Apple h/w

   - Use typed accessors in platform driver code

   - Fix mismatch between DT MAX_PHANDLE_ARGS and
     NR_FWNODE_REFERENCE_ARGS and increase the maximum number args

   - Rework of_resolve_phandles() to use __free() cleanup and fix ref
     count error

   - Use of_prop_cmp() in a few more places

   - Improve make_fit.py script error handling

  DT bindings:

   - Update DT property ordering rules for properties within groups
     (i.e. common suffix)

   - Update DT submitting-patches doc to cover sending .dts patches and
     SoC maintainer rules on being warning free against linux-next

   - Add ti,tps53681, ti,tps53681, Maxim max15301, max15303, and
     max20751 to trivial devices

   - Add Renesas RZ/V2H(P) and Allwinner H616 support to Arm Mali
     Bifrost GPU. Add Samsung exynos7870 support to Arm Mail Midgard.

   - Rework qcom,ebi2 and samsung,exynos4210-sram memory controller
     bindings to split child node properties. Fix the LAN9115 binding to
     use the child node schema so all properties are documented.

   - Convert nxp,lpc3220-mic and Altera ECC manager bindings to schema

   - Fix some issues with LVDS display panels causing validation
     warnings

   - Drop some obsolete parts of Xilinx bindings"

* tag 'devicetree-for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (48 commits)
  scripts/make_fit: Print DT name before libfdt errors
  dt-bindings: edac: altera: socfpga: Convert to YAML
  dt-bindings: pps: gpio: Correct indentation and style in DTS example
  media: dt-bindings: mediatek,vcodec-encoder: Drop assigned-clock properties
  of: address: Allow to specify nonposted-mmio per-device
  of: address: Expand nonposted-mmio to non-Apple Silicon platforms
  docs: dt-bindings: Specify ordering for properties within groups
  dt-bindings: gpu: arm,mali-midgard: add exynos7870-mali compatible
  of: Move of_prop_val_eq() next to the single user
  of/platform: Use typed accessors rather than of_get_property()
  dt-bindings: trivial-devices: Add Maxim max15301, max15303, and max20751
  dt-bindings: fsi: ibm,p9-scom: Add "ibm,fsi2pib" compatible
  dt-bindings: memory-controllers: qcom,ebi2: Enforce child props
  dt-bindings: memory-controllers: samsung,exynos4210-srom: Enforce child props
  dt-bindings: display: mitsubishi,aa104xd12: Adjust allowed and required properties
  dt-bindings: display: mitsubishi,aa104xd12: Allow jeida-18 for data-mapping
  dt-bindings: interrupt-controller: Convert nxp,lpc3220-mic.txt to yaml format
  docs: process: maintainer-soc-clean-dts: linux-next is decisive
  docs: dt: submitting-patches: Document sending DTS patches
  of: Align macro MAX_PHANDLE_ARGS with NR_FWNODE_REFERENCE_ARGS
  ...
pull/1188/head
Linus Torvalds 2025-03-29 11:23:16 -07:00
parent 092e335082 314655d41e
commit 3b9ea5b5ed
36 changed files with 764 additions and 707 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml
View File

@ -41,6 +41,7 @@ properties:
- enum:
- ti,ds90cf364a # For the DS90CF364A FPD-Link LVDS Receiver
- ti,ds90cf384a # For the DS90CF384A FPD-Link LVDS Receiver
- ti,sn65lvds822 # For the SN65LVDS822 FlatLink LVDS Receiver
- ti,sn65lvds94 # For the SN65DS94 LVDS serdes
- const: lvds-decoder # Generic LVDS decoders compatible fallback
- enum:

6
Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.yaml
View File

@ -33,7 +33,9 @@ properties:
description: Reference to the regulator powering the panel VCC pins.
data-mapping:
const: jeida-24
enum:
- jeida-18
- jeida-24
width-mm:
const: 210
@ -41,6 +43,7 @@ properties:
height-mm:
const: 158
backlight: true
panel-timing: true
port: true
@ -48,7 +51,6 @@ additionalProperties: false
required:
- compatible
- vcc-supply
- data-mapping
- width-mm
- height-mm

8
Documentation/devicetree/bindings/dts-coding-style.rst
View File

@ -133,6 +133,9 @@ The above-described ordering follows this approach:
3. Status is the last information to annotate that device node is or is not
finished (board resources are needed).
The individual properties inside each group shall use natural sort order by
the property name.
Example::
/* SoC DTSI */
@ -158,7 +161,10 @@ Example::
/* Board DTS */
&device_node {
vdd-supply = <&board_vreg1>;
vdd-0v9-supply = <&board_vreg1>;
vdd-1v8-supply = <&board_vreg4>;
vdd-3v3-supply = <&board_vreg2>;
vdd-12v-supply = <&board_vreg3>;
status = "okay";
}

323
Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml Normal file
View File

@ -0,0 +1,323 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright (C) 2025 Altera Corporation
%YAML 1.2
---
$id: http://devicetree.org/schemas/edac/altr,socfpga-ecc-manager.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Altera SoCFPGA ECC Manager
maintainers:
- Matthew Gerlach <matthew.gerlach@altera.com>
description:
This binding describes the device tree nodes required for the Altera SoCFPGA
ECC Manager for the Cyclone5, Arria5, Arria10, Stratix10, and Agilex chip
families.
properties:
compatible:
oneOf:
- items:
- const: altr,socfpga-s10-ecc-manager
- const: altr,socfpga-a10-ecc-manager
- const: altr,socfpga-a10-ecc-manager
- const: altr,socfpga-ecc-manager
"#address-cells":
const: 1
"#size-cells":
const: 1
interrupts:
minItems: 1
maxItems: 2
interrupt-controller: true
"#interrupt-cells":
const: 2
ranges: true
altr,sysmgr-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to Stratix10 System Manager Block with the ECC manager registers
sdramedac:
type: object
additionalProperties: false
properties:
compatible:
enum:
- altr,sdram-edac-a10
- altr,sdram-edac-s10
interrupts:
minItems: 1
maxItems: 2
altr,sdr-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to SDRAM parent
required:
- compatible
- interrupts
- altr,sdr-syscon
patternProperties:
"^ocram-ecc@[a-f0-9]+$":
type: object
additionalProperties: false
properties:
compatible:
oneOf:
- items:
- const: altr,socfpga-s10-ocram-ecc
- const: altr,socfpga-a10-ocram-ecc
- const: altr,socfpga-a10-ocram-ecc
- const: altr,socfpga-ocram-ecc
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
iram:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to OCRAM parent
altr,ecc-parent:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to OCRAM parent
required:
- compatible
- reg
- interrupts
"^usb[0-9]-ecc@[a-f0-9]+$":
type: object
additionalProperties: false
properties:
compatible:
oneOf:
- items:
- const: altr,socfpga-s10-usb-ecc
- const: altr,socfpga-usb-ecc
- const: altr,socfpga-usb-ecc
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
altr,ecc-parent:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to USB parent
required:
- compatible
- reg
- interrupts
- altr,ecc-parent
"^emac[0-9]-[t,r]x-ecc@[a-f0-9]+$":
type: object
additionalProperties: false
properties:
compatible:
oneOf:
- items:
- const: altr,socfpga-s10-eth-mac-ecc
- const: altr,socfpga-eth-mac-ecc
- const: altr,socfpga-eth-mac-ecc
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
altr,ecc-parent:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to ethernet parent
required:
- compatible
- reg
- interrupts
- altr,ecc-parent
"^sdmmc[a-f]-ecc@[a-f0-9]+$":
type: object
additionalProperties: false
properties:
compatible:
oneOf:
- items:
- const: altr,socfpga-s10-sdmmc-ecc
- const: altr,socfpga-sdmmc-ecc
- const: altr,socfpga-sdmmc-ecc
reg:
maxItems: 1
interrupts:
minItems: 2
maxItems: 4
altr,ecc-parent:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to SD/MMC parent
required:
- compatible
- reg
- interrupts
- altr,ecc-parent
"^l2-ecc@[a-f0-9]+$":
type: object
additionalProperties: false
properties:
compatible:
enum:
- altr,socfpga-a10-l2-ecc
- altr,socfpga-l2-ecc
reg:
maxItems: 1
interrupts:
maxItems: 2
required:
- compatible
- reg
- interrupts
"^dma-ecc@[a-f0-9]+$":
type: object
additionalProperties: false
properties:
compatible:
const: altr,socfpga-dma-ecc
reg:
maxItems: 1
interrupts:
maxItems: 2
altr,ecc-parent:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to SD/MMC parent
required:
- compatible
- reg
- interrupts
- altr,ecc-parent
if:
properties:
compatible:
contains:
const: altr,socfpga-ecc-manager
then:
required:
- compatible
- "#address-cells"
- "#size-cells"
- ranges
else:
required:
- compatible
- "#address-cells"
- "#size-cells"
- interrupts
- interrupt-controller
- "#interrupt-cells"
- ranges
- altr,sysmgr-syscon
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
eccmgr {
compatible = "altr,socfpga-s10-ecc-manager",
"altr,socfpga-a10-ecc-manager";
altr,sysmgr-syscon = <&sysmgr>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
ranges;
sdramedac {
compatible = "altr,sdram-edac-s10";
altr,sdr-syscon = <&sdr>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
};
ocram-ecc@ff8cc000 {
compatible = "altr,socfpga-s10-ocram-ecc",
"altr,socfpga-a10-ocram-ecc";
reg = <0xff8cc000 0x100>;
altr,ecc-parent = <&ocram>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
};
usb0-ecc@ff8c4000 {
compatible = "altr,socfpga-s10-usb-ecc",
"altr,socfpga-usb-ecc";
reg = <0xff8c4000 0x100>;
altr,ecc-parent = <&usb0>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-rx-ecc@ff8c0000 {
compatible = "altr,socfpga-s10-eth-mac-ecc",
"altr,socfpga-eth-mac-ecc";
reg = <0xff8c0000 0x100>;
altr,ecc-parent = <&gmac0>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-tx-ecc@ff8c0400 {
compatible = "altr,socfpga-s10-eth-mac-ecc",
"altr,socfpga-eth-mac-ecc";
reg = <0xff8c0400 0x100>;
altr,ecc-parent = <&gmac0>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
};
sdmmca-ecc@ff8c8c00 {
compatible = "altr,socfpga-s10-sdmmc-ecc",
"altr,socfpga-sdmmc-ecc";
reg = <0xff8c8c00 0x100>;
altr,ecc-parent = <&mmc>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
<15 IRQ_TYPE_LEVEL_HIGH>;
};
};

383
Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
View File

@ -1,383 +0,0 @@
Altera SoCFPGA ECC Manager
This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
The ECC Manager counts and corrects single bit errors and counts/handles
double bit errors which are uncorrectable.
Cyclone5 and Arria5 ECC Manager
Required Properties:
- compatible : Should be "altr,socfpga-ecc-manager"
- #address-cells: must be 1
- #size-cells: must be 1
- ranges : standard definition, should translate from local addresses
Subcomponents:
L2 Cache ECC
Required Properties:
- compatible : Should be "altr,socfpga-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt. Note the rising edge type.
On Chip RAM ECC
Required Properties:
- compatible : Should be "altr,socfpga-ocram-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- iram : phandle to On-Chip RAM definition.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt. Note the rising edge type.
Example:
eccmgr: eccmgr@ffd08140 {
compatible = "altr,socfpga-ecc-manager";
#address-cells = <1>;
#size-cells = <1>;
ranges;
l2-ecc@ffd08140 {
compatible = "altr,socfpga-l2-ecc";
reg = <0xffd08140 0x4>;
interrupts = <0 36 1>, <0 37 1>;
};
ocram-ecc@ffd08144 {
compatible = "altr,socfpga-ocram-ecc";
reg = <0xffd08144 0x4>;
iram = <&ocram>;
interrupts = <0 178 1>, <0 179 1>;
};
};
Arria10 SoCFPGA ECC Manager
The Arria10 SoC ECC Manager handles the IRQs for each peripheral
in a shared register instead of individual IRQs like the Cyclone5
and Arria5. Therefore the device tree is different as well.
Required Properties:
- compatible : Should be "altr,socfpga-a10-ecc-manager"
- altr,sysgr-syscon : phandle to Arria10 System Manager Block
containing the ECC manager registers.
- #address-cells: must be 1
- #size-cells: must be 1
- interrupts : Should be single bit error interrupt, then double bit error
interrupt.
- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
- #interrupt-cells : must be set to 2.
- ranges : standard definition, should translate from local addresses
Subcomponents:
L2 Cache ECC
Required Properties:
- compatible : Should be "altr,socfpga-a10-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
On-Chip RAM ECC
Required Properties:
- compatible : Should be "altr,socfpga-a10-ocram-ecc"
- reg : Address and size for ECC block registers.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
Ethernet FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-eth-mac-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent Ethernet node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
NAND FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-nand-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent NAND node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
DMA FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-dma-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent DMA node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
USB FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-usb-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent USB node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
QSPI FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-qspi-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent QSPI node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
SDMMC FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-sdmmc-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent SD/MMC node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order for port A, and then single bit error interrupt,
then double bit error interrupt in this order for port B.
Example:
eccmgr: eccmgr@ffd06000 {
compatible = "altr,socfpga-a10-ecc-manager";
altr,sysmgr-syscon = <&sysmgr>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
<0 0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
ranges;
l2-ecc@ffd06010 {
compatible = "altr,socfpga-a10-l2-ecc";
reg = <0xffd06010 0x4>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
<32 IRQ_TYPE_LEVEL_HIGH>;
};
ocram-ecc@ff8c3000 {
compatible = "altr,socfpga-a10-ocram-ecc";
reg = <0xff8c3000 0x90>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
<33 IRQ_TYPE_LEVEL_HIGH> ;
};
emac0-rx-ecc@ff8c0800 {
compatible = "altr,socfpga-eth-mac-ecc";
reg = <0xff8c0800 0x400>;
altr,ecc-parent = <&gmac0>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
<36 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-tx-ecc@ff8c0c00 {
compatible = "altr,socfpga-eth-mac-ecc";
reg = <0xff8c0c00 0x400>;
altr,ecc-parent = <&gmac0>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
<37 IRQ_TYPE_LEVEL_HIGH>;
};
nand-buf-ecc@ff8c2000 {
compatible = "altr,socfpga-nand-ecc";
reg = <0xff8c2000 0x400>;
altr,ecc-parent = <&nand>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>,
<43 IRQ_TYPE_LEVEL_HIGH>;
};
nand-rd-ecc@ff8c2400 {
compatible = "altr,socfpga-nand-ecc";
reg = <0xff8c2400 0x400>;
altr,ecc-parent = <&nand>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>,
<45 IRQ_TYPE_LEVEL_HIGH>;
};
nand-wr-ecc@ff8c2800 {
compatible = "altr,socfpga-nand-ecc";
reg = <0xff8c2800 0x400>;
altr,ecc-parent = <&nand>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
<44 IRQ_TYPE_LEVEL_HIGH>;
};
dma-ecc@ff8c8000 {
compatible = "altr,socfpga-dma-ecc";
reg = <0xff8c8000 0x400>;
altr,ecc-parent = <&pdma>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
<42 IRQ_TYPE_LEVEL_HIGH>;
usb0-ecc@ff8c8800 {
compatible = "altr,socfpga-usb-ecc";
reg = <0xff8c8800 0x400>;
altr,ecc-parent = <&usb0>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
<34 IRQ_TYPE_LEVEL_HIGH>;
};
qspi-ecc@ff8c8400 {
compatible = "altr,socfpga-qspi-ecc";
reg = <0xff8c8400 0x400>;
altr,ecc-parent = <&qspi>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
<46 IRQ_TYPE_LEVEL_HIGH>;
};
sdmmc-ecc@ff8c2c00 {
compatible = "altr,socfpga-sdmmc-ecc";
reg = <0xff8c2c00 0x400>;
altr,ecc-parent = <&mmc>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
<47 IRQ_TYPE_LEVEL_HIGH>,
<16 IRQ_TYPE_LEVEL_HIGH>,
<48 IRQ_TYPE_LEVEL_HIGH>;
};
};
Stratix10 SoCFPGA ECC Manager (ARM64)
The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
in a shared register similar to the Arria10. However, Stratix10 ECC
requires access to registers that can only be read from Secure Monitor
with SMC calls. Therefore the device tree is slightly different. Note
that only 1 interrupt is sent in Stratix10 because the double bit errors
are treated as SErrors in ARM64 instead of IRQs in ARM32.
Required Properties:
- compatible : Should be "altr,socfpga-s10-ecc-manager"
- altr,sysgr-syscon : phandle to Stratix10 System Manager Block
containing the ECC manager registers.
- interrupts : Should be single bit error interrupt.
- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
- #interrupt-cells : must be set to 2.
- #address-cells: must be 1
- #size-cells: must be 1
- ranges : standard definition, should translate from local addresses
Subcomponents:
SDRAM ECC
Required Properties:
- compatible : Should be "altr,sdram-edac-s10"
- interrupts : Should be single bit error interrupt.
On-Chip RAM ECC
Required Properties:
- compatible : Should be "altr,socfpga-s10-ocram-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent OCRAM node.
- interrupts : Should be single bit error interrupt.
Ethernet FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-s10-eth-mac-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent Ethernet node.
- interrupts : Should be single bit error interrupt.
NAND FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-s10-nand-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent NAND node.
- interrupts : Should be single bit error interrupt.
DMA FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-s10-dma-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent DMA node.
- interrupts : Should be single bit error interrupt.
USB FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-s10-usb-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent USB node.
- interrupts : Should be single bit error interrupt.
SDMMC FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-s10-sdmmc-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent SD/MMC node.
- interrupts : Should be single bit error interrupt for port A
and then single bit error interrupt for port B.
Example:
eccmgr {
compatible = "altr,socfpga-s10-ecc-manager";
altr,sysmgr-syscon = <&sysmgr>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <0 15 4>;
interrupt-controller;
#interrupt-cells = <2>;
ranges;
sdramedac {
compatible = "altr,sdram-edac-s10";
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
};
ocram-ecc@ff8cc000 {
compatible = "altr,socfpga-s10-ocram-ecc";
reg = <ff8cc000 0x100>;
altr,ecc-parent = <&ocram>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-rx-ecc@ff8c0000 {
compatible = "altr,socfpga-s10-eth-mac-ecc";
reg = <0xff8c0000 0x100>;
altr,ecc-parent = <&gmac0>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-tx-ecc@ff8c0400 {
compatible = "altr,socfpga-s10-eth-mac-ecc";
reg = <0xff8c0400 0x100>;
altr,ecc-parent = <&gmac0>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>'
};
nand-buf-ecc@ff8c8000 {
compatible = "altr,socfpga-s10-nand-ecc";
reg = <0xff8c8000 0x100>;
altr,ecc-parent = <&nand>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
};
nand-rd-ecc@ff8c8400 {
compatible = "altr,socfpga-s10-nand-ecc";
reg = <0xff8c8400 0x100>;
altr,ecc-parent = <&nand>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
};
nand-wr-ecc@ff8c8800 {
compatible = "altr,socfpga-s10-nand-ecc";
reg = <0xff8c8800 0x100>;
altr,ecc-parent = <&nand>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
};
dma-ecc@ff8c9000 {
compatible = "altr,socfpga-s10-dma-ecc";
reg = <0xff8c9000 0x100>;
altr,ecc-parent = <&pdma>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
usb0-ecc@ff8c4000 {
compatible = "altr,socfpga-s10-usb-ecc";
reg = <0xff8c4000 0x100>;
altr,ecc-parent = <&usb0>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
};
sdmmc-ecc@ff8c8c00 {
compatible = "altr,socfpga-s10-sdmmc-ecc";
reg = <0xff8c8c00 0x100>;
altr,ecc-parent = <&mmc>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
<15 IRQ_TYPE_LEVEL_HIGH>;
};
};

1
Documentation/devicetree/bindings/fsi/ibm,p9-scom.yaml
View File

@ -16,6 +16,7 @@ description:
properties:
compatible:
enum:
- ibm,fsi2pib
- ibm,p9-scom
- ibm,i2cr-scom

3
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
View File

@ -17,6 +17,7 @@ properties:
oneOf:
- items:
- enum:
- allwinner,sun50i-h616-mali
- amlogic,meson-g12a-mali
- mediatek,mt8183-mali
- mediatek,mt8183b-mali
@ -24,6 +25,7 @@ properties:
- realtek,rtd1619-mali
- renesas,r9a07g044-mali
- renesas,r9a07g054-mali
- renesas,r9a09g057-mali
- rockchip,px30-mali
- rockchip,rk3562-mali
- rockchip,rk3568-mali
@ -143,6 +145,7 @@ allOf:
enum:
- renesas,r9a07g044-mali
- renesas,r9a07g054-mali
- renesas,r9a09g057-mali
then:
properties:
interrupts:

5
Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml
View File

@ -45,12 +45,15 @@ properties:
- samsung,exynos7-mali
- const: samsung,exynos5433-mali
- const: arm,mali-t760
- items:
- enum:
- samsung,exynos7870-mali
- const: arm,mali-t830
- items:
- enum:
- rockchip,rk3399-mali
- const: arm,mali-t860
# "arm,mali-t830"
# "arm,mali-t880"
reg:

58
Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt
View File

@ -1,58 +0,0 @@
* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
Required properties:
- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
- reg: should contain IC registers location and length.
- interrupt-controller: identifies the node as an interrupt controller.
- #interrupt-cells: the number of cells to define an interrupt, should be 2.
The first cell is the IRQ number, the second cell is used to specify
one of the supported IRQ types:
IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
Reset value is IRQ_TYPE_LEVEL_LOW.
Optional properties:
- interrupts: empty for MIC interrupt controller, cascaded MIC
hardware interrupts for SIC1 and SIC2
Examples:
/* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */
mic: interrupt-controller@40008000 {
compatible = "nxp,lpc3220-mic";
reg = <0x40008000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
};
sic1: interrupt-controller@4000c000 {
compatible = "nxp,lpc3220-sic";
reg = <0x4000c000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&mic>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
<30 IRQ_TYPE_LEVEL_LOW>;
};
sic2: interrupt-controller@40010000 {
compatible = "nxp,lpc3220-sic";
reg = <0x40010000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&mic>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
<31 IRQ_TYPE_LEVEL_LOW>;
};
/* ADC */
adc@40048000 {
compatible = "nxp,lpc3220-adc";
reg = <0x40048000 0x1000>;
interrupt-parent = <&sic1>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
};

68
Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.yaml Normal file
View File

@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/nxp,lpc3220-mic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
maintainers:
- Vladimir Zapolskiy <vz@mleia.com>
properties:
compatible:
enum:
- nxp,lpc3220-mic
- nxp,lpc3220-sic
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
items:
- description: Regular interrupt request
- description: Fast interrupt request
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
allOf:
- if:
properties:
compatible:
contains:
const: nxp,lpc3220-sic
then:
required:
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
mic: interrupt-controller@40008000 {
compatible = "nxp,lpc3220-mic";
reg = <0x40008000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
};
interrupt-controller@4000c000 {
compatible = "nxp,lpc3220-sic";
reg = <0x4000c000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&mic>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
<30 IRQ_TYPE_LEVEL_LOW>;
};

6
Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
View File

@ -41,10 +41,6 @@ properties:
minItems: 1
maxItems: 5
assigned-clocks: true
assigned-clock-parents: true
iommus:
minItems: 1
maxItems: 32
@ -78,8 +74,6 @@ required:
- clocks
- clock-names
- iommus
- assigned-clocks
- assigned-clock-parents
allOf:
- if:

36
Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml
View File

@ -38,50 +38,16 @@ properties:
patternProperties:
"^.*@[0-3],[a-f0-9]+$":
type: object
$ref: mc-peripheral-props.yaml#
additionalProperties: true
description:
The actual device nodes should be added as subnodes to the SROMc node.
These subnodes, in addition to regular device specification, should
contain the following properties, describing configuration
of the relevant SROM bank.
properties:
reg:
description:
Bank number, base address (relative to start of the bank) and size
of the memory mapped for the device. Note that base address will be
typically 0 as this is the start of the bank.
maxItems: 1
reg-io-width:
enum: [1, 2]
description:
Data width in bytes (1 or 2). If omitted, default of 1 is used.
samsung,srom-page-mode:
description:
If page mode is set, 4 data page mode will be configured,
else normal (1 data) page mode will be set.
type: boolean
samsung,srom-timing:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 6
maxItems: 6
description: |
Array of 6 integers, specifying bank timings in the following order:
Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
Each value is specified in cycles and has the following meaning
and valid range:
Tacp: Page mode access cycle at Page mode (0 - 15)
Tcah: Address holding time after CSn (0 - 15)
Tcoh: Chip selection hold on OEn (0 - 15)
Tacc: Access cycle (0 - 31, the actual time is N + 1)
Tcos: Chip selection set-up before OEn (0 - 15)
Tacs: Address set-up before CSn (0 - 15)
required:
- reg
- samsung,srom-timing
required:

2
Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml
View File

@ -36,6 +36,8 @@ allOf:
- $ref: st,stm32-fmc2-ebi-props.yaml#
- $ref: ingenic,nemc-peripherals.yaml#
- $ref: intel,ixp4xx-expansion-peripheral-props.yaml#
- $ref: qcom,ebi2-peripheral-props.yaml#
- $ref: samsung,exynos4210-srom-peripheral-props.yaml#
- $ref: ti,gpmc-child.yaml#
- $ref: fsl/fsl,imx-weim-peripherals.yaml

91
Documentation/devicetree/bindings/memory-controllers/qcom,ebi2-peripheral-props.yaml Normal file
View File

@ -0,0 +1,91 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/qcom,ebi2-peripheral-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Peripheral Properties for Qualcomm External Bus Interface 2 (EBI2)
maintainers:
- Bjorn Andersson <andersson@kernel.org>
properties:
# SLOW chip selects
qcom,xmem-recovery-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The time the memory continues to drive the data bus after OE
is de-asserted, in order to avoid contention on the data bus.
They are inserted when reading one CS and switching to another
CS or read followed by write on the same CS. Minimum value is
actually 1, so a value of 0 will still yield 1 recovery cycle.
minimum: 0
maximum: 15
qcom,xmem-write-hold-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The extra cycles inserted after every write minimum 1. The
data out is driven from the time WE is asserted until CS is
asserted. With a hold of 1 (value = 0), the CS stays active
for 1 extra cycle, etc.
minimum: 0
maximum: 15
qcom,xmem-write-delta-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The initial latency for write cycles inserted for the first
write to a page or burst memory.
minimum: 0
maximum: 255
qcom,xmem-read-delta-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The initial latency for read cycles inserted for the first
read to a page or burst memory.
minimum: 0
maximum: 255
qcom,xmem-write-wait-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of wait cycles for every write access.
minimum: 0
maximum: 15
qcom,xmem-read-wait-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of wait cycles for every read access.
minimum: 0
maximum: 15
# FAST chip selects
qcom,xmem-address-hold-enable:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
Holds the address for an extra cycle to meet hold time
requirements with ADV assertion, when set to 1.
enum: [ 0, 1 ]
qcom,xmem-adv-to-oe-recovery-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of cycles elapsed before an OE assertion, with
respect to the cycle where ADV (address valid) is asserted.
minimum: 0
maximum: 3
qcom,xmem-read-hold-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The length in cycles of the first segment of a read transfer.
For a single read transfer this will be the time from CS
assertion to OE assertion.
minimum: 0
maximum: 15
additionalProperties: true

87
Documentation/devicetree/bindings/bus/qcom,ebi2.yaml → Documentation/devicetree/bindings/memory-controllers/qcom,ebi2.yaml
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/qcom,ebi2.yaml#
$id: http://devicetree.org/schemas/memory-controllers/qcom,ebi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm External Bus Interface 2 (EBI2)
@ -104,91 +104,8 @@ required:
patternProperties:
"^.*@[0-5],[0-9a-f]+$":
type: object
$ref: mc-peripheral-props.yaml#
additionalProperties: true
properties:
reg:
maxItems: 1
# SLOW chip selects
qcom,xmem-recovery-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The time the memory continues to drive the data bus after OE
is de-asserted, in order to avoid contention on the data bus.
They are inserted when reading one CS and switching to another
CS or read followed by write on the same CS. Minimum value is
actually 1, so a value of 0 will still yield 1 recovery cycle.
minimum: 0
maximum: 15
qcom,xmem-write-hold-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The extra cycles inserted after every write minimum 1. The
data out is driven from the time WE is asserted until CS is
asserted. With a hold of 1 (value = 0), the CS stays active
for 1 extra cycle, etc.
minimum: 0
maximum: 15
qcom,xmem-write-delta-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The initial latency for write cycles inserted for the first
write to a page or burst memory.
minimum: 0
maximum: 255
qcom,xmem-read-delta-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The initial latency for read cycles inserted for the first
read to a page or burst memory.
minimum: 0
maximum: 255
qcom,xmem-write-wait-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of wait cycles for every write access.
minimum: 0
maximum: 15
qcom,xmem-read-wait-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of wait cycles for every read access.
minimum: 0
maximum: 15
# FAST chip selects
qcom,xmem-address-hold-enable:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
Holds the address for an extra cycle to meet hold time
requirements with ADV assertion, when set to 1.
enum: [ 0, 1 ]
qcom,xmem-adv-to-oe-recovery-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of cycles elapsed before an OE assertion, with
respect to the cycle where ADV (address valid) is asserted.
minimum: 0
maximum: 3
qcom,xmem-read-hold-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The length in cycles of the first segment of a read transfer.
For a single read transfer this will be the time from CS
assertion to OE assertion.
minimum: 0
maximum: 15
required:
- reg
additionalProperties: false

35
Documentation/devicetree/bindings/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml Normal file
View File

@ -0,0 +1,35 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Peripheral Properties for Samsung Exynos SoC SROM Controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
samsung,srom-page-mode:
description:
If page mode is set, 4 data page mode will be configured,
else normal (1 data) page mode will be set.
type: boolean
samsung,srom-timing:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 6
maxItems: 6
description: |
Array of 6 integers, specifying bank timings in the following order:
Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
Each value is specified in cycles and has the following meaning
and valid range:
Tacp: Page mode access cycle at Page mode (0 - 15)
Tcah: Address holding time after CSn (0 - 15)
Tcoh: Chip selection hold on OEn (0 - 15)
Tacc: Access cycle (0 - 31, the actual time is N + 1)
Tcos: Chip selection set-up before OEn (0 - 15)
Tacs: Address set-up before CSn (0 - 15)
additionalProperties: true

6
Documentation/devicetree/bindings/net/smsc,lan9115.yaml
View File

@ -11,6 +11,7 @@ maintainers:
allOf:
- $ref: ethernet-controller.yaml#
- $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
properties:
compatible:
@ -89,10 +90,7 @@ required:
- reg
- interrupts
# There are lots of bus-specific properties ("qcom,*", "samsung,*", "fsl,*",
# "gpmc,*", ...) to be found, that actually depend on the compatible value of
# the parent node.
additionalProperties: true
unevaluatedProperties: false
examples:
- |

20
Documentation/devicetree/bindings/pps/pps-gpio.yaml
View File

@ -36,14 +36,14 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/gpio.h>
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
assert-falling-edge;
echo-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
echo-active-ms = <100>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
assert-falling-edge;
echo-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
echo-active-ms = <100>;
};

5
Documentation/devicetree/bindings/soc/imx/fsl,aips-bus.yaml
View File

@ -22,6 +22,9 @@ select:
required:
- compatible
allOf:
- $ref: /schemas/simple-bus.yaml#
properties:
compatible:
items:
@ -35,7 +38,7 @@ required:
- compatible
- reg
additionalProperties: true
unevaluatedProperties: false
examples:
- |

19
Documentation/devicetree/bindings/submitting-patches.rst
View File

@ -54,11 +54,22 @@ I. For patch submitters
followed as of commit bff5da4335256513497cc8c79f9a9d1665e09864
("checkpatch: add DT compatible string documentation checks"). ]
7) If a documented compatible string is not yet matched by the
7) DTS is treated in general as driver-independent hardware description, thus
any DTS patches, regardless whether using existing or new bindings, should
be placed at the end of patchset to indicate no dependency of drivers on
the DTS. DTS will be anyway applied through separate tree or branch, so
different order would indicate the serie is non-bisectable.
If a driver subsystem maintainer prefers to apply entire set, instead of
their relevant portion of patchset, please split the DTS patches into
separate patchset with a reference in changelog or cover letter to the
bindings submission on the mailing list.
8) If a documented compatible string is not yet matched by the
driver, the documentation should also include a compatible
string that is matched by the driver.
8) Bindings are actively used by multiple projects other than the Linux
9) Bindings are actively used by multiple projects other than the Linux
Kernel, extra care and consideration may need to be taken when making changes
to existing bindings.
@ -79,6 +90,10 @@ II. For kernel maintainers
3) For a series going though multiple trees, the binding patch should be
kept with the driver using the binding.
4) The DTS files should however never be applied via driver subsystem tree,
but always via platform SoC trees on dedicated branches (see also
Documentation/process/maintainer-soc.rst).
III. Notes
==========

9
Documentation/devicetree/bindings/trivial-devices.yaml
View File

@ -185,6 +185,12 @@ properties:
- maxim,max5484
# PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion
- maxim,max6621
# InTune Automatically Compensated Digital PoL Controller with Driver and PMBus Telemetry
- maxim,max15301
# 6A InTune Automatically Compensated Converter with PMBus Telemetry
- maxim,max15303
# Multiphase Master with PMBus Interface and Internal Buck Converter
- maxim,max20751
# mCube 3-axis 8-bit digital accelerometer
- mcube,mc3230
# Measurement Specialities I2C temperature and humidity sensor
@ -382,6 +388,8 @@ properties:
- ti,tps53676
# TI Dual channel DCAP+ multiphase controller TPS53679
- ti,tps53679
# TI Dual channel DCAP+ multiphase controller TPS53681
- ti,tps53681
# TI Dual channel DCAP+ multiphase controller TPS53688
- ti,tps53688
# TI DC-DC converters on PMBus
@ -389,6 +397,7 @@ properties:
- ti,tps544b25
- ti,tps544c20
- ti,tps544c25
- ti,tps546b24
- ti,tps546d24
# I2C Touch-Screen Controller
- ti,tsc2003

26
Documentation/devicetree/bindings/xilinx.txt
View File

@ -102,15 +102,6 @@
Default is <d#1024 d#480>.
- rotate-display (empty) : rotate display 180 degrees.
ii) Xilinx SystemACE
The Xilinx SystemACE device is used to program FPGAs from an FPGA
bitstream stored on a CF card. It can also be used as a generic CF
interface device.
Optional properties:
- 8-bit (empty) : Set this property for SystemACE in 8 bit mode
iii) Xilinx EMAC and Xilinx TEMAC
Xilinx Ethernet devices. In addition to general xilinx properties
@ -118,13 +109,6 @@
property, and may include other common network device properties
like local-mac-address.
iv) Xilinx Uartlite
Xilinx uartlite devices are simple fixed speed serial ports.
Required properties:
- current-speed : Baud rate of uartlite
v) Xilinx hwicap
Xilinx hwicap devices provide access to the configuration logic
@ -141,16 +125,6 @@
- compatible : should contain "xlnx,xps-hwicap-1.00.a" or
"xlnx,opb-hwicap-1.00.b".
vi) Xilinx Uart 16550
Xilinx UART 16550 devices are very similar to the NS16550 but with
different register spacing and an offset from the base address.
Required properties:
- clock-frequency : Frequency of the clock input
- reg-offset : A value of 3 is required
- reg-shift : A value of 2 is required
vii) Xilinx USB Host controller
The Xilinx USB host controller is EHCI compatible but with a different

5
Documentation/process/maintainer-soc-clean-dts.rst
View File

@ -17,8 +17,9 @@ Strict DTS DT Schema and dtc Compliance
No changes to the SoC platform Devicetree sources (DTS files) should introduce
new ``make dtbs_check W=1`` warnings. Warnings in a new board DTS, which are
results of issues in an included DTSI file, are considered existing, not new
warnings. The platform maintainers have automation in place which should point
out any new warnings.
warnings. For series split between different trees (DT bindings go via driver
subsystem tree), warnings on linux-next are decisive. The platform maintainers
have automation in place which should point out any new warnings.
If a commit introducing new warnings gets accepted somehow, the resulting
issues shall be fixed in reasonable time (e.g. within one release) or the

5
MAINTAINERS
View File

@ -3148,6 +3148,11 @@ M: Dinh Nguyen <dinguyen@kernel.org>
S: Maintained
F: drivers/clk/socfpga/
ARM/SOCFPGA EDAC BINDINGS
M: Matthew Gerlach <matthew.gerlach@altera.com>
S: Maintained
F: Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml
ARM/SOCFPGA EDAC SUPPORT
M: Dinh Nguyen <dinguyen@kernel.org>
S: Maintained

13
drivers/of/address.c
View File

@ -1031,20 +1031,15 @@ EXPORT_SYMBOL_GPL(of_dma_is_coherent);
*
* Returns true if the "nonposted-mmio" property was found for
* the device's bus.
*
* This is currently only enabled on builds that support Apple ARM devices, as
* an optimization.
*/
static bool of_mmio_is_nonposted(const struct device_node *np)
{
if (!IS_ENABLED(CONFIG_ARCH_APPLE))
return false;
struct device_node *parent __free(device_node) = of_get_parent(np);
if (!parent)
return false;
return of_property_read_bool(parent, "nonposted-mmio");
if (of_property_read_bool(np, "nonposted-mmio"))
return true;
return parent && of_property_read_bool(parent, "nonposted-mmio");
}
static int __of_address_to_resource(struct device_node *dev, int index, int bar_no,

6
drivers/of/base.c
View File

@ -1678,7 +1678,7 @@ int __of_add_property(struct device_node *np, struct property *prop)
prop->next = NULL;
next = &np->properties;
while (*next) {
if (strcmp(prop->name, (*next)->name) == 0) {
if (of_prop_cmp(prop->name, (*next)->name) == 0) {
/* duplicate ! don't insert it */
rc = -EEXIST;
goto out_unlock;
@ -1882,9 +1882,7 @@ void of_alias_scan(void * (*dt_alloc)(u64 size, u64 align))
int id, len;
/* Skip those we do not want to proceed */
if (!strcmp(pp->name, "name") ||
!strcmp(pp->name, "phandle") ||
!strcmp(pp->name, "linux,phandle"))
if (is_pseudo_property(pp->name))
continue;
np = of_find_node_by_path(pp->value);

82
drivers/of/irq.c
View File

@ -16,6 +16,7 @@
#define pr_fmt(fmt) "OF: " fmt
#include <linux/cleanup.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/list.h>
@ -38,11 +39,15 @@
unsigned int irq_of_parse_and_map(struct device_node *dev, int index)
{
struct of_phandle_args oirq;
unsigned int ret;
if (of_irq_parse_one(dev, index, &oirq))
return 0;
return irq_create_of_mapping(&oirq);
ret = irq_create_of_mapping(&oirq);
of_node_put(oirq.np);
return ret;
}
EXPORT_SYMBOL_GPL(irq_of_parse_and_map);
@ -50,8 +55,8 @@ EXPORT_SYMBOL_GPL(irq_of_parse_and_map);
* of_irq_find_parent - Given a device node, find its interrupt parent node
* @child: pointer to device node
*
* Return: A pointer to the interrupt parent node, or NULL if the interrupt
* parent could not be determined.
* Return: A pointer to the interrupt parent node with refcount increased
* or NULL if the interrupt parent could not be determined.
*/
struct device_node *of_irq_find_parent(struct device_node *child)
{
@ -165,6 +170,8 @@ const __be32 *of_irq_parse_imap_parent(const __be32 *imap, int len, struct of_ph
* the specifier for each map, and then returns the translated map.
*
* Return: 0 on success and a negative number on error
*
* Note: refcount of node @out_irq->np is increased by 1 on success.
*/
int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *out_irq)
{
@ -310,6 +317,12 @@ int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *out_irq)
addrsize = (imap - match_array) - intsize;
if (ipar == newpar) {
/*
* We got @ipar's refcount, but the refcount was
* gotten again by of_irq_parse_imap_parent() via its
* alias @newpar.
*/
of_node_put(ipar);
pr_debug("%pOF interrupt-map entry to self\n", ipar);
return 0;
}
@ -339,10 +352,12 @@ EXPORT_SYMBOL_GPL(of_irq_parse_raw);
* This function resolves an interrupt for a node by walking the interrupt tree,
* finding which interrupt controller node it is attached to, and returning the
* interrupt specifier that can be used to retrieve a Linux IRQ number.
*
* Note: refcount of node @out_irq->np is increased by 1 on success.
*/
int of_irq_parse_one(struct device_node *device, int index, struct of_phandle_args *out_irq)
{
struct device_node *p;
struct device_node __free(device_node) *p = NULL;
const __be32 *addr;
u32 intsize;
int i, res, addr_len;
@ -367,41 +382,33 @@ int of_irq_parse_one(struct device_node *device, int index, struct of_phandle_ar
/* Try the new-style interrupts-extended first */
res = of_parse_phandle_with_args(device, "interrupts-extended",
"#interrupt-cells", index, out_irq);
if (!res)
return of_irq_parse_raw(addr_buf, out_irq);
if (!res) {
p = out_irq->np;
} else {
/* Look for the interrupt parent. */
p = of_irq_find_parent(device);
/* Get size of interrupt specifier */
if (!p || of_property_read_u32(p, "#interrupt-cells", &intsize))
return -EINVAL;
/* Look for the interrupt parent. */
p = of_irq_find_parent(device);
if (p == NULL)
return -EINVAL;
pr_debug(" parent=%pOF, intsize=%d\n", p, intsize);
/* Get size of interrupt specifier */
if (of_property_read_u32(p, "#interrupt-cells", &intsize)) {
res = -EINVAL;
goto out;
/* Copy intspec into irq structure */
out_irq->np = p;
out_irq->args_count = intsize;
for (i = 0; i < intsize; i++) {
res = of_property_read_u32_index(device, "interrupts",
(index * intsize) + i,
out_irq->args + i);
if (res)
return res;
}
pr_debug(" intspec=%d\n", *out_irq->args);
}
pr_debug(" parent=%pOF, intsize=%d\n", p, intsize);
/* Copy intspec into irq structure */
out_irq->np = p;
out_irq->args_count = intsize;
for (i = 0; i < intsize; i++) {
res = of_property_read_u32_index(device, "interrupts",
(index * intsize) + i,
out_irq->args + i);
if (res)
goto out;
}
pr_debug(" intspec=%d\n", *out_irq->args);
/* Check if there are any interrupt-map translations to process */
res = of_irq_parse_raw(addr_buf, out_irq);
out:
of_node_put(p);
return res;
return of_irq_parse_raw(addr_buf, out_irq);
}
EXPORT_SYMBOL_GPL(of_irq_parse_one);
@ -505,8 +512,10 @@ int of_irq_count(struct device_node *dev)
struct of_phandle_args irq;
int nr = 0;
while (of_irq_parse_one(dev, nr, &irq) == 0)
while (of_irq_parse_one(dev, nr, &irq) == 0) {
of_node_put(irq.np);
nr++;
}
return nr;
}
@ -623,6 +632,8 @@ void __init of_irq_init(const struct of_device_id *matches)
__func__, desc->dev, desc->dev,
desc->interrupt_parent);
of_node_clear_flag(desc->dev, OF_POPULATED);
of_node_put(desc->interrupt_parent);
of_node_put(desc->dev);
kfree(desc);
continue;
}
@ -653,6 +664,7 @@ void __init of_irq_init(const struct of_device_id *matches)
err:
list_for_each_entry_safe(desc, temp_desc, &intc_desc_list, list) {
list_del(&desc->list);
of_node_put(desc->interrupt_parent);
of_node_put(desc->dev);
kfree(desc);
}

7
drivers/of/of_private.h
View File

@ -208,6 +208,13 @@ static void __maybe_unused of_dump_addr(const char *s, const __be32 *addr, int n
static void __maybe_unused of_dump_addr(const char *s, const __be32 *addr, int na) { }
#endif
static inline bool is_pseudo_property(const char *prop_name)
{
return !of_prop_cmp(prop_name, "name") ||
!of_prop_cmp(prop_name, "phandle") ||
!of_prop_cmp(prop_name, "linux,phandle");
}
#if IS_ENABLED(CONFIG_KUNIT)
int __of_address_resource_bounds(struct resource *r, u64 start, u64 size);
#endif

10
drivers/of/overlay.c
View File

@ -84,6 +84,12 @@ static int devicetree_state_flags;
#define DTSF_APPLY_FAIL 0x01
#define DTSF_REVERT_FAIL 0x02
static int of_prop_val_eq(const struct property *p1, const struct property *p2)
{
return p1->length == p2->length &&
!memcmp(p1->value, p2->value, (size_t)p1->length);
}
/*
* If a changeset apply or revert encounters an error, an attempt will
* be made to undo partial changes, but may fail. If the undo fails
@ -304,9 +310,7 @@ static int add_changeset_property(struct overlay_changeset *ovcs,
int ret = 0;
if (target->in_livetree)
if (!of_prop_cmp(overlay_prop->name, "name") ||
!of_prop_cmp(overlay_prop->name, "phandle") ||
!of_prop_cmp(overlay_prop->name, "linux,phandle"))
if (is_pseudo_property(overlay_prop->name))
return 0;
if (target->in_livetree)

8
drivers/of/platform.c
View File

@ -334,7 +334,7 @@ static int of_platform_bus_create(struct device_node *bus,
int rc = 0;
/* Make sure it has a compatible property */
if (strict && (!of_get_property(bus, "compatible", NULL))) {
if (strict && (!of_property_present(bus, "compatible"))) {
pr_debug("%s() - skipping %pOF, no compatible prop\n",
__func__, bus);
return 0;
@ -536,8 +536,8 @@ static int __init of_platform_default_populate_init(void)
* ignore errors for the rest.
*/
for_each_node_by_type(node, "display") {
if (!of_get_property(node, "linux,opened", NULL) ||
!of_get_property(node, "linux,boot-display", NULL))
if (!of_property_read_bool(node, "linux,opened") ||
!of_property_read_bool(node, "linux,boot-display"))
continue;
dev = of_platform_device_create(node, "of-display", NULL);
of_node_put(node);
@ -551,7 +551,7 @@ static int __init of_platform_default_populate_init(void)
char buf[14];
const char *of_display_format = "of-display.%d";
if (!of_get_property(node, "linux,opened", NULL) || node == boot_display)
if (!of_property_read_bool(node, "linux,opened") || node == boot_display)
continue;
ret = snprintf(buf, sizeof(buf), of_display_format, display_number++);
if (ret < sizeof(buf))

41
drivers/of/resolver.c
View File

@ -161,9 +161,7 @@ static int adjust_local_phandle_references(const struct device_node *local_fixup
for_each_property_of_node(local_fixups, prop_fix) {
/* skip properties added automatically */
if (!of_prop_cmp(prop_fix->name, "name") ||
!of_prop_cmp(prop_fix->name, "phandle") ||
!of_prop_cmp(prop_fix->name, "linux,phandle"))
if (is_pseudo_property(prop_fix->name))
continue;
if ((prop_fix->length % 4) != 0 || prop_fix->length == 0)
@ -249,25 +247,22 @@ static int adjust_local_phandle_references(const struct device_node *local_fixup
*/
int of_resolve_phandles(struct device_node *overlay)
{
struct device_node *child, *local_fixups, *refnode;
struct device_node *tree_symbols, *overlay_fixups;
struct device_node *child, *refnode;
struct device_node *overlay_fixups;
struct device_node __free(device_node) *local_fixups = NULL;
struct property *prop;
const char *refpath;
phandle phandle, phandle_delta;
int err;
tree_symbols = NULL;
if (!overlay) {
pr_err("null overlay\n");
err = -EINVAL;
goto out;
return -EINVAL;
}
if (!of_node_check_flag(overlay, OF_DETACHED)) {
pr_err("overlay not detached\n");
err = -EINVAL;
goto out;
return -EINVAL;
}
phandle_delta = live_tree_max_phandle() + 1;
@ -279,7 +274,7 @@ int of_resolve_phandles(struct device_node *overlay)
err = adjust_local_phandle_references(local_fixups, overlay, phandle_delta);
if (err)
goto out;
return err;
overlay_fixups = NULL;
@ -288,16 +283,13 @@ int of_resolve_phandles(struct device_node *overlay)
overlay_fixups = child;
}
if (!overlay_fixups) {
err = 0;
goto out;
}
if (!overlay_fixups)
return 0;
tree_symbols = of_find_node_by_path("/__symbols__");
struct device_node __free(device_node) *tree_symbols = of_find_node_by_path("/__symbols__");
if (!tree_symbols) {
pr_err("no symbols in root of device tree.\n");
err = -EINVAL;
goto out;
return -EINVAL;
}
for_each_property_of_node(overlay_fixups, prop) {
@ -311,14 +303,12 @@ int of_resolve_phandles(struct device_node *overlay)
if (err) {
pr_err("node label '%s' not found in live devicetree symbols table\n",
prop->name);
goto out;
return err;
}
refnode = of_find_node_by_path(refpath);
if (!refnode) {
err = -ENOENT;
goto out;
}
if (!refnode)
return -ENOENT;
phandle = refnode->phandle;
of_node_put(refnode);
@ -328,11 +318,8 @@ int of_resolve_phandles(struct device_node *overlay)
break;
}
out:
if (err)
pr_err("overlay phandle fixup failed: %d\n", err);
of_node_put(tree_symbols);
return err;
}
EXPORT_SYMBOL_GPL(of_resolve_phandles);

13
drivers/of/unittest-data/tests-interrupts.dtsi
View File

@ -50,6 +50,13 @@
interrupt-map = <0x5000 1 2 &test_intc0 15>;
};
test_intc_intmap0: intc-intmap0 {
#interrupt-cells = <1>;
#address-cells = <1>;
interrupt-controller;
interrupt-map = <0x6000 1 &test_intc_intmap0 0x7000 2>;
};
interrupts0 {
interrupt-parent = <&test_intc0>;
interrupts = <1>, <2>, <3>, <4>;
@ -60,6 +67,12 @@
interrupts = <1>, <2>, <3>, <4>;
};
interrupts2 {
reg = <0x6000 0x100>;
interrupt-parent = <&test_intc_intmap0>;
interrupts = <1>;
};
interrupts-extended0 {
reg = <0x5000 0x100>;
/*

67
drivers/of/unittest.c
View File

@ -1654,6 +1654,72 @@ static void __init of_unittest_parse_interrupts_extended(void)
of_node_put(np);
}
#if IS_ENABLED(CONFIG_OF_DYNAMIC)
static void __init of_unittest_irq_refcount(void)
{
struct of_phandle_args args;
struct device_node *intc0, *int_ext0;
struct device_node *int2, *intc_intmap0;
unsigned int ref_c0, ref_c1, ref_c2;
int rc;
bool passed;
if (of_irq_workarounds & OF_IMAP_OLDWORLD_MAC)
return;
intc0 = of_find_node_by_path("/testcase-data/interrupts/intc0");
int_ext0 = of_find_node_by_path("/testcase-data/interrupts/interrupts-extended0");
intc_intmap0 = of_find_node_by_path("/testcase-data/interrupts/intc-intmap0");
int2 = of_find_node_by_path("/testcase-data/interrupts/interrupts2");
if (!intc0 || !int_ext0 || !intc_intmap0 || !int2) {
pr_err("missing testcase data\n");
goto out;
}
/* Test refcount for API of_irq_parse_one() */
passed = true;
ref_c0 = OF_KREF_READ(intc0);
ref_c1 = ref_c0 + 1;
memset(&args, 0, sizeof(args));
rc = of_irq_parse_one(int_ext0, 0, &args);
ref_c2 = OF_KREF_READ(intc0);
of_node_put(args.np);
passed &= !rc;
passed &= (args.np == intc0);
passed &= (args.args_count == 1);
passed &= (args.args[0] == 1);
passed &= (ref_c1 == ref_c2);
unittest(passed, "IRQ refcount case #1 failed, original(%u) expected(%u) got(%u)\n",
ref_c0, ref_c1, ref_c2);
/* Test refcount for API of_irq_parse_raw() */
passed = true;
ref_c0 = OF_KREF_READ(intc_intmap0);
ref_c1 = ref_c0 + 1;
memset(&args, 0, sizeof(args));
rc = of_irq_parse_one(int2, 0, &args);
ref_c2 = OF_KREF_READ(intc_intmap0);
of_node_put(args.np);
passed &= !rc;
passed &= (args.np == intc_intmap0);
passed &= (args.args_count == 1);
passed &= (args.args[0] == 2);
passed &= (ref_c1 == ref_c2);
unittest(passed, "IRQ refcount case #2 failed, original(%u) expected(%u) got(%u)\n",
ref_c0, ref_c1, ref_c2);
out:
of_node_put(int2);
of_node_put(intc_intmap0);
of_node_put(int_ext0);
of_node_put(intc0);
}
#else
static inline void __init of_unittest_irq_refcount(void) { }
#endif
static const struct of_device_id match_node_table[] = {
{ .data = "A", .name = "name0", }, /* Name alone is lowest priority */
{ .data = "B", .type = "type1", }, /* followed by type alone */
@ -4324,6 +4390,7 @@ static int __init of_unittest(void)
of_unittest_changeset_prop();
of_unittest_parse_interrupts();
of_unittest_parse_interrupts_extended();
of_unittest_irq_refcount();
of_unittest_dma_get_max_cpu_address();
of_unittest_parse_dma_ranges();
of_unittest_pci_dma_ranges();

2
include/linux/fwnode.h
View File

@ -91,7 +91,7 @@ struct fwnode_endpoint {
#define SWNODE_GRAPH_PORT_NAME_FMT "port@%u"
#define SWNODE_GRAPH_ENDPOINT_NAME_FMT "endpoint@%u"
#define NR_FWNODE_REFERENCE_ARGS 8
#define NR_FWNODE_REFERENCE_ARGS 16
/**
* struct fwnode_reference_args - Fwnode reference with additional arguments

8
include/linux/of.h
View File

@ -67,7 +67,7 @@ struct device_node {
#endif
};
#define MAX_PHANDLE_ARGS 16
#define MAX_PHANDLE_ARGS NR_FWNODE_REFERENCE_ARGS
struct of_phandle_args {
struct device_node *np;
int args_count;
@ -926,12 +926,6 @@ static inline const void *of_device_get_match_data(const struct device *dev)
#define of_node_cmp(s1, s2) strcasecmp((s1), (s2))
#endif
static inline int of_prop_val_eq(const struct property *p1, const struct property *p2)
{
return p1->length == p2->length &&
!memcmp(p1->value, p2->value, (size_t)p1->length);
}
#define for_each_property_of_node(dn, pp) \
for (pp = dn->properties; pp != NULL; pp = pp->next)

6
scripts/make_fit.py
View File

@ -279,7 +279,11 @@ def build_fit(args):
if os.path.splitext(fname)[1] != '.dtb':
continue
(model, compat, files) = process_dtb(fname, args)
try:
(model, compat, files) = process_dtb(fname, args)
except Exception as e:
sys.stderr.write(f"Error processing {fname}:\n")
raise e
for fn in files:
if fn not in fdts: