dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document lanes mapping when not using in USB-C complex

The QMP USB3/DP Combo PHY hosts an USB3 phy and a DP PHY on top
of a combo glue to route either lanes to the 4 shared physical lanes.

The routing of the lanes can be:
- 2 DP + 2 USB3
- 4 DP
- 2 USB3

The layout of the lanes was designed to be mapped and swapped
related to the USB-C Power Delivery negociation, so it supports
a finite set of mappings inherited by the USB-C Altmode layouts.

Nevertheless those QMP Comby PHY can be used to drive a DisplayPort
connector, DP->HDMI bridge, USB3 A Connector, etc... without
an USB-C connector and no PD events.

Document the data-lanes on numbered port@0 out endpoints,
allowing us to document the lanes mapping to DisplayPort
and/or USB3 connectors/peripherals.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20251119-topic-x1e80100-hdmi-v7-1-2bee0e66cc1b@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
pull/1354/merge
Neil Armstrong 2025-11-19 09:45:40 +01:00 committed by Vinod Koul
parent be866e6896
commit 3faa2d0e79
1 changed files with 68 additions and 1 deletions

View File

@ -78,10 +78,77 @@ properties:
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
$ref: /schemas/graph.yaml#/$defs/port-base
description: Output endpoint of the PHY
unevaluatedProperties: false
properties:
endpoint:
$ref: /schemas/graph.yaml#/$defs/endpoint-base
unevaluatedProperties: false
endpoint@0:
$ref: /schemas/graph.yaml#/$defs/endpoint-base
description: Display Port Output lanes of the PHY when used with static mapping,
The entry index is the DP lanes index, and the number is the PHY
signal in the order RX0, TX0, TX1, RX1.
unevaluatedProperties: false
properties:
# Static lane mappings are mutually exclusive with typec-mux/orientation-mux
data-lanes:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 2
maxItems: 4
oneOf:
- items: # DisplayPort 1 lane, normal orientation
- const: 3
- items: # DisplayPort 1 lane, flipped orientation
- const: 0
- items: # DisplayPort 2 lanes, normal orientation
- const: 3
- const: 2
- items: # DisplayPort 2 lanes, flipped orientation
- const: 0
- const: 1
- items: # DisplayPort 4 lanes, normal orientation
- const: 3
- const: 2
- const: 1
- const: 0
- items: # DisplayPort 4 lanes, flipped orientation
- const: 0
- const: 1
- const: 2
- const: 3
required:
- data-lanes
endpoint@1:
$ref: /schemas/graph.yaml#/$defs/endpoint-base
description: USB Output lanes of the PHY when used with static mapping.
The entry index is the USB3 lane in the order TX then RX, and the
number is the PHY signal in the order RX0, TX0, TX1, RX1.
unevaluatedProperties: false
properties:
# Static lane mappings are mutually exclusive with typec-mux/orientation-mux
data-lanes:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 2
oneOf:
- items: # USB3, normal orientation
- const: 1
- const: 0
- items: # USB3, flipped orientation
- const: 2
- const: 3
required:
- data-lanes
port@1:
$ref: /schemas/graph.yaml#/properties/port