drm/amdkfd: Trap handler support for expert scheduling mode
The trap may be entered with dependency checking disabled. Wait for dependency counters and save/restore scheduling mode. v2: Use ttmp1 instead of ttmp11. ttmp11 is not zero-initialized. While the trap handler does zero this field before use, a user-mode second-level trap handler could not rely on this being zero when using an older kernel mode driver. v3: Use ttmp11 primarily but copy to ttmp1 before jumping to the second level trap handler. ttmp1 is inspectable by a debugger. Unexpected bits in the unused space may regress existing software. Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>master
Jay Cornwall
Alex Deucher
parent
97b2e10e94
commit
4238888794
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@ -3644,14 +3644,18 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = {
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};
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static const uint32_t cwsr_trap_gfx12_hex[] = {
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0xbfa00001, 0xbfa002a2,
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0xb0804009, 0xb8f8f804,
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0xbfa00001, 0xbfa002b2,
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0xb0804009, 0xb8eef81a,
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0xbf880000, 0xb980081a,
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0x00000000, 0xb8f8f804,
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0x9177ff77, 0x0c000000,
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0x846e9a6e, 0x8c776e77,
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0x9178ff78, 0x00008c00,
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0xb8fbf811, 0x8b6eff78,
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0x00004000, 0xbfa10008,
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0x8b6eff7b, 0x00000080,
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0xbfa20018, 0x8b6ea07b,
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0xbfa20042, 0xbf830010,
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0xbfa2004a, 0xbf830010,
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0xb8fbf811, 0xbfa0fffb,
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0x8b6eff7b, 0x00000bd0,
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0xbfa20010, 0xb8eef812,
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@ -3662,28 +3666,32 @@ static const uint32_t cwsr_trap_gfx12_hex[] = {
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0xf0000000, 0xbfa20005,
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0x8b6fff6f, 0x00000200,
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0xbfa20002, 0x8b6ea07b,
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0xbfa2002c, 0xbefa4d82,
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0xbfa20034, 0xbefa4d82,
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0xbf8a0000, 0x84fa887a,
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0xbf0d8f7b, 0xbfa10002,
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0x8c7bff7b, 0xffff0000,
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0xf4601bbd, 0xf8000010,
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0xbf8a0000, 0x846e976e,
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0x9177ff77, 0x00800000,
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0x8c776e77, 0xf4603bbd,
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0xf8000000, 0xbf8a0000,
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0xf4603ebd, 0xf8000008,
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0xbf8a0000, 0x8bee6e6e,
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0xbfa10001, 0xbe80486e,
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0x8b6eff6d, 0xf0000000,
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0xbfa20009, 0xb8eef811,
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0x8b6eff6e, 0x00000080,
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0xbfa20007, 0x8c78ff78,
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0x00004000, 0x80ec886c,
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0x82ed806d, 0xbfa00002,
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0x806c846c, 0x826d806d,
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0x8b6dff6d, 0x0000ffff,
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0x8bfe7e7e, 0x8bea6a6a,
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0x85788978, 0xb9783244,
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0x8b6eff77, 0x0c000000,
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0x916dff6d, 0x0c000000,
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0x8c6d6e6d, 0xf4601bbd,
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0xf8000010, 0xbf8a0000,
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0x846e976e, 0x9177ff77,
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0x00800000, 0x8c776e77,
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0xf4603bbd, 0xf8000000,
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0xbf8a0000, 0xf4603ebd,
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0xf8000008, 0xbf8a0000,
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0x8bee6e6e, 0xbfa10001,
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0xbe80486e, 0x8b6eff6d,
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0xf0000000, 0xbfa20009,
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0xb8eef811, 0x8b6eff6e,
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0x00000080, 0xbfa20007,
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0x8c78ff78, 0x00004000,
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0x80ec886c, 0x82ed806d,
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0xbfa00002, 0x806c846c,
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0x826d806d, 0x8b6dff6d,
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0x0000ffff, 0x8bfe7e7e,
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0x8bea6a6a, 0x85788978,
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0x936eff77, 0x0002001a,
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0xb96ef81a, 0xb9783244,
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0xbe804a6c, 0xb8faf802,
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0xbf0d987a, 0xbfa10001,
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0xbfb00000, 0x8b6dff6d,
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@ -3981,7 +3989,7 @@ static const uint32_t cwsr_trap_gfx12_hex[] = {
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0x008ce800, 0x00000000,
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0x807d817d, 0x8070ff70,
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0x00000080, 0xbf0a7b7d,
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0xbfa2fff7, 0xbfa0016e,
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0xbfa2fff7, 0xbfa00171,
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0xbef4007e, 0x8b75ff7f,
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0x0000ffff, 0x8c75ff75,
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0x00040000, 0xbef60080,
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@ -4163,12 +4171,14 @@ static const uint32_t cwsr_trap_gfx12_hex[] = {
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0xf8000074, 0xbf8a0000,
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0x8b6dff6d, 0x0000ffff,
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0x8bfe7e7e, 0x8bea6a6a,
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0xb97af804, 0xbe804ec2,
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0xbf94fffe, 0xbe804a6c,
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0x936eff77, 0x0002001a,
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0xb96ef81a, 0xb97af804,
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0xbe804ec2, 0xbf94fffe,
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0xbfb10000, 0xbf9f0000,
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0xbe804a6c, 0xbe804ec2,
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0xbf94fffe, 0xbfb10000,
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0xbf9f0000, 0xbf9f0000,
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0xbf9f0000, 0xbf9f0000,
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0xbf9f0000, 0x00000000,
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};
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static const uint32_t cwsr_trap_gfx9_5_0_hex[] = {
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@ -78,9 +78,16 @@ var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SHIFT = SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL
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var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SIZE = SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT - SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT
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var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SHIFT = SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_SHIFT
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var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SIZE = 32 - SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SHIFT
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var SQ_WAVE_SCHED_MODE_DEP_MODE_SHIFT = 0
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var SQ_WAVE_SCHED_MODE_DEP_MODE_SIZE = 2
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var BARRIER_STATE_SIGNAL_OFFSET = 16
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var BARRIER_STATE_VALID_OFFSET = 0
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var TTMP11_SCHED_MODE_SHIFT = 26
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var TTMP11_SCHED_MODE_SIZE = 2
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var TTMP11_SCHED_MODE_MASK = 0xC000000
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var TTMP11_DEBUG_TRAP_ENABLED_SHIFT = 23
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var TTMP11_DEBUG_TRAP_ENABLED_MASK = 0x800000
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@ -160,8 +167,19 @@ L_JUMP_TO_RESTORE:
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s_branch L_RESTORE
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L_SKIP_RESTORE:
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// Assume most relaxed scheduling mode is set. Save and revert to normal mode.
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s_getreg_b32 ttmp2, hwreg(HW_REG_WAVE_SCHED_MODE)
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s_wait_alu 0
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s_setreg_imm32_b32 hwreg(HW_REG_WAVE_SCHED_MODE, \
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SQ_WAVE_SCHED_MODE_DEP_MODE_SHIFT, SQ_WAVE_SCHED_MODE_DEP_MODE_SIZE), 0
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s_getreg_b32 s_save_state_priv, hwreg(HW_REG_WAVE_STATE_PRIV) //save STATUS since we will change SCC
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// Save SCHED_MODE[1:0] into ttmp11[27:26].
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s_andn2_b32 ttmp11, ttmp11, TTMP11_SCHED_MODE_MASK
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s_lshl_b32 ttmp2, ttmp2, TTMP11_SCHED_MODE_SHIFT
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s_or_b32 ttmp11, ttmp11, ttmp2
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// Clear SPI_PRIO: do not save with elevated priority.
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// Clear ECC_ERR: prevents SQC store and triggers FATAL_HALT if setreg'd.
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s_andn2_b32 s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_ALWAYS_CLEAR_MASK
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@ -238,6 +256,13 @@ L_FETCH_2ND_TRAP:
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s_cbranch_scc0 L_NO_SIGN_EXTEND_TMA
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s_or_b32 ttmp15, ttmp15, 0xFFFF0000
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L_NO_SIGN_EXTEND_TMA:
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#if ASIC_FAMILY == CHIP_GFX12
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// Move SCHED_MODE[1:0] from ttmp11 to unused bits in ttmp1[27:26] (return PC_HI).
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// The second-level trap will restore from ttmp1 for backwards compatibility.
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s_and_b32 ttmp2, ttmp11, TTMP11_SCHED_MODE_MASK
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s_andn2_b32 ttmp1, ttmp1, TTMP11_SCHED_MODE_MASK
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s_or_b32 ttmp1, ttmp1, ttmp2
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#endif
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s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 scope:SCOPE_SYS // debug trap enabled flag
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s_wait_idle
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@ -287,6 +312,10 @@ L_EXIT_TRAP:
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// STATE_PRIV.BARRIER_COMPLETE may have changed since we read it.
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// Only restore fields which the trap handler changes.
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s_lshr_b32 s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_SCC_SHIFT
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// Assume relaxed scheduling mode after this point.
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restore_sched_mode(ttmp2)
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s_setreg_b32 hwreg(HW_REG_WAVE_STATE_PRIV, SQ_WAVE_STATE_PRIV_SCC_SHIFT, \
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SQ_WAVE_STATE_PRIV_POISON_ERR_SHIFT - SQ_WAVE_STATE_PRIV_SCC_SHIFT + 1), s_save_state_priv
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@ -1043,6 +1072,9 @@ L_SKIP_BARRIER_RESTORE:
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s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32
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s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32
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// Assume relaxed scheduling mode after this point.
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restore_sched_mode(s_restore_tmp)
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s_setreg_b32 hwreg(HW_REG_WAVE_STATE_PRIV), s_restore_state_priv // SCC is included, which is changed by previous salu
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// Make barrier and LDS state visible to all waves in the group.
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@ -1134,3 +1166,8 @@ function valu_sgpr_hazard
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end
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#endif
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end
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function restore_sched_mode(s_tmp)
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s_bfe_u32 s_tmp, ttmp11, (TTMP11_SCHED_MODE_SHIFT | (TTMP11_SCHED_MODE_SIZE << 0x10))
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s_setreg_b32 hwreg(HW_REG_WAVE_SCHED_MODE), s_tmp
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end
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