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ARM: soc updates for 6.18 

The at91 power management code and the TI AM33 platform each get
 a few updates for robustness, the other changes are just minor
 cleanups.
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Merge tag 'soc-arm-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC updates from Arnd Bergmann:
 "The at91 power management code and the TI AM33 platform each get a few
  updates for robustness, the other changes are just minor cleanups"

* tag 'soc-arm-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  ARM: versatile: clock: convert from round_rate() to determine_rate()
  ARM: rockchip: remove REGULATOR conditional to PM
  ARM: at91: pm: Remove 2.5V regulator
  ARM: OMAP2+: clock: convert from round_rate() to determine_rate()
  ARM: OMAP1: clock: convert from round_rate() to determine_rate()
  ARM: mach-hpe: Rework support and directory structure
  arm: omap2: use string choices helper
  ARM: OMAP2+: pm33xx-core: ix device node reference leaks in amx3_idle_init
  ARM: OMAP2+: use IS_ERR_OR_NULL() helper
  ARM: AM33xx: Implement TI advisory 1.0.36 (EMU0/EMU1 pins state on reset)
  ARM: at91: pm: save and restore ACR during PLL disable/enable
  ARM: at91: pm: fix MCKx restore routine
  ARM: at91: pm: fix .uhp_udp_mask specification for current SoCs
  ARM: shmobile: rcar-gen2: Use SZ_256K definition
pull/1354/merge
Linus Torvalds 2025-10-01 17:41:15 -07:00
parent 38057e3236 65d2419f93
commit 42cbaeec98
21 changed files with 113 additions and 111 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
View File

@ -2737,7 +2737,6 @@ F: Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml
F: Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
F: Documentation/hwmon/gxp-fan-ctrl.rst
F: arch/arm/boot/dts/hpe/
F: arch/arm/mach-hpe/
F: drivers/clocksource/timer-gxp.c
F: drivers/hwmon/gxp-fan-ctrl.c
F: drivers/i2c/busses/i2c-gxp.c

2
arch/arm/Kconfig
View File

@ -393,8 +393,6 @@ source "arch/arm/mach-highbank/Kconfig"
source "arch/arm/mach-hisi/Kconfig"
source "arch/arm/mach-hpe/Kconfig"
source "arch/arm/mach-imx/Kconfig"
source "arch/arm/mach-ixp4xx/Kconfig"

25
arch/arm/Kconfig.platforms
View File

@ -87,6 +87,31 @@ config MACH_ASM9260
help
Support for Alphascale ASM9260 based platform.
menuconfig ARCH_HPE
bool "HPE SoC support"
depends on ARCH_MULTI_V7
help
This enables support for HPE ARM based BMC chips.
if ARCH_HPE
config ARCH_HPE_GXP
bool "HPE GXP SoC"
depends on ARCH_MULTI_V7
select ARM_VIC
select GENERIC_IRQ_CHIP
select CLKSRC_MMIO
help
HPE GXP is the name of the HPE Soc. This SoC is used to implement many
BMC features at HPE. It supports ARMv7 architecture based on the Cortex
A9 core. It is capable of using an AXI bus to which a memory controller
is attached. It has multiple SPI interfaces to connect boot flash and
BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It
has multiple i2c engines to drive connectivity with a host
infrastructure.
endif
menuconfig ARCH_MOXART
bool "MOXA ART SoC"
depends on ARCH_MULTI_V4

1
arch/arm/Makefile
View File

@ -189,7 +189,6 @@ machine-$(CONFIG_ARCH_FOOTBRIDGE) += footbridge
machine-$(CONFIG_ARCH_GEMINI) += gemini
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_HISI) += hisi
machine-$(CONFIG_ARCH_HPE) += hpe
machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx

2
arch/arm/mach-at91/pm.c
View File

@ -1364,7 +1364,7 @@ static const struct pmc_info pmc_infos[] __initconst = {
.version = AT91_PMC_V1,
},
{
.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
.uhp_udp_mask = AT91SAM926x_PMC_UHP,
.mckr = 0x28,
.version = AT91_PMC_V2,
},

41
arch/arm/mach-at91/pm_suspend.S
View File

@ -87,29 +87,6 @@ tmp3 .req r6
.endm
/**
* Set state for 2.5V low power regulator
* @ena: 0 - disable regulator
* 1 - enable regulator
*
* Side effects: overwrites r7, r8, r9, r10
*/
.macro at91_2_5V_reg_set_low_power ena
#ifdef CONFIG_SOC_SAMA7
ldr r7, .sfrbu
mov r8, #\ena
ldr r9, [r7, #AT91_SFRBU_25LDOCR]
orr r9, r9, #AT91_SFRBU_25LDOCR_LP
cmp r8, #1
beq lp_done_\ena
bic r9, r9, #AT91_SFRBU_25LDOCR_LP
lp_done_\ena:
ldr r10, =AT91_SFRBU_25LDOCR_LDOANAKEY
orr r9, r9, r10
str r9, [r7, #AT91_SFRBU_25LDOCR]
#endif
.endm
.macro at91_backup_set_lpm reg
#ifdef CONFIG_SOC_SAMA7
orr \reg, \reg, #0x200000
@ -689,6 +666,10 @@ sr_dis_exit:
bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID
str tmp2, [pmc, #AT91_PMC_PLL_UPDT]
/* save acr */
ldr tmp2, [pmc, #AT91_PMC_PLL_ACR]
str tmp2, .saved_acr
/* save div. */
mov tmp1, #0
ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0]
@ -758,7 +739,7 @@ sr_dis_exit:
str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
/* step 2. */
ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA
ldr tmp1, .saved_acr
str tmp1, [pmc, #AT91_PMC_PLL_ACR]
/* step 3. */
@ -904,7 +885,7 @@ e_done:
/**
* at91_mckx_ps_restore: restore MCKx settings
*
* Side effects: overwrites tmp1, tmp2
* Side effects: overwrites tmp1, tmp2 and tmp3
*/
.macro at91_mckx_ps_restore
#ifdef CONFIG_SOC_SAMA7
@ -980,7 +961,7 @@ r_ps:
bic tmp3, tmp3, #AT91_PMC_MCR_V2_ID_MSK
orr tmp3, tmp3, tmp1
orr tmp3, tmp3, #AT91_PMC_MCR_V2_CMD
str tmp2, [pmc, #AT91_PMC_MCR_V2]
str tmp3, [pmc, #AT91_PMC_MCR_V2]
wait_mckrdy tmp1
@ -1019,9 +1000,6 @@ save_mck:
at91_plla_disable
/* Enable low power mode for 2.5V regulator. */
at91_2_5V_reg_set_low_power 1
ldr tmp3, .pm_mode
cmp tmp3, #AT91_PM_ULP1
beq ulp1_mode
@ -1034,9 +1012,6 @@ ulp1_mode:
b ulp_exit
ulp_exit:
/* Disable low power mode for 2.5V regulator. */
at91_2_5V_reg_set_low_power 0
ldr pmc, .pmc_base
at91_plla_enable
@ -1207,6 +1182,8 @@ ENDPROC(at91_pm_suspend_in_sram)
#endif
.saved_mckr:
.word 0
.saved_acr:
.word 0
.saved_pllar:
.word 0
.saved_sam9_lpr:

23
arch/arm/mach-hpe/Kconfig
View File

@ -1,23 +0,0 @@
menuconfig ARCH_HPE
bool "HPE SoC support"
depends on ARCH_MULTI_V7
help
This enables support for HPE ARM based BMC chips.
if ARCH_HPE
config ARCH_HPE_GXP
bool "HPE GXP SoC"
depends on ARCH_MULTI_V7
select ARM_VIC
select GENERIC_IRQ_CHIP
select CLKSRC_MMIO
help
HPE GXP is the name of the HPE Soc. This SoC is used to implement many
BMC features at HPE. It supports ARMv7 architecture based on the Cortex
A9 core. It is capable of using an AXI bus to which a memory controller
is attached. It has multiple SPI interfaces to connect boot flash and
BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It
has multiple i2c engines to drive connectivity with a host
infrastructure.
endif

1
arch/arm/mach-hpe/Makefile
View File

@ -1 +0,0 @@
obj-$(CONFIG_ARCH_HPE_GXP) += gxp.o

15
arch/arm/mach-hpe/gxp.c
View File

@ -1,15 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P. */
#include <asm/mach/arch.h>
static const char * const gxp_board_dt_compat[] = {
"hpe,gxp",
NULL,
};
DT_MACHINE_START(GXP_DT, "HPE GXP")
.dt_compat = gxp_board_dt_compat,
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
MACHINE_END

19
arch/arm/mach-omap1/clock.c
View File

@ -705,14 +705,21 @@ static unsigned long omap1_clk_recalc_rate(struct clk_hw *hw, unsigned long p_ra
return clk->rate;
}
static long omap1_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *p_rate)
static int omap1_clk_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct omap1_clk *clk = to_omap1_clk(hw);
if (clk->round_rate != NULL)
return clk->round_rate(clk, rate, p_rate);
if (clk->round_rate != NULL) {
req->rate = clk->round_rate(clk, req->rate,
&req->best_parent_rate);
return omap1_clk_recalc_rate(hw, *p_rate);
return 0;
}
req->rate = omap1_clk_recalc_rate(hw, req->best_parent_rate);
return 0;
}
static int omap1_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long p_rate)
@ -771,7 +778,7 @@ const struct clk_ops omap1_clk_gate_ops = {
const struct clk_ops omap1_clk_rate_ops = {
.recalc_rate = omap1_clk_recalc_rate,
.round_rate = omap1_clk_round_rate,
.determine_rate = omap1_clk_determine_rate,
.set_rate = omap1_clk_set_rate,
.init = omap1_clk_init_op,
};
@ -784,7 +791,7 @@ const struct clk_ops omap1_clk_full_ops = {
.disable_unused = omap1_clk_disable_unused,
#endif
.recalc_rate = omap1_clk_recalc_rate,
.round_rate = omap1_clk_round_rate,
.determine_rate = omap1_clk_determine_rate,
.set_rate = omap1_clk_set_rate,
.init = omap1_clk_init_op,
};

36
arch/arm/mach-omap2/am33xx-restart.c
View File

@ -2,12 +2,46 @@
/*
* am33xx-restart.c - Code common to all AM33xx machines.
*/
#include <dt-bindings/pinctrl/am33xx.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/reboot.h>
#include "common.h"
#include "control.h"
#include "prm.h"
/*
* Advisory 1.0.36 EMU0 and EMU1: Terminals Must be Pulled High Before
* ICEPick Samples
*
* If EMU0/EMU1 pins have been used as GPIO outputs and actively driving low
* level, the device might not reboot in normal mode. We are in a bad position
* to override GPIO state here, so just switch the pins into EMU input mode
* (that's what reset will do anyway) and wait a bit, because the state will be
* latched 190 ns after reset.
*/
static void am33xx_advisory_1_0_36(void)
{
u32 emu0 = omap_ctrl_readl(AM335X_PIN_EMU0);
u32 emu1 = omap_ctrl_readl(AM335X_PIN_EMU1);
/* If both pins are in EMU mode, nothing to do */
if (!(emu0 & 7) && !(emu1 & 7))
return;
/* Switch GPIO3_7/GPIO3_8 into EMU0/EMU1 modes respectively */
omap_ctrl_writel(emu0 & ~7, AM335X_PIN_EMU0);
omap_ctrl_writel(emu1 & ~7, AM335X_PIN_EMU1);
/*
* Give pull-ups time to load the pin/PCB trace capacity.
* 5 ms shall be enough to load 1 uF (would be huge capacity for these
* pins) with TI-recommended 4k7 external pull-ups.
*/
mdelay(5);
}
/**
* am33xx_restart - trigger a software restart of the SoC
* @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
@ -18,6 +52,8 @@
*/
void am33xx_restart(enum reboot_mode mode, const char *cmd)
{
am33xx_advisory_1_0_36();
/* TODO: Handle cmd if necessary */
prm_reboot_mode = mode;

2
arch/arm/mach-omap2/board-n8x0.c
View File

@ -167,7 +167,7 @@ static int n8x0_mmc_set_power_menelaus(struct device *dev, int slot,
#ifdef CONFIG_MMC_DEBUG
dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1,
power_on ? "on" : "off", vdd);
str_on_off(power_on), vdd);
#endif
if (slot == 0) {
if (!power_on)

12
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
View File

@ -70,8 +70,8 @@ static unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
* Some might argue L3-DDR, others ARM, others IVA. This code is simple and
* just uses the ARM rates.
*/
static long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
static int omap2_determine_rate_to_table(struct clk_hw *hw,
struct clk_rate_request *req)
{
const struct prcm_config *ptr;
long highest_rate;
@ -87,10 +87,12 @@ static long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
highest_rate = ptr->mpu_speed;
/* Can check only after xtal frequency check */
if (ptr->mpu_speed <= rate)
if (ptr->mpu_speed <= req->rate)
break;
}
return highest_rate;
req->rate = highest_rate;
return 0;
}
/* Sets basic clocks based on the specified rate */
@ -215,7 +217,7 @@ static void omap2xxx_clkt_vps_late_init(void)
static const struct clk_ops virt_prcm_set_ops = {
.recalc_rate = &omap2_table_mpu_recalc,
.set_rate = &omap2_select_table_rate,
.round_rate = &omap2_round_to_table_rate,
.determine_rate = &omap2_determine_rate_to_table,
};
/**

6
arch/arm/mach-omap2/pm33xx-core.c
View File

@ -388,12 +388,15 @@ static int __init amx3_idle_init(struct device_node *cpu_node, int cpu)
if (!state_node)
break;
if (!of_device_is_available(state_node))
if (!of_device_is_available(state_node)) {
of_node_put(state_node);
continue;
}
if (i == CPUIDLE_STATE_MAX) {
pr_warn("%s: cpuidle states reached max possible\n",
__func__);
of_node_put(state_node);
break;
}
@ -403,6 +406,7 @@ static int __init amx3_idle_init(struct device_node *cpu_node, int cpu)
states[state_count].wfi_flags |= WFI_FLAG_WAKE_M3 |
WFI_FLAG_FLUSH_CACHE;
of_node_put(state_node);
state_count++;
}

2
arch/arm/mach-omap2/powerdomain.c
View File

@ -1111,7 +1111,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst)
int curr_pwrst;
int ret = 0;
if (!pwrdm || IS_ERR(pwrdm))
if (IS_ERR_OR_NULL(pwrdm))
return -EINVAL;
while (!(pwrdm->pwrsts & (1 << pwrst))) {

12
arch/arm/mach-omap2/voltage.c
View File

@ -51,7 +51,7 @@ static LIST_HEAD(voltdm_list);
*/
unsigned long voltdm_get_voltage(struct voltagedomain *voltdm)
{
if (!voltdm || IS_ERR(voltdm)) {
if (IS_ERR_OR_NULL(voltdm)) {
pr_warn("%s: VDD specified does not exist!\n", __func__);
return 0;
}
@ -73,7 +73,7 @@ static int voltdm_scale(struct voltagedomain *voltdm,
int ret, i;
unsigned long volt = 0;
if (!voltdm || IS_ERR(voltdm)) {
if (IS_ERR_OR_NULL(voltdm)) {
pr_warn("%s: VDD specified does not exist!\n", __func__);
return -EINVAL;
}
@ -124,7 +124,7 @@ void voltdm_reset(struct voltagedomain *voltdm)
{
unsigned long target_volt;
if (!voltdm || IS_ERR(voltdm)) {
if (IS_ERR_OR_NULL(voltdm)) {
pr_warn("%s: VDD specified does not exist!\n", __func__);
return;
}
@ -154,7 +154,7 @@ void voltdm_reset(struct voltagedomain *voltdm)
void omap_voltage_get_volttable(struct voltagedomain *voltdm,
struct omap_volt_data **volt_data)
{
if (!voltdm || IS_ERR(voltdm)) {
if (IS_ERR_OR_NULL(voltdm)) {
pr_warn("%s: VDD specified does not exist!\n", __func__);
return;
}
@ -182,7 +182,7 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
{
int i;
if (!voltdm || IS_ERR(voltdm)) {
if (IS_ERR_OR_NULL(voltdm)) {
pr_warn("%s: VDD specified does not exist!\n", __func__);
return ERR_PTR(-EINVAL);
}
@ -216,7 +216,7 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
int omap_voltage_register_pmic(struct voltagedomain *voltdm,
struct omap_voltdm_pmic *pmic)
{
if (!voltdm || IS_ERR(voltdm)) {
if (IS_ERR_OR_NULL(voltdm)) {
pr_warn("%s: VDD specified does not exist!\n", __func__);
return -EINVAL;
}

4
arch/arm/mach-omap2/vp.c
View File

@ -199,7 +199,7 @@ void omap_vp_enable(struct voltagedomain *voltdm)
struct omap_vp_instance *vp;
u32 vpconfig, volt;
if (!voltdm || IS_ERR(voltdm)) {
if (IS_ERR_OR_NULL(voltdm)) {
pr_warn("%s: VDD specified does not exist!\n", __func__);
return;
}
@ -244,7 +244,7 @@ void omap_vp_disable(struct voltagedomain *voltdm)
u32 vpconfig;
int timeout;
if (!voltdm || IS_ERR(voltdm)) {
if (IS_ERR_OR_NULL(voltdm)) {
pr_warn("%s: VDD specified does not exist!\n", __func__);
return;
}

2
arch/arm/mach-rockchip/Kconfig
View File

@ -13,7 +13,7 @@ config ARCH_ROCKCHIP
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select DW_APB_TIMER_OF
select REGULATOR if PM
select REGULATOR
select ROCKCHIP_TIMER
select ARM_GLOBAL_TIMER
select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK

2
arch/arm/mach-shmobile/pm-rcar-gen2.c
View File

@ -81,7 +81,7 @@ void __init rcar_gen2_pm_init(void)
map:
/* RAM for jump stub, because BAR requires 256KB aligned address */
if (res.start & (256 * 1024 - 1) ||
if (res.start & (SZ_256K - 1) ||
resource_size(&res) < shmobile_boot_size) {
pr_err("Invalid smp-sram region\n");
return;

9
arch/arm/mach-versatile/spc.c
View File

@ -497,12 +497,13 @@ static unsigned long spc_recalc_rate(struct clk_hw *hw,
return freq * 1000;
}
static long spc_round_rate(struct clk_hw *hw, unsigned long drate,
unsigned long *parent_rate)
static int spc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{
struct clk_spc *spc = to_clk_spc(hw);
return ve_spc_round_performance(spc->cluster, drate);
req->rate = ve_spc_round_performance(spc->cluster, req->rate);
return 0;
}
static int spc_set_rate(struct clk_hw *hw, unsigned long rate,
@ -515,7 +516,7 @@ static int spc_set_rate(struct clk_hw *hw, unsigned long rate,
static struct clk_ops clk_spc_ops = {
.recalc_rate = spc_recalc_rate,
.round_rate = spc_round_rate,
.determine_rate = spc_determine_rate,
.set_rate = spc_set_rate,
};

7
include/soc/at91/sama7-sfrbu.h
View File

@ -18,13 +18,6 @@
#define AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1) /* Power switch BU source selection */
#define AT91_SFRBU_PSWBU_CTRL (1 << 0) /* Power switch BU control */
#define AT91_SFRBU_25LDOCR (0x0C) /* SFRBU 2.5V LDO Control Register */
#define AT91_SFRBU_25LDOCR_LDOANAKEY (0x3B6E18 << 8) /* Specific value mandatory to allow writing of other register bits. */
#define AT91_SFRBU_25LDOCR_STATE (1 << 3) /* LDOANA Switch On/Off Control */
#define AT91_SFRBU_25LDOCR_LP (1 << 2) /* LDOANA Low-Power Mode Control */
#define AT91_SFRBU_PD_VALUE_MSK (0x3)
#define AT91_SFRBU_25LDOCR_PD_VALUE(v) ((v) & AT91_SFRBU_PD_VALUE_MSK) /* LDOANA Pull-down value */
#define AT91_FRBU_DDRPWR (0x10) /* SFRBU DDR Power Control Register */
#define AT91_FRBU_DDRPWR_STATE (1 << 0) /* DDR Power Mode State */