dt-bindings: phy: socionext,uniphier: add top-level constraints
Properties with variable number of items per each device are expected to have widest constraints in top-level "properties:" block and further customized (narrowed) in "if:then:". Add missing top-level constraints for clock-names and reset-names. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20240818172835.121757-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>pull/963/head
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@ -30,13 +30,17 @@ properties:
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minItems: 1
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maxItems: 2
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clock-names: true
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clock-names:
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minItems: 1
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maxItems: 6
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resets:
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minItems: 2
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maxItems: 6
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reset-names: true
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reset-names:
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minItems: 2
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maxItems: 6
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allOf:
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- if:
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@ -31,13 +31,17 @@ properties:
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minItems: 1
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maxItems: 2
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clock-names: true
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clock-names:
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minItems: 1
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maxItems: 2
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resets:
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minItems: 1
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maxItems: 2
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reset-names: true
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reset-names:
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minItems: 1
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maxItems: 2
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socionext,syscon:
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$ref: /schemas/types.yaml#/definitions/phandle
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@ -34,12 +34,15 @@ properties:
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minItems: 2
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maxItems: 3
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clock-names: true
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clock-names:
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minItems: 2
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maxItems: 3
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resets:
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maxItems: 2
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reset-names: true
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reset-names:
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maxItems: 2
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vbus-supply:
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description: A phandle to the regulator for USB VBUS
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@ -35,12 +35,15 @@ properties:
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minItems: 2
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maxItems: 3
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clock-names: true
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clock-names:
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minItems: 2
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maxItems: 3
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resets:
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maxItems: 2
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reset-names: true
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reset-names:
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maxItems: 2
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vbus-supply:
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description: A phandle to the regulator for USB VBUS, only for USB host
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