iio: adc: ad7606: add offset and phase calibration support
Add support for offset and phase calibration, only for
devices that support software mode, that are:
ad7606b
ad7606c-16
ad7606c-18
Tested-by: David Lechner <dlechner@baylibre.com>
Reviewed-by: Nuno Sá <nuno.sa@analog.com>
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://patch.msgid.link/20250606-wip-bl-ad7606-calibration-v9-3-6e014a1f92a2@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
pull/1279/head
Angelo Dureghello
Jonathan Cameron
parent
342c52dde2
commit
48d487dc64
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@ -95,6 +95,22 @@ static const unsigned int ad7616_oversampling_avail[8] = {
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1, 2, 4, 8, 16, 32, 64, 128,
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};
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static const int ad7606_calib_offset_avail[3] = {
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-128, 1, 127,
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};
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static const int ad7606c_18bit_calib_offset_avail[3] = {
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-512, 4, 508,
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};
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static const int ad7606b_calib_phase_avail[][2] = {
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{ 0, 0 }, { 0, 1250 }, { 0, 318750 },
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};
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static const int ad7606c_calib_phase_avail[][2] = {
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{ 0, 0 }, { 0, 1000 }, { 0, 255000 },
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};
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static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev,
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struct iio_chan_spec *chan);
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static int ad7606c_16bit_chan_scale_setup(struct iio_dev *indio_dev,
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@ -164,6 +180,8 @@ const struct ad7606_chip_info ad7606b_info = {
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.scale_setup_cb = ad7606_16bit_chan_scale_setup,
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.sw_setup_cb = ad7606b_sw_mode_setup,
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.offload_storagebits = 32,
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.calib_offset_avail = ad7606_calib_offset_avail,
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.calib_phase_avail = ad7606b_calib_phase_avail,
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};
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EXPORT_SYMBOL_NS_GPL(ad7606b_info, "IIO_AD7606");
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@ -177,6 +195,8 @@ const struct ad7606_chip_info ad7606c_16_info = {
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.scale_setup_cb = ad7606c_16bit_chan_scale_setup,
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.sw_setup_cb = ad7606b_sw_mode_setup,
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.offload_storagebits = 32,
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.calib_offset_avail = ad7606_calib_offset_avail,
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.calib_phase_avail = ad7606c_calib_phase_avail,
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};
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EXPORT_SYMBOL_NS_GPL(ad7606c_16_info, "IIO_AD7606");
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@ -226,6 +246,8 @@ const struct ad7606_chip_info ad7606c_18_info = {
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.scale_setup_cb = ad7606c_18bit_chan_scale_setup,
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.sw_setup_cb = ad7606b_sw_mode_setup,
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.offload_storagebits = 32,
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.calib_offset_avail = ad7606c_18bit_calib_offset_avail,
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.calib_phase_avail = ad7606c_calib_phase_avail,
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};
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EXPORT_SYMBOL_NS_GPL(ad7606c_18_info, "IIO_AD7606");
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@ -681,6 +703,40 @@ error_ret:
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return ret;
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}
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static int ad7606_get_calib_offset(struct ad7606_state *st, int ch, int *val)
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{
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int ret;
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ret = st->bops->reg_read(st, AD7606_CALIB_OFFSET(ch));
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if (ret < 0)
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return ret;
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*val = st->chip_info->calib_offset_avail[0] +
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ret * st->chip_info->calib_offset_avail[1];
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return 0;
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}
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static int ad7606_get_calib_phase(struct ad7606_state *st, int ch, int *val,
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int *val2)
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{
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int ret;
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ret = st->bops->reg_read(st, AD7606_CALIB_PHASE(ch));
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if (ret < 0)
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return ret;
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*val = 0;
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/*
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* ad7606b: phase delay from 0 to 318.75 μs in steps of 1.25 μs.
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* ad7606c-16/18: phase delay from 0 µs to 255 µs in steps of 1 µs.
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*/
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*val2 = ret * st->chip_info->calib_phase_avail[1][1];
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return 0;
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}
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static int ad7606_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val,
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@ -715,6 +771,22 @@ static int ad7606_read_raw(struct iio_dev *indio_dev,
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pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state);
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*val = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, cnvst_pwm_state.period);
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_CALIBBIAS:
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if (!iio_device_claim_direct(indio_dev))
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return -EBUSY;
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ret = ad7606_get_calib_offset(st, chan->scan_index, val);
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iio_device_release_direct(indio_dev);
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if (ret)
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return ret;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_CONVDELAY:
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if (!iio_device_claim_direct(indio_dev))
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return -EBUSY;
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ret = ad7606_get_calib_phase(st, chan->scan_index, val, val2);
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iio_device_release_direct(indio_dev);
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if (ret)
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return ret;
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return IIO_VAL_INT_PLUS_NANO;
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}
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return -EINVAL;
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}
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@ -765,6 +837,64 @@ static int ad7606_write_os_hw(struct iio_dev *indio_dev, int val)
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return 0;
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}
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static int ad7606_set_calib_offset(struct ad7606_state *st, int ch, int val)
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{
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int start_val, step_val, stop_val;
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int offset;
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start_val = st->chip_info->calib_offset_avail[0];
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step_val = st->chip_info->calib_offset_avail[1];
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stop_val = st->chip_info->calib_offset_avail[2];
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if (val < start_val || val > stop_val)
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return -EINVAL;
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offset = (val - start_val) / step_val;
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return st->bops->reg_write(st, AD7606_CALIB_OFFSET(ch), offset);
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}
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static int ad7606_set_calib_phase(struct ad7606_state *st, int ch, int val,
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int val2)
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{
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int wreg, start_ns, step_ns, stop_ns;
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if (val != 0)
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return -EINVAL;
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start_ns = st->chip_info->calib_phase_avail[0][1];
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step_ns = st->chip_info->calib_phase_avail[1][1];
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stop_ns = st->chip_info->calib_phase_avail[2][1];
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/*
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* ad7606b: phase delay from 0 to 318.75 μs in steps of 1.25 μs.
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* ad7606c-16/18: phase delay from 0 µs to 255 µs in steps of 1 µs.
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*/
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if (val2 < start_ns || val2 > stop_ns)
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return -EINVAL;
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wreg = val2 / step_ns;
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return st->bops->reg_write(st, AD7606_CALIB_PHASE(ch), wreg);
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}
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static int ad7606_write_raw_get_fmt(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan, long info)
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{
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switch (info) {
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case IIO_CHAN_INFO_SCALE:
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return IIO_VAL_INT_PLUS_MICRO;
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case IIO_CHAN_INFO_SAMP_FREQ:
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case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
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case IIO_CHAN_INFO_CALIBBIAS:
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_CONVDELAY:
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return IIO_VAL_INT_PLUS_NANO;
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default:
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return -EINVAL;
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}
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}
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static int ad7606_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val,
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@ -818,6 +948,18 @@ static int ad7606_write_raw(struct iio_dev *indio_dev,
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if (val < 0 && val2 != 0)
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return -EINVAL;
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return ad7606_set_sampling_freq(st, val);
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case IIO_CHAN_INFO_CALIBBIAS:
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if (!iio_device_claim_direct(indio_dev))
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return -EBUSY;
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ret = ad7606_set_calib_offset(st, chan->scan_index, val);
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iio_device_release_direct(indio_dev);
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return ret;
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case IIO_CHAN_INFO_CONVDELAY:
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if (!iio_device_claim_direct(indio_dev))
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return -EBUSY;
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ret = ad7606_set_calib_phase(st, chan->scan_index, val, val2);
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iio_device_release_direct(indio_dev);
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return ret;
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default:
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return -EINVAL;
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}
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@ -996,6 +1138,14 @@ static int ad7606_read_avail(struct iio_dev *indio_dev,
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*type = IIO_VAL_INT_PLUS_MICRO;
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return IIO_AVAIL_LIST;
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case IIO_CHAN_INFO_CALIBBIAS:
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*vals = st->chip_info->calib_offset_avail;
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*type = IIO_VAL_INT;
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return IIO_AVAIL_RANGE;
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case IIO_CHAN_INFO_CONVDELAY:
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*vals = (const int *)st->chip_info->calib_phase_avail;
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*type = IIO_VAL_INT_PLUS_NANO;
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return IIO_AVAIL_RANGE;
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}
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return -EINVAL;
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}
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@ -1058,6 +1208,7 @@ static const struct iio_info ad7606_info_sw_mode = {
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.read_raw = &ad7606_read_raw,
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.write_raw = &ad7606_write_raw,
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.read_avail = &ad7606_read_avail,
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.write_raw_get_fmt = ad7606_write_raw_get_fmt,
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.debugfs_reg_access = &ad7606_reg_access,
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.validate_trigger = &ad7606_validate_trigger,
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.update_scan_mode = &ad7606_update_scan_mode,
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@ -1250,6 +1401,15 @@ static int ad7606_probe_channels(struct iio_dev *indio_dev)
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chan->info_mask_separate_available |=
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BIT(IIO_CHAN_INFO_SCALE);
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if (st->chip_info->calib_offset_avail) {
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chan->info_mask_separate |=
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BIT(IIO_CHAN_INFO_CALIBBIAS) |
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BIT(IIO_CHAN_INFO_CONVDELAY);
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chan->info_mask_separate_available |=
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BIT(IIO_CHAN_INFO_CALIBBIAS) |
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BIT(IIO_CHAN_INFO_CONVDELAY);
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}
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/*
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* All chips with software mode support oversampling,
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* so we skip the oversampling_available check. And the
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@ -40,6 +40,11 @@
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#define AD7606_RANGE_CH_ADDR(ch) (0x03 + ((ch) >> 1))
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#define AD7606_OS_MODE 0x08
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#define AD7606_CALIB_GAIN(ch) (0x09 + (ch))
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#define AD7606_CALIB_GAIN_MASK GENMASK(5, 0)
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#define AD7606_CALIB_OFFSET(ch) (0x11 + (ch))
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#define AD7606_CALIB_PHASE(ch) (0x19 + (ch))
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struct ad7606_state;
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typedef int (*ad7606_scale_setup_cb_t)(struct iio_dev *indio_dev,
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@ -61,6 +66,8 @@ typedef int (*ad7606_sw_setup_cb_t)(struct iio_dev *indio_dev);
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* @init_delay_ms: required delay in milliseconds for initialization
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* after a restart
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* @offload_storagebits: storage bits used by the offload hw implementation
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* @calib_offset_avail: pointer to offset calibration range/limits array
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* @calib_phase_avail: pointer to phase calibration range/limits array
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*/
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struct ad7606_chip_info {
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unsigned int max_samplerate;
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@ -74,6 +81,8 @@ struct ad7606_chip_info {
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bool os_req_reset;
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unsigned long init_delay_ms;
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u8 offload_storagebits;
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const int *calib_offset_avail;
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const int (*calib_phase_avail)[2];
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};
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/**
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