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- Add new AMD MCA bank names and types to the MCA code, preceded by a clean 

up of the relevant places to have them more developer-friendly (read: sort
   them alphanumerically and clean up comments) such that adding new banks is
   easy
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Merge tag 'ras_core_for_v7.1_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull RAS updates from Borislav Petkov:

 - Add new AMD MCA bank names and types to the MCA code, preceded by a
   clean up of the relevant places to have them more developer-friendly
   (read: sort them alphanumerically and clean up comments) such that
   adding new banks is easy

* tag 'ras_core_for_v7.1_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/mce, EDAC/mce_amd: Add new SMCA bank types
  x86/mce, EDAC/mce_amd: Update CS bank type naming
  x86/mce, EDAC/mce_amd: Reorder SMCA bank type enums
master
Linus Torvalds 2026-04-14 15:32:39 -07:00
parent 1834703b84 b90d398138
commit 508fed6795
3 changed files with 138 additions and 110 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

62
arch/x86/include/asm/mce.h
View File

@ -343,44 +343,60 @@ extern void apei_mce_report_mem_error(int corrected,
*/
#ifdef CONFIG_X86_MCE_AMD
/* These may be used by multiple smca_hwid_mcatypes */
/*
* These may be used by multiple smca_hwid_mcatypes.
*
* Keep in alphanumeric order, numerals before letters.
* Exception: Keep "V2, etc." with their originals.
*/
enum smca_bank_types {
SMCA_LS = 0, /* Load Store */
SMCA_LS_V2,
SMCA_IF, /* Instruction Fetch */
SMCA_L2_CACHE, /* L2 Cache */
SMCA_CS, /* Coherent Station */
SMCA_CS_V2,
SMCA_DACC_BE, /* Data Acceleration Back-end */
SMCA_DACC_FE, /* Data Acceleration Front-end */
SMCA_DE, /* Decoder Unit */
SMCA_RESERVED, /* Reserved */
SMCA_EDDR5CMN, /* eDDR5 CMN */
SMCA_EX, /* Execution Unit */
SMCA_FP, /* Floating Point */
SMCA_GMI_PCS, /* GMI PCS Unit */
SMCA_GMI_PHY, /* GMI PHY Unit */
SMCA_IF, /* Instruction Fetch */
SMCA_L2_CACHE, /* L2 Cache */
SMCA_L3_CACHE, /* L3 Cache */
SMCA_CS, /* Coherent Slave */
SMCA_CS_V2,
SMCA_PIE, /* Power, Interrupts, etc. */
SMCA_UMC, /* Unified Memory Controller */
SMCA_UMC_V2,
SMCA_LS, /* Load Store */
SMCA_LS_V2,
SMCA_MA_LLC, /* Memory Attached Last Level Cache */
SMCA_PB, /* Parameter Block */
SMCA_PSP, /* Platform Security Processor */
SMCA_PSP_V2,
SMCA_SMU, /* System Management Unit */
SMCA_SMU_V2,
SMCA_MP5, /* Microprocessor 5 Unit */
SMCA_MPART, /* AMD Root of Trust Microprocessor */
SMCA_MPASP, /* AMD Secure Processor */
SMCA_MPASP_V2,
SMCA_MPDACC, /* MP for Data Acceleration */
SMCA_MPDMA, /* MPDMA Unit */
SMCA_MPM, /* Microprocessor Manageability Core */
SMCA_MPRAS, /* MP for RAS */
SMCA_NBIF, /* NBIF Unit */
SMCA_NBIO, /* Northbridge IO Unit */
SMCA_PB, /* Parameter Block */
SMCA_PCIE, /* PCI Express Unit */
SMCA_PCIE_V2,
SMCA_XGMI_PCS, /* xGMI PCS Unit */
SMCA_NBIF, /* NBIF Unit */
SMCA_SHUB, /* System HUB Unit */
SMCA_PCIE_PL, /* PCIe Link */
SMCA_PIE, /* Power, Interrupts, etc. */
SMCA_PSP, /* Platform Security Processor */
SMCA_PSP_V2,
SMCA_RESERVED, /* Reserved */
SMCA_SATA, /* SATA Unit */
SMCA_SHUB, /* System HUB Unit */
SMCA_SMU, /* System Management Unit */
SMCA_SMU_V2,
SMCA_SSBDCI, /* Die to Die Interconnect */
SMCA_UMC, /* Unified Memory Controller */
SMCA_UMC_V2,
SMCA_USB, /* USB Unit */
SMCA_USR_DP, /* Ultra Short Reach Data Plane Controller */
SMCA_USR_CP, /* Ultra Short Reach Control Plane Controller */
SMCA_GMI_PCS, /* GMI PCS Unit */
SMCA_XGMI_PHY, /* xGMI PHY Unit */
SMCA_USR_DP, /* Ultra Short Reach Data Plane Controller */
SMCA_WAFL_PHY, /* WAFL PHY Unit */
SMCA_GMI_PHY, /* GMI PHY Unit */
SMCA_XGMI_PCS, /* xGMI PCS Unit */
SMCA_XGMI_PHY, /* xGMI PHY Unit */
N_SMCA_BANK_TYPES
};

138
arch/x86/kernel/cpu/mce/amd.c
View File

@ -95,39 +95,49 @@ static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks);
static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts);
static const char * const smca_names[] = {
[SMCA_LS ... SMCA_LS_V2] = "load_store",
[SMCA_IF] = "insn_fetch",
[SMCA_L2_CACHE] = "l2_cache",
[SMCA_CS ... SMCA_CS_V2] = "coherent_station",
[SMCA_DACC_BE] = "dacc_be",
[SMCA_DACC_FE] = "dacc_fe",
[SMCA_DE] = "decode_unit",
[SMCA_RESERVED] = "reserved",
[SMCA_EDDR5CMN] = "eddr5_cmn",
[SMCA_EX] = "execution_unit",
[SMCA_FP] = "floating_point",
[SMCA_GMI_PCS] = "gmi_pcs",
[SMCA_GMI_PHY] = "gmi_phy",
[SMCA_IF] = "insn_fetch",
[SMCA_L2_CACHE] = "l2_cache",
[SMCA_L3_CACHE] = "l3_cache",
[SMCA_CS ... SMCA_CS_V2] = "coherent_slave",
[SMCA_LS ... SMCA_LS_V2] = "load_store",
[SMCA_MA_LLC] = "ma_llc",
[SMCA_MP5] = "mp5",
[SMCA_MPART] = "mpart",
[SMCA_MPASP ... SMCA_MPASP_V2] = "mpasp",
[SMCA_MPDACC] = "mpdacc",
[SMCA_MPDMA] = "mpdma",
[SMCA_MPM] = "mpm",
[SMCA_MPRAS] = "mpras",
[SMCA_NBIF] = "nbif",
[SMCA_NBIO] = "nbio",
[SMCA_PB] = "param_block",
[SMCA_PCIE ... SMCA_PCIE_V2] = "pcie",
[SMCA_PCIE_PL] = "pcie_pl",
[SMCA_PIE] = "pie",
[SMCA_PSP ... SMCA_PSP_V2] = "psp",
[SMCA_RESERVED] = "reserved",
[SMCA_SATA] = "sata",
[SMCA_SHUB] = "shub",
[SMCA_SMU ... SMCA_SMU_V2] = "smu",
[SMCA_SSBDCI] = "ssbdci",
/* UMC v2 is separate because both of them can exist in a single system. */
[SMCA_UMC] = "umc",
[SMCA_UMC_V2] = "umc_v2",
[SMCA_MA_LLC] = "ma_llc",
[SMCA_PB] = "param_block",
[SMCA_PSP ... SMCA_PSP_V2] = "psp",
[SMCA_SMU ... SMCA_SMU_V2] = "smu",
[SMCA_MP5] = "mp5",
[SMCA_MPDMA] = "mpdma",
[SMCA_NBIO] = "nbio",
[SMCA_PCIE ... SMCA_PCIE_V2] = "pcie",
[SMCA_XGMI_PCS] = "xgmi_pcs",
[SMCA_NBIF] = "nbif",
[SMCA_SHUB] = "shub",
[SMCA_SATA] = "sata",
[SMCA_USB] = "usb",
[SMCA_USR_DP] = "usr_dp",
[SMCA_USR_CP] = "usr_cp",
[SMCA_GMI_PCS] = "gmi_pcs",
[SMCA_XGMI_PHY] = "xgmi_phy",
[SMCA_USR_DP] = "usr_dp",
[SMCA_WAFL_PHY] = "wafl_phy",
[SMCA_GMI_PHY] = "gmi_phy",
[SMCA_XGMI_PCS] = "xgmi_pcs",
[SMCA_XGMI_PHY] = "xgmi_phy",
};
static const char *smca_get_name(enum smca_bank_types t)
@ -153,68 +163,60 @@ enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank)
}
EXPORT_SYMBOL_GPL(smca_get_bank_type);
/*
* Format:
* { bank_type, hwid_mcatype }
*
* alphanumerically sorted by bank type.
*/
static const struct smca_hwid smca_hwid_mcatypes[] = {
/* { bank_type, hwid_mcatype } */
/* Reserved type */
{ SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) },
/* ZN Core (HWID=0xB0) MCA types */
{ SMCA_LS, HWID_MCATYPE(0xB0, 0x0) },
{ SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) },
{ SMCA_IF, HWID_MCATYPE(0xB0, 0x1) },
{ SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) },
{ SMCA_CS, HWID_MCATYPE(0x2E, 0x0) },
{ SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) },
{ SMCA_DACC_BE, HWID_MCATYPE(0x164, 0x0) },
{ SMCA_DACC_FE, HWID_MCATYPE(0x157, 0x0) },
{ SMCA_DE, HWID_MCATYPE(0xB0, 0x3) },
/* HWID 0xB0 MCATYPE 0x4 is Reserved */
{ SMCA_EDDR5CMN, HWID_MCATYPE(0x1E0, 0x0) },
{ SMCA_EX, HWID_MCATYPE(0xB0, 0x5) },
{ SMCA_FP, HWID_MCATYPE(0xB0, 0x6) },
{ SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) },
{ SMCA_GMI_PHY, HWID_MCATYPE(0x269, 0x0) },
{ SMCA_IF, HWID_MCATYPE(0xB0, 0x1) },
{ SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) },
{ SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7) },
/* Data Fabric MCA types */
{ SMCA_CS, HWID_MCATYPE(0x2E, 0x0) },
{ SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) },
{ SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) },
{ SMCA_LS, HWID_MCATYPE(0xB0, 0x0) },
{ SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) },
{ SMCA_MA_LLC, HWID_MCATYPE(0x2E, 0x4) },
/* Unified Memory Controller MCA type */
{ SMCA_UMC, HWID_MCATYPE(0x96, 0x0) },
{ SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) },
/* Parameter Block MCA type */
{ SMCA_PB, HWID_MCATYPE(0x05, 0x0) },
/* Platform Security Processor MCA type */
{ SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) },
{ SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) },
/* System Management Unit MCA type */
{ SMCA_SMU, HWID_MCATYPE(0x01, 0x0) },
{ SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) },
/* Microprocessor 5 Unit MCA type */
{ SMCA_MP5, HWID_MCATYPE(0x01, 0x2) },
/* MPDMA MCA type */
{ SMCA_MPART, HWID_MCATYPE(0xFF, 0x2) },
{ SMCA_MPASP, HWID_MCATYPE(0xFD, 0x0) },
{ SMCA_MPASP_V2, HWID_MCATYPE(0xFD, 0x1) },
{ SMCA_MPDACC, HWID_MCATYPE(0xBE, 0x0) },
{ SMCA_MPDMA, HWID_MCATYPE(0x01, 0x3) },
/* Northbridge IO Unit MCA type */
{ SMCA_MPM, HWID_MCATYPE(0xF9, 0x0) },
{ SMCA_MPRAS, HWID_MCATYPE(0x12, 0x0) },
{ SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) },
{ SMCA_NBIO, HWID_MCATYPE(0x18, 0x0) },
/* PCI Express Unit MCA type */
{ SMCA_PB, HWID_MCATYPE(0x05, 0x0) },
{ SMCA_PCIE, HWID_MCATYPE(0x46, 0x0) },
{ SMCA_PCIE_V2, HWID_MCATYPE(0x46, 0x1) },
{ SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) },
{ SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) },
{ SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) },
{ SMCA_PCIE_PL, HWID_MCATYPE(0x1E1, 0x0) },
{ SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) },
{ SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) },
{ SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) },
{ SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) },
{ SMCA_SATA, HWID_MCATYPE(0xA8, 0x0) },
{ SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) },
{ SMCA_SMU, HWID_MCATYPE(0x01, 0x0) },
{ SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) },
{ SMCA_SSBDCI, HWID_MCATYPE(0x5C, 0x0) },
{ SMCA_UMC, HWID_MCATYPE(0x96, 0x0) },
{ SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) },
{ SMCA_USB, HWID_MCATYPE(0xAA, 0x0) },
{ SMCA_USR_DP, HWID_MCATYPE(0x170, 0x0) },
{ SMCA_USR_CP, HWID_MCATYPE(0x180, 0x0) },
{ SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) },
{ SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) },
{ SMCA_USR_DP, HWID_MCATYPE(0x170, 0x0) },
{ SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0) },
{ SMCA_GMI_PHY, HWID_MCATYPE(0x269, 0x0) },
{ SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) },
{ SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) },
};
/*

48
drivers/edac/mce_amd.c
View File

@ -689,36 +689,46 @@ static void decode_mc6_mce(struct mce *m)
}
static const char * const smca_long_names[] = {
[SMCA_LS ... SMCA_LS_V2] = "Load Store Unit",
[SMCA_IF] = "Instruction Fetch Unit",
[SMCA_L2_CACHE] = "L2 Cache",
[SMCA_CS ... SMCA_CS_V2] = "Coherent Station",
[SMCA_DACC_BE] = "DACC Back-end Unit",
[SMCA_DACC_FE] = "DACC Front-end Unit",
[SMCA_DE] = "Decode Unit",
[SMCA_RESERVED] = "Reserved",
[SMCA_EDDR5CMN] = "eDDR5 CMN Unit",
[SMCA_EX] = "Execution Unit",
[SMCA_FP] = "Floating Point Unit",
[SMCA_GMI_PCS] = "Global Memory Interconnect PCS Unit",
[SMCA_GMI_PHY] = "Global Memory Interconnect PHY Unit",
[SMCA_IF] = "Instruction Fetch Unit",
[SMCA_L2_CACHE] = "L2 Cache",
[SMCA_L3_CACHE] = "L3 Cache",
[SMCA_CS ... SMCA_CS_V2] = "Coherent Slave",
[SMCA_LS ... SMCA_LS_V2] = "Load Store Unit",
[SMCA_MP5] = "Microprocessor 5 Unit",
[SMCA_MPART] = "MPART Unit",
[SMCA_MPASP ... SMCA_MPASP_V2] = "MPASP Unit",
[SMCA_MPDACC] = "MPDACC Unit",
[SMCA_MPDMA] = "MPDMA Unit",
[SMCA_MPM] = "MPM Unit",
[SMCA_MPRAS] = "MPRAS Unit",
[SMCA_NBIF] = "NBIF Unit",
[SMCA_NBIO] = "Northbridge IO Unit",
[SMCA_PB] = "Parameter Block",
[SMCA_PCIE ... SMCA_PCIE_V2] = "PCI Express Unit",
[SMCA_PCIE_PL] = "PCIe Link Unit",
[SMCA_PIE] = "Power, Interrupts, etc.",
[SMCA_PSP ... SMCA_PSP_V2] = "Platform Security Processor",
[SMCA_RESERVED] = "Reserved",
[SMCA_SATA] = "SATA Unit",
[SMCA_SHUB] = "System Hub Unit",
[SMCA_SMU ... SMCA_SMU_V2] = "System Management Unit",
[SMCA_SSBDCI] = "Die to Die Interconnect Unit",
/* UMC v2 is separate because both of them can exist in a single system. */
[SMCA_UMC] = "Unified Memory Controller",
[SMCA_UMC_V2] = "Unified Memory Controller v2",
[SMCA_PB] = "Parameter Block",
[SMCA_PSP ... SMCA_PSP_V2] = "Platform Security Processor",
[SMCA_SMU ... SMCA_SMU_V2] = "System Management Unit",
[SMCA_MP5] = "Microprocessor 5 Unit",
[SMCA_MPDMA] = "MPDMA Unit",
[SMCA_NBIO] = "Northbridge IO Unit",
[SMCA_PCIE ... SMCA_PCIE_V2] = "PCI Express Unit",
[SMCA_XGMI_PCS] = "Ext Global Memory Interconnect PCS Unit",
[SMCA_NBIF] = "NBIF Unit",
[SMCA_SHUB] = "System Hub Unit",
[SMCA_SATA] = "SATA Unit",
[SMCA_USB] = "USB Unit",
[SMCA_GMI_PCS] = "Global Memory Interconnect PCS Unit",
[SMCA_XGMI_PHY] = "Ext Global Memory Interconnect PHY Unit",
[SMCA_WAFL_PHY] = "WAFL PHY Unit",
[SMCA_GMI_PHY] = "Global Memory Interconnect PHY Unit",
[SMCA_XGMI_PCS] = "Ext Global Memory Interconnect PCS Unit",
[SMCA_XGMI_PHY] = "Ext Global Memory Interconnect PHY Unit",
};
static const char *smca_get_long_name(enum smca_bank_types t)