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usb: musb: Constify struct musb_fifo_cfg 

'struct musb_fifo_cfg' are not modified in these drivers.

Constifying these structures moves some data to a read-only section, so
increase overall security.

On a x86_64, with allmodconfig, as an example:
Before:
======
   text	   data	    bss	    dec	    hex	filename
  64381	   5537	    202	  70120	  111e8	drivers/usb/musb/musb_core.o

After:
=====
   text	   data	    bss	    dec	    hex	filename
  64957	   4929	    202	  70088	  111c8	drivers/usb/musb/musb_core.o

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/26e6f3e25dc8e785d0034dd7e59918e455563e60.1737234596.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
pull/1193/head
Christophe JAILLET 2025-01-18 22:10:17 +01:00 committed by Greg Kroah-Hartman
parent 42bc7faaf3
commit 51333bfbf1
7 changed files with 15 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/driver-api/usb/writing_musb_glue_layer.rst
View File

@ -613,7 +613,7 @@ endpoints configuration from the hardware, so we use line 12 instruction
to bypass reading the configuration from silicon, and rely on a to bypass reading the configuration from silicon, and rely on a
hard-coded table that describes the endpoints configuration instead:: hard-coded table that describes the endpoints configuration instead::
static struct musb_fifo_cfg jz4740_musb_fifo_cfg[] = { static const struct musb_fifo_cfg jz4740_musb_fifo_cfg[] = {
{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 64, }, { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 64, },

4
drivers/usb/musb/jz4740.c
View File

@ -59,7 +59,7 @@ static irqreturn_t jz4740_musb_interrupt(int irq, void *__hci)
return IRQ_NONE; return IRQ_NONE;
} }
static struct musb_fifo_cfg jz4740_musb_fifo_cfg[] = { static const struct musb_fifo_cfg jz4740_musb_fifo_cfg[] = {
{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 64, }, { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 64, },
@ -205,7 +205,7 @@ static const struct musb_hdrc_platform_data jz4740_musb_pdata = {
.platform_ops = &jz4740_musb_ops, .platform_ops = &jz4740_musb_ops,
}; };
static struct musb_fifo_cfg jz4770_musb_fifo_cfg[] = { static const struct musb_fifo_cfg jz4770_musb_fifo_cfg[] = {
{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },

2
drivers/usb/musb/mediatek.c
View File

@ -365,7 +365,7 @@ static const struct musb_platform_ops mtk_musb_ops = {
#define MTK_MUSB_MAX_EP_NUM 8 #define MTK_MUSB_MAX_EP_NUM 8
#define MTK_MUSB_RAM_BITS 11 #define MTK_MUSB_RAM_BITS 11
static struct musb_fifo_cfg mtk_musb_mode_cfg[] = { static const struct musb_fifo_cfg mtk_musb_mode_cfg[] = {
{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },

2
drivers/usb/musb/mpfs.c
View File

@ -29,7 +29,7 @@ struct mpfs_glue {
struct clk *clk; struct clk *clk;
}; };
static struct musb_fifo_cfg mpfs_musb_mode_cfg[] = { static const struct musb_fifo_cfg mpfs_musb_mode_cfg[] = {
{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },

14
drivers/usb/musb/musb_core.c
View File

@ -1271,7 +1271,7 @@ MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
*/ */
/* mode 0 - fits in 2KB */ /* mode 0 - fits in 2KB */
static struct musb_fifo_cfg mode_0_cfg[] = { static const struct musb_fifo_cfg mode_0_cfg[] = {
{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
@ -1280,7 +1280,7 @@ static struct musb_fifo_cfg mode_0_cfg[] = {
}; };
/* mode 1 - fits in 4KB */ /* mode 1 - fits in 4KB */
static struct musb_fifo_cfg mode_1_cfg[] = { static const struct musb_fifo_cfg mode_1_cfg[] = {
{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
@ -1289,7 +1289,7 @@ static struct musb_fifo_cfg mode_1_cfg[] = {
}; };
/* mode 2 - fits in 4KB */ /* mode 2 - fits in 4KB */
static struct musb_fifo_cfg mode_2_cfg[] = { static const struct musb_fifo_cfg mode_2_cfg[] = {
{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
@ -1299,7 +1299,7 @@ static struct musb_fifo_cfg mode_2_cfg[] = {
}; };
/* mode 3 - fits in 4KB */ /* mode 3 - fits in 4KB */
static struct musb_fifo_cfg mode_3_cfg[] = { static const struct musb_fifo_cfg mode_3_cfg[] = {
{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
@ -1309,7 +1309,7 @@ static struct musb_fifo_cfg mode_3_cfg[] = {
}; };
/* mode 4 - fits in 16KB */ /* mode 4 - fits in 16KB */
static struct musb_fifo_cfg mode_4_cfg[] = { static const struct musb_fifo_cfg mode_4_cfg[] = {
{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
@ -1340,7 +1340,7 @@ static struct musb_fifo_cfg mode_4_cfg[] = {
}; };
/* mode 5 - fits in 8KB */ /* mode 5 - fits in 8KB */
static struct musb_fifo_cfg mode_5_cfg[] = { static const struct musb_fifo_cfg mode_5_cfg[] = {
{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
@ -1447,7 +1447,7 @@ fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
} }
static struct musb_fifo_cfg ep0_cfg = { static const struct musb_fifo_cfg ep0_cfg = {
.style = FIFO_RXTX, .maxpacket = 64, .style = FIFO_RXTX, .maxpacket = 64,
}; };

4
drivers/usb/musb/sunxi.c
View File

@ -629,7 +629,7 @@ static const struct musb_platform_ops sunxi_musb_ops = {
#define SUNXI_MUSB_RAM_BITS 11 #define SUNXI_MUSB_RAM_BITS 11
/* Allwinner OTG supports up to 5 endpoints */ /* Allwinner OTG supports up to 5 endpoints */
static struct musb_fifo_cfg sunxi_musb_mode_cfg_5eps[] = { static const struct musb_fifo_cfg sunxi_musb_mode_cfg_5eps[] = {
MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512), MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512), MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512), MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
@ -643,7 +643,7 @@ static struct musb_fifo_cfg sunxi_musb_mode_cfg_5eps[] = {
}; };
/* H3/V3s OTG supports only 4 endpoints */ /* H3/V3s OTG supports only 4 endpoints */
static struct musb_fifo_cfg sunxi_musb_mode_cfg_4eps[] = { static const struct musb_fifo_cfg sunxi_musb_mode_cfg_4eps[] = {
MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512), MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512), MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512), MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),

2
include/linux/usb/musb.h
View File

@ -61,7 +61,7 @@ struct musb_hdrc_eps_bits {
}; };
struct musb_hdrc_config { struct musb_hdrc_config {
struct musb_fifo_cfg *fifo_cfg; /* board fifo configuration */ const struct musb_fifo_cfg *fifo_cfg; /* board fifo configuration */
unsigned fifo_cfg_size; /* size of the fifo configuration */ unsigned fifo_cfg_size; /* size of the fifo configuration */
/* MUSB configuration-specific details */ /* MUSB configuration-specific details */