arm64: dts: qcom: ipq9574: Add details for eMMC
RDP433 and RDP418 has NAND and eMMC variants. Presently, only NAND variant is supported. To enable support for eMMC variant, add the relevant GPIO and regulator information. Do not enable NAND or eMMC by default in ipq9574-rdp-common.dtsi. Enable it in board specific DTS as applicable. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260205085936.3220108-2-varadarajan.narayanan@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>master
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@ -22,6 +22,15 @@
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stdout-path = "serial0:115200n8";
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};
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regulator_fixed_1p8: s1800 {
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compatible = "regulator-fixed";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-name = "fixed_1p8";
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};
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regulator_fixed_3p3: s3300 {
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compatible = "regulator-fixed";
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regulator-min-microvolt = <3300000>;
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@ -137,6 +146,11 @@
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};
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};
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&sdhc_1 {
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vmmc-supply = <®ulator_fixed_3p3>;
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vqmmc-supply = <®ulator_fixed_1p8>;
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};
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&sleep_clk {
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clock-frequency = <32000>;
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};
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@ -185,6 +199,38 @@
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bias-disable;
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};
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};
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sdc_default_state: sdc-default-state {
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clk-pins {
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pins = "gpio5";
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function = "sdc_clk";
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drive-strength = <8>;
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bias-disable;
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};
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cmd-pins {
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pins = "gpio4";
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function = "sdc_cmd";
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drive-strength = <8>;
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bias-pull-up;
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};
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data-pins {
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pins = "gpio0", "gpio1", "gpio2",
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"gpio3", "gpio6", "gpio7",
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"gpio8", "gpio9";
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function = "sdc_data";
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drive-strength = <8>;
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bias-pull-up;
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};
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rclk-pins {
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pins = "gpio10";
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function = "sdc_rclk";
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drive-strength = <8>;
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bias-pull-down;
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};
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};
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};
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&qpic_bam {
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@ -195,8 +241,6 @@
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pinctrl-0 = <&qpic_snand_default_state>;
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pinctrl-names = "default";
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status = "okay";
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flash@0 {
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compatible = "spi-nand";
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reg = <0>;
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@ -16,48 +16,6 @@
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};
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&sdhc_1 {
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pinctrl-0 = <&sdc_default_state>;
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pinctrl-names = "default";
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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max-frequency = <384000000>;
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bus-width = <8>;
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&qpic_nand {
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status = "okay";
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};
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&tlmm {
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sdc_default_state: sdc-default-state {
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clk-pins {
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pins = "gpio5";
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function = "sdc_clk";
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drive-strength = <8>;
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bias-disable;
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};
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cmd-pins {
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pins = "gpio4";
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function = "sdc_cmd";
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drive-strength = <8>;
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bias-pull-up;
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};
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data-pins {
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pins = "gpio0", "gpio1", "gpio2",
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"gpio3", "gpio6", "gpio7",
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"gpio8", "gpio9";
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function = "sdc_data";
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drive-strength = <8>;
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bias-pull-up;
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};
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rclk-pins {
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pins = "gpio10";
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function = "sdc_rclk";
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drive-strength = <8>;
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bias-pull-down;
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};
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};
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};
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@ -55,6 +55,10 @@
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status = "okay";
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};
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&qpic_nand {
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status = "okay";
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};
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&tlmm {
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pcie1_default: pcie1-default-state {
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@ -15,3 +15,7 @@
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compatible = "qcom,ipq9574-ap-al02-c6", "qcom,ipq9574";
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};
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&qpic_nand {
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status = "okay";
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};
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@ -15,3 +15,7 @@
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compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574";
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};
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&qpic_nand {
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status = "okay";
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};
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@ -14,3 +14,7 @@
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model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9";
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compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574";
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};
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&qpic_nand {
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status = "okay";
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};
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@ -463,6 +463,15 @@
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clock-names = "iface", "core", "xo", "ice";
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non-removable;
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supports-cqe;
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pinctrl-0 = <&sdc_default_state>;
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pinctrl-names = "default";
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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max-frequency = <384000000>;
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bus-width = <8>;
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status = "disabled";
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};
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