arm64: dts: qcom: ipq9574: Add details for eMMC

RDP433 and RDP418 has NAND and eMMC variants. Presently, only NAND
variant is supported. To enable support for eMMC variant, add the
relevant GPIO and regulator information.

Do not enable NAND or eMMC by default in ipq9574-rdp-common.dtsi. Enable
it in board specific DTS as applicable.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260205085936.3220108-2-varadarajan.narayanan@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
master
Varadarajan Narayanan 2026-02-05 14:29:33 +05:30 committed by Bjorn Andersson
parent 7aec47be7c
commit 53f5d2d61a
7 changed files with 72 additions and 45 deletions

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@ -22,6 +22,15 @@
stdout-path = "serial0:115200n8";
};
regulator_fixed_1p8: s1800 {
compatible = "regulator-fixed";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
regulator-name = "fixed_1p8";
};
regulator_fixed_3p3: s3300 {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
@ -137,6 +146,11 @@
};
};
&sdhc_1 {
vmmc-supply = <&regulator_fixed_3p3>;
vqmmc-supply = <&regulator_fixed_1p8>;
};
&sleep_clk {
clock-frequency = <32000>;
};
@ -185,6 +199,38 @@
bias-disable;
};
};
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio5";
function = "sdc_clk";
drive-strength = <8>;
bias-disable;
};
cmd-pins {
pins = "gpio4";
function = "sdc_cmd";
drive-strength = <8>;
bias-pull-up;
};
data-pins {
pins = "gpio0", "gpio1", "gpio2",
"gpio3", "gpio6", "gpio7",
"gpio8", "gpio9";
function = "sdc_data";
drive-strength = <8>;
bias-pull-up;
};
rclk-pins {
pins = "gpio10";
function = "sdc_rclk";
drive-strength = <8>;
bias-pull-down;
};
};
};
&qpic_bam {
@ -195,8 +241,6 @@
pinctrl-0 = <&qpic_snand_default_state>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;

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@ -16,48 +16,6 @@
};
&sdhc_1 {
pinctrl-0 = <&sdc_default_state>;
pinctrl-names = "default";
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
max-frequency = <384000000>;
bus-width = <8>;
&qpic_nand {
status = "okay";
};
&tlmm {
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio5";
function = "sdc_clk";
drive-strength = <8>;
bias-disable;
};
cmd-pins {
pins = "gpio4";
function = "sdc_cmd";
drive-strength = <8>;
bias-pull-up;
};
data-pins {
pins = "gpio0", "gpio1", "gpio2",
"gpio3", "gpio6", "gpio7",
"gpio8", "gpio9";
function = "sdc_data";
drive-strength = <8>;
bias-pull-up;
};
rclk-pins {
pins = "gpio10";
function = "sdc_rclk";
drive-strength = <8>;
bias-pull-down;
};
};
};

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@ -55,6 +55,10 @@
status = "okay";
};
&qpic_nand {
status = "okay";
};
&tlmm {
pcie1_default: pcie1-default-state {

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@ -15,3 +15,7 @@
compatible = "qcom,ipq9574-ap-al02-c6", "qcom,ipq9574";
};
&qpic_nand {
status = "okay";
};

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@ -15,3 +15,7 @@
compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574";
};
&qpic_nand {
status = "okay";
};

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@ -14,3 +14,7 @@
model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9";
compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574";
};
&qpic_nand {
status = "okay";
};

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@ -463,6 +463,15 @@
clock-names = "iface", "core", "xo", "ice";
non-removable;
supports-cqe;
pinctrl-0 = <&sdc_default_state>;
pinctrl-names = "default";
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
max-frequency = <384000000>;
bus-width = <8>;
status = "disabled";
};