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dt-bindings: phy: airoha: Add dtime and Rx AEQ IO registers 

Introduce Tx-Rx detection time and Rx AEQ mappings in Airoha EN7581
PCIe-PHY binding. This change is not introducing any backward compatibility
issue since the EN7581 dts is not upstream yet.

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/a018329ff9678f3360bc6381294f95c62d34f3e3.1719682943.git.lorenzo@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
pull/920/head
Lorenzo Bianconi 2024-06-29 19:51:48 +02:00 committed by Vinod Koul
parent e245c725c7
commit 5854d0aa52
1 changed files with 13 additions and 2 deletions
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15
Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml
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@ -21,12 +21,18 @@ properties:
- description: PCIE analog base address
- description: PCIE lane0 base address
- description: PCIE lane1 base address
- description: PCIE lane0 detection time base address
- description: PCIE lane1 detection time base address
- description: PCIE Rx AEQ base address
reg-names:
items:
- const: csr-2l
- const: pma0
- const: pma1
- const: p0-xr-dtime
- const: p1-xr-dtime
- const: rx-aeq
"#phy-cells":
const: 0
@ -52,7 +58,12 @@ examples:
#phy-cells = <0>;
reg = <0x0 0x1fa5a000 0x0 0xfff>,
<0x0 0x1fa5b000 0x0 0xfff>,
<0x0 0x1fa5c000 0x0 0xfff>;
reg-names = "csr-2l", "pma0", "pma1";
<0x0 0x1fa5c000 0x0 0xfff>,
<0x0 0x1fc10044 0x0 0x4>,
<0x0 0x1fc30044 0x0 0x4>,
<0x0 0x1fc15030 0x0 0x104>;
reg-names = "csr-2l", "pma0", "pma1",
"p0-xr-dtime", "p1-xr-dtime",
"rx-aeq";
};
};