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In SPI NOR, there was an issue with the RDCR capability, leading to 

several platforms no longer capable of using it for wrong reasons (the
 follow-up commit renames the helper to avoid future confusion).
 
 NAND controller drivers needed to be improved to fix some timings,
 a locking schenario and avoid certain operations during panic writes.
 
 The Spear600 DT binding conversion was done partially, leading to
 several warnings which have individually been fixed.
 
 Tudor gets replaced by Takahiro for the SPI NOR maintainance.
 
 Plus two more misc fixes.
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Merge tag 'mtd/fixes-for-7.0-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux

Pull MTD fixes from Miquel Raynal:

 - In SPI NOR, there was an issue with the RDCR capability, leading to
   several platforms no longer capable of using it for wrong reasons
   (the follow-up commit renames the helper to avoid future confusion)

 - NAND controller drivers needed to be improved to fix some timings, a
   locking schenario and avoid certain operations during panic writes

 - The Spear600 DT binding conversion was done partially, leading to
   several warnings which have individually been fixed

 - Tudor gets replaced by Takahiro for the SPI NOR maintainance

 - Plus two more misc fixes

* tag 'mtd/fixes-for-7.0-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux:
  mtd: rawnand: pl353: make sure optimal timings are applied
  mtd: spi-nor: Rename spi_nor_spimem_check_op()
  mtd: spi-nor: Fix RDCR controller capability core check
  mtd: rawnand: brcmnand: skip DMA during panic write
  mtd: rawnand: serialize lock/unlock against other NAND operations
  dt-bindings: mtd: st,spear600-smi: Fix example
  dt-bindings: mtd: st,spear600-smi: #address/size-cells is mandatory
  dt-bindings: mtd: st,spear600-smi: Fix description
  mtd: rawnand: cadence: Fix error check for dma_alloc_coherent() in cadence_nand_init()
  mtd: Avoid boot crash in RedBoot partition table parser
  MAINTAINERS: add Takahiro Kuwano as SPI NOR reviewer
  MAINTAINERS: remove Tudor Ambarus as SPI NOR maintainer
master
Linus Torvalds 2026-03-20 09:34:32 -07:00
parent 47e231cbd3 b9465b04de
commit 6ac513185c
8 changed files with 48 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
Documentation/devicetree/bindings/mtd/st,spear600-smi.yaml
View File

@ -19,9 +19,6 @@ description:
Flash sub nodes describe the memory range and optional per-flash
properties.
allOf:
- $ref: mtd.yaml#
properties:
compatible:
const: st,spear600-smi
@ -42,14 +39,29 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
description: Functional clock rate of the SMI controller in Hz.
st,smi-fast-mode:
type: boolean
description: Indicates that the attached flash supports fast read mode.
patternProperties:
"^flash@.*$":
$ref: /schemas/mtd/mtd.yaml#
properties:
reg:
maxItems: 1
st,smi-fast-mode:
type: boolean
description: Indicates that the attached flash supports fast read mode.
unevaluatedProperties: false
required:
- reg
required:
- compatible
- reg
- clock-rate
- "#address-cells"
- "#size-cells"
unevaluatedProperties: false
@ -64,7 +76,7 @@ examples:
interrupts = <12>;
clock-rate = <50000000>; /* 50 MHz */
flash@f8000000 {
flash@fc000000 {
reg = <0xfc000000 0x1000>;
st,smi-fast-mode;
};

2
MAINTAINERS
View File

@ -24902,9 +24902,9 @@ F: drivers/clk/spear/
F: drivers/pinctrl/spear/
SPI NOR SUBSYSTEM
M: Tudor Ambarus <tudor.ambarus@linaro.org>
M: Pratyush Yadav <pratyush@kernel.org>
M: Michael Walle <mwalle@kernel.org>
R: Takahiro Kuwano <takahiro.kuwano@infineon.com>
L: linux-mtd@lists.infradead.org
S: Maintained
W: http://www.linux-mtd.infradead.org/

6
drivers/mtd/nand/raw/brcmnand/brcmnand.c
View File

@ -2350,14 +2350,12 @@ static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
for (i = 0; i < ctrl->max_oob; i += 4)
oob_reg_write(ctrl, i, 0xffffffff);
if (mtd->oops_panic_write)
if (mtd->oops_panic_write) {
/* switch to interrupt polling and PIO mode */
disable_ctrl_irqs(ctrl);
if (use_dma(ctrl) && (has_edu(ctrl) || !oob) && flash_dma_buf_ok(buf)) {
} else if (use_dma(ctrl) && (has_edu(ctrl) || !oob) && flash_dma_buf_ok(buf)) {
if (ctrl->dma_trans(host, addr, (u32 *)buf, oob, mtd->writesize,
CMD_PROGRAM_PAGE))
ret = -EIO;
goto out;

2
drivers/mtd/nand/raw/cadence-nand-controller.c
View File

@ -3133,7 +3133,7 @@ static int cadence_nand_init(struct cdns_nand_ctrl *cdns_ctrl)
sizeof(*cdns_ctrl->cdma_desc),
&cdns_ctrl->dma_cdma_desc,
GFP_KERNEL);
if (!cdns_ctrl->dma_cdma_desc)
if (!cdns_ctrl->cdma_desc)
return -ENOMEM;
cdns_ctrl->buf_size = SZ_16K;

14
drivers/mtd/nand/raw/nand_base.c
View File

@ -4737,11 +4737,16 @@ static void nand_shutdown(struct mtd_info *mtd)
static int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
struct nand_chip *chip = mtd_to_nand(mtd);
int ret;
if (!chip->ops.lock_area)
return -ENOTSUPP;
return chip->ops.lock_area(chip, ofs, len);
nand_get_device(chip);
ret = chip->ops.lock_area(chip, ofs, len);
nand_release_device(chip);
return ret;
}
/**
@ -4753,11 +4758,16 @@ static int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
static int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
struct nand_chip *chip = mtd_to_nand(mtd);
int ret;
if (!chip->ops.unlock_area)
return -ENOTSUPP;
return chip->ops.unlock_area(chip, ofs, len);
nand_get_device(chip);
ret = chip->ops.unlock_area(chip, ofs, len);
nand_release_device(chip);
return ret;
}
/* Set default functions */

3
drivers/mtd/nand/raw/pl35x-nand-controller.c
View File

@ -862,6 +862,9 @@ static int pl35x_nfc_setup_interface(struct nand_chip *chip, int cs,
PL35X_SMC_NAND_TAR_CYCLES(tmgs.t_ar) |
PL35X_SMC_NAND_TRR_CYCLES(tmgs.t_rr);
writel(plnand->timings, nfc->conf_regs + PL35X_SMC_CYCLES);
pl35x_smc_update_regs(nfc);
return 0;
}

6
drivers/mtd/parsers/redboot.c
View File

@ -270,9 +270,9 @@ nogood:
strcpy(names, fl->img->name);
#ifdef CONFIG_MTD_REDBOOT_PARTS_READONLY
if (!memcmp(names, "RedBoot", 8) ||
!memcmp(names, "RedBoot config", 15) ||
!memcmp(names, "FIS directory", 14)) {
if (!strcmp(names, "RedBoot") ||
!strcmp(names, "RedBoot config") ||
!strcmp(names, "FIS directory")) {
parts[i].mask_flags = MTD_WRITEABLE;
}
#endif

14
drivers/mtd/spi-nor/core.c
View File

@ -2345,15 +2345,15 @@ int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
}
/**
* spi_nor_spimem_check_op - check if the operation is supported
* by controller
* spi_nor_spimem_check_read_pp_op - check if a read or a page program operation is
* supported by controller
*@nor: pointer to a 'struct spi_nor'
*@op: pointer to op template to be checked
*
* Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
*/
static int spi_nor_spimem_check_op(struct spi_nor *nor,
struct spi_mem_op *op)
static int spi_nor_spimem_check_read_pp_op(struct spi_nor *nor,
struct spi_mem_op *op)
{
/*
* First test with 4 address bytes. The opcode itself might
@ -2396,7 +2396,7 @@ static int spi_nor_spimem_check_readop(struct spi_nor *nor,
if (spi_nor_protocol_is_dtr(nor->read_proto))
op.dummy.nbytes *= 2;
return spi_nor_spimem_check_op(nor, &op);
return spi_nor_spimem_check_read_pp_op(nor, &op);
}
/**
@ -2414,7 +2414,7 @@ static int spi_nor_spimem_check_pp(struct spi_nor *nor,
spi_nor_spimem_setup_op(nor, &op, pp->proto);
return spi_nor_spimem_check_op(nor, &op);
return spi_nor_spimem_check_read_pp_op(nor, &op);
}
/**
@ -2466,7 +2466,7 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
if (spi_nor_spimem_check_op(nor, &op))
if (!spi_mem_supports_op(nor->spimem, &op))
nor->flags |= SNOR_F_NO_READ_CR;
}
}