ARM updates for 6.17-rc1
- Finish removing Coresight support -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEuNNh8scc2k/wOAE+9OeQG+StrGQFAmiRwswACgkQ9OeQG+St rGQ6MA//eZ15Ss0IKmiMVvde+zKQdu16QoUe5Fn85y8Lf1gEpBQpVxT55ygPD2sR WgppomiUp+HfaUhU8DBnBAgv+aJuMuEnIaKUF45Tnq+igHWAOF1/7zvAXNV8wbeW WRY/DDvLkq8vQGT03H2eDyPYy98w8v4uStiIbHNf3r0CmoomubZIKBbV6jkabG+V pliCmzziYuMDon//qldq2kyirSJ48o5nncZl1eMhdcw+qMuEiMuDsnEGbvmoszL4 kWzy4IlBa88cyN1fziack1NlCruHv/5Wi+IkuMK1QdeuDGApv4Gcl46NNcCLWWVE FLEAzw5O9GwPVG1lXXgVn6WmY6IP6FXhyFiGEQLtbD1guMMQkRtydFJ+jq89Mcrg Ver3mZWF5BwSYJrrSsfN1Pxz7biECHhmf2UKHK28zsAzy5n6Cq7LHJF3PWyqpd2p SbUhEZKRae4ohr3dtffCyESN48BSROqp53x7aULwDBBD0e3KwF6WNmMdCfIsnffq VtLyfzx13HFqNbzSIA0CjmF6oHV8/D3dGT0iEQxFgWDU9sGdYZx0H/fb+qRx+1h+ iVB03/gxqFcH4H3CXOK+PVevXKOZ1BCprujf+NQNjJoD40t6wgj3Tnl5ClzUsQwe YH4caHWNYP0SltOtkJ9kryPOXBL7XNnpZnkIzULzNrZ+18V+KGg= =HTDS -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rmk/linux Pull ARM update from Russell King: "Just one development update this time: - Finish removing Coresight support" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rmk/linux: ARM: 9449/1: coresight: Finish removal of Coresight support in arch/arm/kernelpull/1314/head
Linus Torvalds
commit
6bcdbd62bd
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASMARM_CTI_H
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#define __ASMARM_CTI_H
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#include <asm/io.h>
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#include <asm/hardware/coresight.h>
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/* The registers' definition is from section 3.2 of
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* Embedded Cross Trigger Revision: r0p0
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*/
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#define CTICONTROL 0x000
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#define CTISTATUS 0x004
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#define CTILOCK 0x008
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#define CTIPROTECTION 0x00C
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#define CTIINTACK 0x010
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#define CTIAPPSET 0x014
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#define CTIAPPCLEAR 0x018
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#define CTIAPPPULSE 0x01c
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#define CTIINEN 0x020
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#define CTIOUTEN 0x0A0
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#define CTITRIGINSTATUS 0x130
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#define CTITRIGOUTSTATUS 0x134
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#define CTICHINSTATUS 0x138
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#define CTICHOUTSTATUS 0x13c
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#define CTIPERIPHID0 0xFE0
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#define CTIPERIPHID1 0xFE4
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#define CTIPERIPHID2 0xFE8
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#define CTIPERIPHID3 0xFEC
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#define CTIPCELLID0 0xFF0
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#define CTIPCELLID1 0xFF4
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#define CTIPCELLID2 0xFF8
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#define CTIPCELLID3 0xFFC
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/* The below are from section 3.6.4 of
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* CoreSight v1.0 Architecture Specification
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*/
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#define LOCKACCESS 0xFB0
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#define LOCKSTATUS 0xFB4
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/**
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* struct cti - cross trigger interface struct
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* @base: mapped virtual address for the cti base
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* @irq: irq number for the cti
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* @trig_out_for_irq: triger out number which will cause
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* the @irq happen
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*
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* cti struct used to operate cti registers.
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*/
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struct cti {
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void __iomem *base;
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int irq;
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int trig_out_for_irq;
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};
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/**
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* cti_init - initialize the cti instance
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* @cti: cti instance
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* @base: mapped virtual address for the cti base
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* @irq: irq number for the cti
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* @trig_out: triger out number which will cause
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* the @irq happen
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*
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* called by machine code to pass the board dependent
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* @base, @irq and @trig_out to cti.
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*/
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static inline void cti_init(struct cti *cti,
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void __iomem *base, int irq, int trig_out)
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{
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cti->base = base;
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cti->irq = irq;
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cti->trig_out_for_irq = trig_out;
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}
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/**
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* cti_map_trigger - use the @chan to map @trig_in to @trig_out
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* @cti: cti instance
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* @trig_in: trigger in number
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* @trig_out: trigger out number
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* @channel: channel number
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*
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* This function maps one trigger in of @trig_in to one trigger
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* out of @trig_out using the channel @chan.
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*/
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static inline void cti_map_trigger(struct cti *cti,
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int trig_in, int trig_out, int chan)
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{
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void __iomem *base = cti->base;
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unsigned long val;
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val = __raw_readl(base + CTIINEN + trig_in * 4);
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val |= BIT(chan);
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__raw_writel(val, base + CTIINEN + trig_in * 4);
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val = __raw_readl(base + CTIOUTEN + trig_out * 4);
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val |= BIT(chan);
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__raw_writel(val, base + CTIOUTEN + trig_out * 4);
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}
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/**
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* cti_enable - enable the cti module
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* @cti: cti instance
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*
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* enable the cti module
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*/
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static inline void cti_enable(struct cti *cti)
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{
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__raw_writel(0x1, cti->base + CTICONTROL);
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}
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/**
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* cti_disable - disable the cti module
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* @cti: cti instance
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*
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* enable the cti module
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*/
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static inline void cti_disable(struct cti *cti)
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{
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__raw_writel(0, cti->base + CTICONTROL);
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}
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/**
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* cti_irq_ack - clear the cti irq
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* @cti: cti instance
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*
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* clear the cti irq
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*/
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static inline void cti_irq_ack(struct cti *cti)
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{
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void __iomem *base = cti->base;
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unsigned long val;
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val = __raw_readl(base + CTIINTACK);
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val |= BIT(cti->trig_out_for_irq);
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__raw_writel(val, base + CTIINTACK);
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}
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/**
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* cti_unlock - unlock cti module
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* @cti: cti instance
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*
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* unlock the cti module, or else any writes to the cti
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* module is not allowed.
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*/
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static inline void cti_unlock(struct cti *cti)
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{
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__raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS);
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}
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/**
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* cti_lock - lock cti module
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* @cti: cti instance
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*
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* lock the cti module, so any writes to the cti
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* module will be not allowed.
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*/
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static inline void cti_lock(struct cti *cti)
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{
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__raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS);
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}
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#endif
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Reference in New Issue