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ASoC: SOF: Intel: NVL/NVL-S: add platform name 

Bard Liao <yung-chuan.liao@linux.intel.com> says:

The platform name will be used in the topology name.

Link: https://patch.msgid.link/20260413060800.3156425-1-yung-chuan.liao@linux.intel.com
master
Mark Brown 2026-04-14 12:47:16 +01:00
parent cf162476f7 a158fe7b0c
commit 6e5b0fac10
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GPG Key ID: 24D68B725D5487D0
281 changed files with 2458 additions and 1379 deletions
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2
.mailmap
View File

@ -849,6 +849,8 @@ Tvrtko Ursulin <tursulin@ursulin.net> <tvrtko.ursulin@onelan.co.uk>
Tvrtko Ursulin <tursulin@ursulin.net> <tvrtko@ursulin.net>
Tycho Andersen <tycho@tycho.pizza> <tycho@tycho.ws>
Tzung-Bi Shih <tzungbi@kernel.org> <tzungbi@google.com>
Ulf Hansson <ulfh@kernel.org> <ulf.hansson@linaro.org>
Ulf Hansson <ulfh@kernel.org> <ulf.hansson@stericsson.com>
Umang Jain <uajain@igalia.com> <umang.jain@ideasonboard.com>
Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
Uwe Kleine-König <u.kleine-koenig@baylibre.com> <ukleinek@baylibre.com>

57
Documentation/arch/riscv/zicfilp.rst
View File

@ -76,34 +76,49 @@ the program.
4. prctl() enabling
--------------------
:c:macro:`PR_SET_INDIR_BR_LP_STATUS` / :c:macro:`PR_GET_INDIR_BR_LP_STATUS` /
:c:macro:`PR_LOCK_INDIR_BR_LP_STATUS` are three prctls added to manage indirect
branch tracking. These prctls are architecture-agnostic and return -EINVAL if
the underlying functionality is not supported.
Per-task indirect branch tracking state can be monitored and
controlled via the :c:macro:`PR_GET_CFI` and :c:macro:`PR_SET_CFI`
``prctl()` arguments (respectively), by supplying
:c:macro:`PR_CFI_BRANCH_LANDING_PADS` as the second argument. These
are architecture-agnostic, and will return -EINVAL if the underlying
functionality is not supported.
* prctl(PR_SET_INDIR_BR_LP_STATUS, unsigned long arg)
* prctl(:c:macro:`PR_SET_CFI`, :c:macro:`PR_CFI_BRANCH_LANDING_PADS`, unsigned long arg)
If arg1 is :c:macro:`PR_INDIR_BR_LP_ENABLE` and if CPU supports
``zicfilp`` then the kernel will enable indirect branch tracking for the
task. The dynamic loader can issue this :c:macro:`prctl` once it has
arg is a bitmask.
If :c:macro:`PR_CFI_ENABLE` is set in arg, and the CPU supports
``zicfilp``, then the kernel will enable indirect branch tracking for
the task. The dynamic loader can issue this ``prctl()`` once it has
determined that all the objects loaded in the address space support
indirect branch tracking. Additionally, if there is a `dlopen` to an
object which wasn't compiled with ``zicfilp``, the dynamic loader can
issue this prctl with arg1 set to 0 (i.e. :c:macro:`PR_INDIR_BR_LP_ENABLE`
cleared).
indirect branch tracking.
* prctl(PR_GET_INDIR_BR_LP_STATUS, unsigned long * arg)
Indirect branch tracking state can also be locked once enabled. This
prevents the task from subsequently disabling it. This is done by
setting the bit :c:macro:`PR_CFI_LOCK` in arg. Either indirect branch
tracking must already be enabled for the task, or the bit
:c:macro:`PR_CFI_ENABLE` must also be set in arg. This is intended
for environments that wish to run with a strict security posture that
do not wish to load objects without ``zicfilp`` support.
Returns the current status of indirect branch tracking. If enabled
it'll return :c:macro:`PR_INDIR_BR_LP_ENABLE`
Indirect branch tracking can also be disabled for the task, assuming
that it has not previously been enabled and locked. If there is a
``dlopen()`` to an object which wasn't compiled with ``zicfilp``, the
dynamic loader can issue this ``prctl()`` with arg set to
:c:macro:`PR_CFI_DISABLE`. Disabling indirect branch tracking for the
task is not possible if it has previously been enabled and locked.
* prctl(PR_LOCK_INDIR_BR_LP_STATUS, unsigned long arg)
Locks the current status of indirect branch tracking on the task. User
space may want to run with a strict security posture and wouldn't want
loading of objects without ``zicfilp`` support in them, to disallow
disabling of indirect branch tracking. In this case, user space can
use this prctl to lock the current settings.
* prctl(:c:macro:`PR_GET_CFI`, :c:macro:`PR_CFI_BRANCH_LANDING_PADS`, unsigned long * arg)
Returns the current status of indirect branch tracking into a bitmask
stored into the memory location pointed to by arg. The bitmask will
have the :c:macro:`PR_CFI_ENABLE` bit set if indirect branch tracking
is currently enabled for the task, and if it is locked, will
additionally have the :c:macro:`PR_CFI_LOCK` bit set. If indirect
branch tracking is currently disabled for the task, the
:c:macro:`PR_CFI_DISABLE` bit will be set.
5. violations related to indirect branch tracking
--------------------------------------------------

5
Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
View File

@ -33,7 +33,7 @@ properties:
- const: core
iommus:
maxItems: 2
maxItems: 1
interconnects:
items:
@ -107,8 +107,7 @@ examples:
interconnect-names = "mdp0-mem",
"cpu-cfg";
iommus = <&apps_smmu 0x420 0x2>,
<&apps_smmu 0x421 0x0>;
iommus = <&apps_smmu 0x420 0x2>;
ranges;
display-controller@5e01000 {

7
Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml
View File

@ -42,7 +42,7 @@ properties:
- const: vcodec0_bus
iommus:
maxItems: 5
maxItems: 2
interconnects:
maxItems: 2
@ -102,10 +102,7 @@ examples:
memory-region = <&pil_video_mem>;
iommus = <&apps_smmu 0x860 0x0>,
<&apps_smmu 0x880 0x0>,
<&apps_smmu 0x861 0x04>,
<&apps_smmu 0x863 0x0>,
<&apps_smmu 0x804 0xe0>;
<&apps_smmu 0x880 0x0>;
interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,

4
Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
View File

@ -42,7 +42,7 @@ properties:
- const: mgbe
- const: mac
- const: mac-divider
- const: ptp-ref
- const: ptp_ref
- const: rx-input-m
- const: rx-input
- const: tx
@ -133,7 +133,7 @@ examples:
<&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
<&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
<&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m",
"rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
"rx-pcs", "tx-pcs";
resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,

21
MAINTAINERS
View File

@ -1272,6 +1272,7 @@ F: drivers/hid/amd-sfh-hid/
AMD SPI DRIVER
M: Raju Rangoju <Raju.Rangoju@amd.com>
M: Krishnamoorthi M <krishnamoorthi.m@amd.com>
L: linux-spi@vger.kernel.org
S: Supported
F: drivers/spi/spi-amd-pci.c
@ -1291,6 +1292,7 @@ F: include/uapi/drm/amdxdna_accel.h
AMD XGBE DRIVER
M: Raju Rangoju <Raju.Rangoju@amd.com>
M: Prashanth Kumar K R <PrashanthKumar.K.R@amd.com>
L: netdev@vger.kernel.org
S: Maintained
F: arch/arm64/boot/dts/amd/amd-seattle-xgbe*.dtsi
@ -6716,7 +6718,7 @@ F: include/linux/platform_data/cpuidle-exynos.h
CPUIDLE DRIVER - ARM PSCI
M: Lorenzo Pieralisi <lpieralisi@kernel.org>
M: Sudeep Holla <sudeep.holla@kernel.org>
M: Ulf Hansson <ulf.hansson@linaro.org>
M: Ulf Hansson <ulfh@kernel.org>
L: linux-pm@vger.kernel.org
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported
@ -6724,7 +6726,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm.git
F: drivers/cpuidle/cpuidle-psci.c
CPUIDLE DRIVER - ARM PSCI PM DOMAIN
M: Ulf Hansson <ulf.hansson@linaro.org>
M: Ulf Hansson <ulfh@kernel.org>
L: linux-pm@vger.kernel.org
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported
@ -6733,7 +6735,7 @@ F: drivers/cpuidle/cpuidle-psci-domain.c
F: drivers/cpuidle/cpuidle-psci.h
CPUIDLE DRIVER - DT IDLE PM DOMAIN
M: Ulf Hansson <ulf.hansson@linaro.org>
M: Ulf Hansson <ulfh@kernel.org>
L: linux-pm@vger.kernel.org
S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm.git
@ -10729,7 +10731,7 @@ F: Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.yaml
F: drivers/i2c/muxes/i2c-demux-pinctrl.c
GENERIC PM DOMAINS
M: Ulf Hansson <ulf.hansson@linaro.org>
M: Ulf Hansson <ulfh@kernel.org>
L: linux-pm@vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/power/power?domain*
@ -18089,7 +18091,7 @@ F: drivers/mmc/host/mmc_spi.c
F: include/linux/spi/mmc_spi.h
MULTIMEDIA CARD (MMC), SECURE DIGITAL (SD) AND SDIO SUBSYSTEM
M: Ulf Hansson <ulf.hansson@linaro.org>
M: Ulf Hansson <ulfh@kernel.org>
L: linux-mmc@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git
@ -21075,8 +21077,7 @@ F: include/uapi/linux/atmppp.h
F: net/atm/pppoatm.c
PPP OVER ETHERNET
M: Michal Ostrowski <mostrows@earthlink.net>
S: Maintained
S: Orphan
F: drivers/net/ppp/pppoe.c
F: drivers/net/ppp/pppox.c
@ -22130,7 +22131,7 @@ S: Supported
F: drivers/infiniband/sw/rdmavt
RDS - RELIABLE DATAGRAM SOCKETS
M: Allison Henderson <allison.henderson@oracle.com>
M: Allison Henderson <achender@kernel.org>
L: netdev@vger.kernel.org
L: linux-rdma@vger.kernel.org
L: rds-devel@oss.oracle.com (moderated for non-subscribers)
@ -24696,7 +24697,7 @@ F: drivers/media/i2c/imx415.c
SONY MEMORYSTICK SUBSYSTEM
M: Maxim Levitsky <maximlevitsky@gmail.com>
M: Alex Dubov <oakad@yahoo.com>
M: Ulf Hansson <ulf.hansson@linaro.org>
M: Ulf Hansson <ulfh@kernel.org>
L: linux-mmc@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git
@ -27615,7 +27616,7 @@ F: Documentation/fb/uvesafb.rst
F: drivers/video/fbdev/uvesafb.*
Ux500 CLOCK DRIVERS
M: Ulf Hansson <ulf.hansson@linaro.org>
M: Ulf Hansson <ulfh@kernel.org>
L: linux-clk@vger.kernel.org
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained

2
Makefile
View File

@ -2,7 +2,7 @@
VERSION = 7
PATCHLEVEL = 0
SUBLEVEL = 0
EXTRAVERSION = -rc7
EXTRAVERSION =
NAME = Baby Opossum Posse
# *DOCUMENTATION*

2
arch/arm/boot/dts/microchip/sam9x7.dtsi
View File

@ -1226,7 +1226,7 @@
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <26>;
#gpio-lines = <27>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};

6
arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi
View File

@ -36,12 +36,8 @@
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c3 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi
View File

@ -172,12 +172,8 @@
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi
View File

@ -102,12 +102,8 @@
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
View File

@ -73,12 +73,8 @@
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c3 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi
View File

@ -260,14 +260,10 @@
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c3 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi
View File

@ -252,13 +252,9 @@
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
fsl,no-blockmark-swap;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts
View File

@ -133,12 +133,8 @@
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi
View File

@ -101,12 +101,8 @@
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi
View File

@ -63,12 +63,8 @@
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi
View File

@ -296,13 +296,9 @@
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
fsl,no-blockmark-swap;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c2 {

12
arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi
View File

@ -160,15 +160,11 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
fsl,use-minimum-ecc;
nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
};
};
/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */

12
arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi
View File

@ -43,15 +43,11 @@
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-ecc-mode = "hw";
nand-ecc-strength = <0>;
nand-ecc-step-size = <0>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-ecc-mode = "hw";
nand-ecc-strength = <0>;
nand-ecc-step-size = <0>;
nand-on-flash-bbt;
};
};
&iomuxc {

6
arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi
View File

@ -60,12 +60,8 @@
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&uart1 {

6
arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts
View File

@ -25,12 +25,8 @@
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&snvs_poweroff {

8
arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi
View File

@ -375,14 +375,10 @@
/* NAND on such SKUs */
&gpmi {
fsl,use-minimum-ecc;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand@0 {
reg = <0>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
};
};
/* On-module Power I2C */

2
arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
View File

@ -901,7 +901,7 @@
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_BUS_R_SPI>, <&r_ccu CLK_R_SPI>;
clock-names = "ahb", "mod";
dmas = <&dma 53>, <&dma 53>;
dmas = <&mcu_dma 13>, <&mcu_dma 13>;
dma-names = "rx", "tx";
resets = <&r_ccu RST_BUS_R_SPI>;
status = "disabled";

2
arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts
View File

@ -7,7 +7,7 @@
&a53_opp_table {
opp-1000000000 {
opp-microvolt = <950000>;
opp-microvolt = <1000000>;
};
};

24
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
View File

@ -880,9 +880,9 @@
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <880000>;
rohm,dvs-idle-voltage = <820000>;
rohm,dvs-suspend-voltage = <810000>;
rohm,dvs-run-voltage = <900000>;
rohm,dvs-idle-voltage = <850000>;
rohm,dvs-suspend-voltage = <850000>;
regulator-always-on;
};
@ -892,8 +892,8 @@
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <950000>;
rohm,dvs-idle-voltage = <850000>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
regulator-always-on;
};
@ -902,14 +902,14 @@
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
rohm,dvs-run-voltage = <850000>;
rohm,dvs-run-voltage = <900000>;
};
buck4_reg: BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
rohm,dvs-run-voltage = <930000>;
rohm,dvs-run-voltage = <1000000>;
};
buck5_reg: BUCK5 {
@ -1448,13 +1448,3 @@
fsl,ext-reset-output;
status = "okay";
};
&a53_opp_table {
opp-1000000000 {
opp-microvolt = <850000>;
};
opp-1500000000 {
opp-microvolt = <950000>;
};
};

2
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -1632,7 +1632,7 @@
<&clk IMX8MQ_GPU_PLL_OUT>,
<&clk IMX8MQ_GPU_PLL>;
assigned-clock-rates = <800000000>, <800000000>,
<800000000>, <800000000>, <0>;
<800000000>, <400000000>, <0>;
power-domains = <&pgc_gpu>;
};

20
arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi
View File

@ -272,20 +272,20 @@
/* enable SION for data and cmd pad due to ERR052021 */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = /* PD | FSEL 3 | DSE X5 */
<MX91_PAD_SD1_CLK__USDHC1_CLK 0x5be>,
<MX91_PAD_SD1_CLK__USDHC1_CLK 0x59e>,
/* HYS | FSEL 0 | no drive */
<MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1000>,
/* HYS | FSEL 3 | X5 */
<MX91_PAD_SD1_CMD__USDHC1_CMD 0x400011be>,
<MX91_PAD_SD1_CMD__USDHC1_CMD 0x4000139e>,
/* HYS | FSEL 3 | X4 */
<MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x4000119e>,
<MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x4000119e>,
<MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x4000119e>,
<MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x4000119e>,
<MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x4000119e>,
<MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x4000119e>,
<MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x4000119e>,
<MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x4000119e>;
<MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e>,
<MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e>,
<MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x4000139e>,
<MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e>,
<MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e>,
<MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e>,
<MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e>,
<MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e>;
};
pinctrl_wdog: wdoggrp {

2
arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
View File

@ -507,6 +507,7 @@
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
fsl,tuning-step = <1>;
status = "okay";
};
@ -519,6 +520,7 @@
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
no-mmc;
fsl,tuning-step = <1>;
status = "okay";
};

26
arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
View File

@ -271,21 +271,21 @@
/* enable SION for data and cmd pad due to ERR052021 */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
/* PD | FSEL 3 | DSE X5 */
MX93_PAD_SD1_CLK__USDHC1_CLK 0x5be
/* PD | FSEL 3 | DSE X4 */
MX93_PAD_SD1_CLK__USDHC1_CLK 0x59e
/* HYS | FSEL 0 | no drive */
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1000
/* HYS | FSEL 3 | X5 */
MX93_PAD_SD1_CMD__USDHC1_CMD 0x400011be
/* HYS | FSEL 3 | X4 */
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000119e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000119e
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000119e
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000119e
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000119e
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000119e
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000119e
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000119e
/* HYS | PU | FSEL 3 | DSE X4 */
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
/* HYS | PU | FSEL 3 | DSE X4 */
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000139e
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e
>;
};

2
arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
View File

@ -179,7 +179,7 @@
};
&pcie {
reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcie>;
status = "okay";
};

1
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
View File

@ -122,6 +122,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xf0000000 0x10000000>;
dma-ranges = <0x0 0x0 0x0 0x40000000>;
crg: clock-reset-controller@8a22000 {
compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";

11
arch/arm64/boot/dts/qcom/agatti.dtsi
View File

@ -1669,8 +1669,7 @@
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
interconnect-names = "gfx-mem";
iommus = <&adreno_smmu 0 1>,
<&adreno_smmu 2 0>;
iommus = <&adreno_smmu 0 1>;
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&rpmpd QCM2290_VDDCX>;
qcom,gmu = <&gmu_wrapper>;
@ -1951,8 +1950,7 @@
power-domains = <&dispcc MDSS_GDSC>;
iommus = <&apps_smmu 0x420 0x2>,
<&apps_smmu 0x421 0x0>;
iommus = <&apps_smmu 0x420 0x2>;
interconnects = <&mmrt_virt MASTER_MDP0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
@ -2436,10 +2434,7 @@
memory-region = <&pil_video_mem>;
iommus = <&apps_smmu 0x860 0x0>,
<&apps_smmu 0x880 0x0>,
<&apps_smmu 0x861 0x04>,
<&apps_smmu 0x863 0x0>,
<&apps_smmu 0x804 0xe0>;
<&apps_smmu 0x880 0x0>;
interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,

2
arch/arm64/boot/dts/qcom/hamoa.dtsi
View File

@ -269,7 +269,7 @@
idle-state-name = "ret";
arm,psci-suspend-param = <0x00000004>;
entry-latency-us = <180>;
exit-latency-us = <500>;
exit-latency-us = <320>;
min-residency-us = <600>;
};
};

9
arch/arm64/boot/dts/qcom/monaco.dtsi
View File

@ -765,6 +765,11 @@
hwlocks = <&tcsr_mutex 3>;
};
gunyah_md_mem: gunyah-md-region@91a80000 {
reg = <0x0 0x91a80000 0x0 0x80000>;
no-map;
};
lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 {
reg = <0x0 0x93b00000 0x0 0xf00000>;
no-map;
@ -6414,12 +6419,12 @@
};
qup_uart10_rts: qup-uart10-rts-state {
pins = "gpio84";
pins = "gpio85";
function = "qup1_se2";
};
qup_uart10_tx: qup-uart10-tx-state {
pins = "gpio85";
pins = "gpio86";
function = "qup1_se2";
};

2
arch/arm64/boot/dts/qcom/qcm6490-idp.dts
View File

@ -177,7 +177,7 @@
pinctrl-0 = <&wcd_default>;
pinctrl-names = "default";
reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>;
reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
vdd-buck-supply = <&vreg_l17b_1p7>;
vdd-rxtx-supply = <&vreg_l18b_1p8>;

16
arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi
View File

@ -1032,9 +1032,6 @@
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
@ -1048,10 +1045,12 @@
status = "okay";
};
&pcie6a {
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
&pcie4_port0 {
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
};
&pcie6a {
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
@ -1067,6 +1066,11 @@
status = "okay";
};
&pcie6a_port0 {
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
};
&pm8550_gpios {
rtmr0_default: rtmr0-reset-n-active-state {
pins = "gpio10";

24
arch/arm64/boot/dts/qcom/x1-crd.dtsi
View File

@ -1216,15 +1216,17 @@
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
status = "okay";
};
&pcie4_port0 {
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
};
&pcie4_phy {
vdda-phy-supply = <&vreg_l3i_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
@ -1233,9 +1235,6 @@
};
&pcie5 {
perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_wwan>;
pinctrl-0 = <&pcie5_default>;
@ -1251,10 +1250,12 @@
status = "okay";
};
&pcie6a {
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
&pcie5_port0 {
reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
};
&pcie6a {
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-names = "default";
@ -1270,6 +1271,11 @@
status = "okay";
};
&pcie6a_port0 {
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
};
&pm8550_gpios {
kypd_vol_up_n: kypd-vol-up-n-state {
pins = "gpio6";

14
arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi
View File

@ -1081,9 +1081,6 @@
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
@ -1098,6 +1095,9 @@
};
&pcie4_port0 {
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@ -1115,9 +1115,6 @@
};
&pcie6a {
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
@ -1126,6 +1123,11 @@
status = "okay";
};
&pcie6a_port0 {
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
};
&pcie6a_phy {
vdda-phy-supply = <&vreg_l1d_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;

14
arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi
View File

@ -1065,9 +1065,6 @@
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
@ -1082,6 +1079,9 @@
};
&pcie4_port0 {
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@ -1099,9 +1099,6 @@
};
&pcie6a {
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
@ -1110,6 +1107,11 @@
status = "okay";
};
&pcie6a_port0 {
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
};
&pcie6a_phy {
vdda-phy-supply = <&vreg_l1d_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;

8
arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi
View File

@ -964,9 +964,6 @@
};
&pcie6a {
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
@ -982,6 +979,11 @@
status = "okay";
};
&pcie6a_port0 {
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
};
&pm8550_gpios {
rtmr0_default: rtmr0-reset-n-active-state {
pins = "gpio10";

6
arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts
View File

@ -1126,9 +1126,6 @@
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
@ -1143,6 +1140,9 @@
};
&pcie4_port0 {
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;

15
arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts
View File

@ -1033,9 +1033,6 @@
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
@ -1050,6 +1047,9 @@
};
&pcie4_port0 {
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@ -1067,10 +1067,6 @@
};
&pcie6a {
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
@ -1086,6 +1082,11 @@
status = "okay";
};
&pcie6a_port0 {
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
};
&pm8550_gpios {
rtmr0_default: rtmr0-reset-n-active-state {
pins = "gpio10";

14
arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts
View File

@ -1131,9 +1131,6 @@
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
@ -1148,6 +1145,9 @@
};
&pcie4_port0 {
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@ -1165,9 +1165,6 @@
};
&pcie6a {
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
@ -1183,6 +1180,11 @@
status = "okay";
};
&pcie6a_port0 {
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
};
&pm8550_pwm {
status = "okay";
};

11
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts
View File

@ -118,6 +118,17 @@
reg = <0x6 0x00000000 0x1 0x00000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
tfa@40000000 {
reg = <0x0 0x40000000 0x0 0x8000000>;
no-map;
};
};
/* Page 27 / DSI to Display */
dp-con {
compatible = "dp-connector";

18
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
View File

@ -879,12 +879,6 @@
};
};
wifi {
wifi_host_wake_l: wifi-host-wake-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-bluetooth {
bt_wake_pin: bt-wake-pin {
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
@ -942,19 +936,7 @@
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
};
};
&sdhci {

8
arch/riscv/include/asm/usercfi.h
View File

@ -39,7 +39,7 @@ void set_active_shstk(struct task_struct *task, unsigned long shstk_addr);
bool is_shstk_enabled(struct task_struct *task);
bool is_shstk_locked(struct task_struct *task);
bool is_shstk_allocated(struct task_struct *task);
void set_shstk_lock(struct task_struct *task);
void set_shstk_lock(struct task_struct *task, bool lock);
void set_shstk_status(struct task_struct *task, bool enable);
unsigned long get_active_shstk(struct task_struct *task);
int restore_user_shstk(struct task_struct *tsk, unsigned long shstk_ptr);
@ -47,7 +47,7 @@ int save_user_shstk(struct task_struct *tsk, unsigned long *saved_shstk_ptr);
bool is_indir_lp_enabled(struct task_struct *task);
bool is_indir_lp_locked(struct task_struct *task);
void set_indir_lp_status(struct task_struct *task, bool enable);
void set_indir_lp_lock(struct task_struct *task);
void set_indir_lp_lock(struct task_struct *task, bool lock);
#define PR_SHADOW_STACK_SUPPORTED_STATUS_MASK (PR_SHADOW_STACK_ENABLE)
@ -69,7 +69,7 @@ void set_indir_lp_lock(struct task_struct *task);
#define is_shstk_allocated(task) false
#define set_shstk_lock(task) do {} while (0)
#define set_shstk_lock(task, lock) do {} while (0)
#define set_shstk_status(task, enable) do {} while (0)
@ -79,7 +79,7 @@ void set_indir_lp_lock(struct task_struct *task);
#define set_indir_lp_status(task, enable) do {} while (0)
#define set_indir_lp_lock(task) do {} while (0)
#define set_indir_lp_lock(task, lock) do {} while (0)
#define restore_user_shstk(tsk, shstk_ptr) -EINVAL

38
arch/riscv/include/uapi/asm/ptrace.h
View File

@ -132,26 +132,28 @@ struct __sc_riscv_cfi_state {
unsigned long ss_ptr; /* shadow stack pointer */
};
#define PTRACE_CFI_LP_EN_BIT 0
#define PTRACE_CFI_LP_LOCK_BIT 1
#define PTRACE_CFI_ELP_BIT 2
#define PTRACE_CFI_SS_EN_BIT 3
#define PTRACE_CFI_SS_LOCK_BIT 4
#define PTRACE_CFI_SS_PTR_BIT 5
#define PTRACE_CFI_BRANCH_LANDING_PAD_EN_BIT 0
#define PTRACE_CFI_BRANCH_LANDING_PAD_LOCK_BIT 1
#define PTRACE_CFI_BRANCH_EXPECTED_LANDING_PAD_BIT 2
#define PTRACE_CFI_SHADOW_STACK_EN_BIT 3
#define PTRACE_CFI_SHADOW_STACK_LOCK_BIT 4
#define PTRACE_CFI_SHADOW_STACK_PTR_BIT 5
#define PTRACE_CFI_LP_EN_STATE _BITUL(PTRACE_CFI_LP_EN_BIT)
#define PTRACE_CFI_LP_LOCK_STATE _BITUL(PTRACE_CFI_LP_LOCK_BIT)
#define PTRACE_CFI_ELP_STATE _BITUL(PTRACE_CFI_ELP_BIT)
#define PTRACE_CFI_SS_EN_STATE _BITUL(PTRACE_CFI_SS_EN_BIT)
#define PTRACE_CFI_SS_LOCK_STATE _BITUL(PTRACE_CFI_SS_LOCK_BIT)
#define PTRACE_CFI_SS_PTR_STATE _BITUL(PTRACE_CFI_SS_PTR_BIT)
#define PTRACE_CFI_BRANCH_LANDING_PAD_EN_STATE _BITUL(PTRACE_CFI_BRANCH_LANDING_PAD_EN_BIT)
#define PTRACE_CFI_BRANCH_LANDING_PAD_LOCK_STATE \
_BITUL(PTRACE_CFI_BRANCH_LANDING_PAD_LOCK_BIT)
#define PTRACE_CFI_BRANCH_EXPECTED_LANDING_PAD_STATE \
_BITUL(PTRACE_CFI_BRANCH_EXPECTED_LANDING_PAD_BIT)
#define PTRACE_CFI_SHADOW_STACK_EN_STATE _BITUL(PTRACE_CFI_SHADOW_STACK_EN_BIT)
#define PTRACE_CFI_SHADOW_STACK_LOCK_STATE _BITUL(PTRACE_CFI_SHADOW_STACK_LOCK_BIT)
#define PTRACE_CFI_SHADOW_STACK_PTR_STATE _BITUL(PTRACE_CFI_SHADOW_STACK_PTR_BIT)
#define PRACE_CFI_STATE_INVALID_MASK ~(PTRACE_CFI_LP_EN_STATE | \
PTRACE_CFI_LP_LOCK_STATE | \
PTRACE_CFI_ELP_STATE | \
PTRACE_CFI_SS_EN_STATE | \
PTRACE_CFI_SS_LOCK_STATE | \
PTRACE_CFI_SS_PTR_STATE)
#define PTRACE_CFI_STATE_INVALID_MASK ~(PTRACE_CFI_BRANCH_LANDING_PAD_EN_STATE | \
PTRACE_CFI_BRANCH_LANDING_PAD_LOCK_STATE | \
PTRACE_CFI_BRANCH_EXPECTED_LANDING_PAD_STATE | \
PTRACE_CFI_SHADOW_STACK_EN_STATE | \
PTRACE_CFI_SHADOW_STACK_LOCK_STATE | \
PTRACE_CFI_SHADOW_STACK_PTR_STATE)
struct __cfi_status {
__u64 cfi_state;

2
arch/riscv/kernel/process.c
View File

@ -160,6 +160,7 @@ void start_thread(struct pt_regs *regs, unsigned long pc,
* clear shadow stack state on exec.
* libc will set it later via prctl.
*/
set_shstk_lock(current, false);
set_shstk_status(current, false);
set_shstk_base(current, 0, 0);
set_active_shstk(current, 0);
@ -167,6 +168,7 @@ void start_thread(struct pt_regs *regs, unsigned long pc,
* disable indirect branch tracking on exec.
* libc will enable it later via prctl.
*/
set_indir_lp_lock(current, false);
set_indir_lp_status(current, false);
#ifdef CONFIG_64BIT

22
arch/riscv/kernel/ptrace.c
View File

@ -303,18 +303,18 @@ static int riscv_cfi_get(struct task_struct *target,
regs = task_pt_regs(target);
if (is_indir_lp_enabled(target)) {
user_cfi.cfi_status.cfi_state |= PTRACE_CFI_LP_EN_STATE;
user_cfi.cfi_status.cfi_state |= PTRACE_CFI_BRANCH_LANDING_PAD_EN_STATE;
user_cfi.cfi_status.cfi_state |= is_indir_lp_locked(target) ?
PTRACE_CFI_LP_LOCK_STATE : 0;
PTRACE_CFI_BRANCH_LANDING_PAD_LOCK_STATE : 0;
user_cfi.cfi_status.cfi_state |= (regs->status & SR_ELP) ?
PTRACE_CFI_ELP_STATE : 0;
PTRACE_CFI_BRANCH_EXPECTED_LANDING_PAD_STATE : 0;
}
if (is_shstk_enabled(target)) {
user_cfi.cfi_status.cfi_state |= (PTRACE_CFI_SS_EN_STATE |
PTRACE_CFI_SS_PTR_STATE);
user_cfi.cfi_status.cfi_state |= (PTRACE_CFI_SHADOW_STACK_EN_STATE |
PTRACE_CFI_SHADOW_STACK_PTR_STATE);
user_cfi.cfi_status.cfi_state |= is_shstk_locked(target) ?
PTRACE_CFI_SS_LOCK_STATE : 0;
PTRACE_CFI_SHADOW_STACK_LOCK_STATE : 0;
user_cfi.shstk_ptr = get_active_shstk(target);
}
@ -349,15 +349,15 @@ static int riscv_cfi_set(struct task_struct *target,
* rsvd field should be set to zero so that if those fields are needed in future
*/
if ((user_cfi.cfi_status.cfi_state &
(PTRACE_CFI_LP_EN_STATE | PTRACE_CFI_LP_LOCK_STATE |
PTRACE_CFI_SS_EN_STATE | PTRACE_CFI_SS_LOCK_STATE)) ||
(user_cfi.cfi_status.cfi_state & PRACE_CFI_STATE_INVALID_MASK))
(PTRACE_CFI_BRANCH_LANDING_PAD_EN_STATE | PTRACE_CFI_BRANCH_LANDING_PAD_LOCK_STATE |
PTRACE_CFI_SHADOW_STACK_EN_STATE | PTRACE_CFI_SHADOW_STACK_LOCK_STATE)) ||
(user_cfi.cfi_status.cfi_state & PTRACE_CFI_STATE_INVALID_MASK))
return -EINVAL;
/* If lpad is enabled on target and ptrace requests to set / clear elp, do that */
if (is_indir_lp_enabled(target)) {
if (user_cfi.cfi_status.cfi_state &
PTRACE_CFI_ELP_STATE) /* set elp state */
PTRACE_CFI_BRANCH_EXPECTED_LANDING_PAD_STATE) /* set elp state */
regs->status |= SR_ELP;
else
regs->status &= ~SR_ELP; /* clear elp state */
@ -365,7 +365,7 @@ static int riscv_cfi_set(struct task_struct *target,
/* If shadow stack enabled on target, set new shadow stack pointer */
if (is_shstk_enabled(target) &&
(user_cfi.cfi_status.cfi_state & PTRACE_CFI_SS_PTR_STATE))
(user_cfi.cfi_status.cfi_state & PTRACE_CFI_SHADOW_STACK_PTR_STATE))
set_active_shstk(target, user_cfi.shstk_ptr);
return 0;

39
arch/riscv/kernel/usercfi.c
View File

@ -74,9 +74,9 @@ void set_shstk_status(struct task_struct *task, bool enable)
csr_write(CSR_ENVCFG, task->thread.envcfg);
}
void set_shstk_lock(struct task_struct *task)
void set_shstk_lock(struct task_struct *task, bool lock)
{
task->thread_info.user_cfi_state.ubcfi_locked = 1;
task->thread_info.user_cfi_state.ubcfi_locked = lock;
}
bool is_indir_lp_enabled(struct task_struct *task)
@ -104,9 +104,9 @@ void set_indir_lp_status(struct task_struct *task, bool enable)
csr_write(CSR_ENVCFG, task->thread.envcfg);
}
void set_indir_lp_lock(struct task_struct *task)
void set_indir_lp_lock(struct task_struct *task, bool lock)
{
task->thread_info.user_cfi_state.ufcfi_locked = 1;
task->thread_info.user_cfi_state.ufcfi_locked = lock;
}
/*
* If size is 0, then to be compatible with regular stack we want it to be as big as
@ -452,28 +452,27 @@ int arch_lock_shadow_stack_status(struct task_struct *task,
!is_shstk_enabled(task) || arg != 0)
return -EINVAL;
set_shstk_lock(task);
set_shstk_lock(task, true);
return 0;
}
int arch_get_indir_br_lp_status(struct task_struct *t, unsigned long __user *status)
int arch_prctl_get_branch_landing_pad_state(struct task_struct *t,
unsigned long __user *state)
{
unsigned long fcfi_status = 0;
if (!is_user_lpad_enabled())
return -EINVAL;
/* indirect branch tracking is enabled on the task or not */
fcfi_status |= (is_indir_lp_enabled(t) ? PR_INDIR_BR_LP_ENABLE : 0);
fcfi_status = (is_indir_lp_enabled(t) ? PR_CFI_ENABLE : PR_CFI_DISABLE);
fcfi_status |= (is_indir_lp_locked(t) ? PR_CFI_LOCK : 0);
return copy_to_user(status, &fcfi_status, sizeof(fcfi_status)) ? -EFAULT : 0;
return copy_to_user(state, &fcfi_status, sizeof(fcfi_status)) ? -EFAULT : 0;
}
int arch_set_indir_br_lp_status(struct task_struct *t, unsigned long status)
int arch_prctl_set_branch_landing_pad_state(struct task_struct *t, unsigned long state)
{
bool enable_indir_lp = false;
if (!is_user_lpad_enabled())
return -EINVAL;
@ -481,28 +480,28 @@ int arch_set_indir_br_lp_status(struct task_struct *t, unsigned long status)
if (is_indir_lp_locked(t))
return -EINVAL;
/* Reject unknown flags */
if (status & ~PR_INDIR_BR_LP_ENABLE)
if (!(state & (PR_CFI_ENABLE | PR_CFI_DISABLE)))
return -EINVAL;
enable_indir_lp = (status & PR_INDIR_BR_LP_ENABLE);
set_indir_lp_status(t, enable_indir_lp);
if (state & PR_CFI_ENABLE && state & PR_CFI_DISABLE)
return -EINVAL;
set_indir_lp_status(t, !!(state & PR_CFI_ENABLE));
return 0;
}
int arch_lock_indir_br_lp_status(struct task_struct *task,
unsigned long arg)
int arch_prctl_lock_branch_landing_pad_state(struct task_struct *task)
{
/*
* If indirect branch tracking is not supported or not enabled on task,
* nothing to lock here
*/
if (!is_user_lpad_enabled() ||
!is_indir_lp_enabled(task) || arg != 0)
!is_indir_lp_enabled(task))
return -EINVAL;
set_indir_lp_lock(task);
set_indir_lp_lock(task, true);
return 0;
}

9
arch/s390/kvm/gaccess.c
View File

@ -1449,7 +1449,7 @@ static int _do_shadow_pte(struct gmap *sg, gpa_t raddr, union pte *ptep_h, union
pgste_set_unlock(ptep_h, pgste);
if (rc)
return rc;
if (!sg->parent)
if (sg->invalidated)
return -EAGAIN;
newpte = _pte(f->pfn, 0, !p, 0);
@ -1479,7 +1479,7 @@ static int _do_shadow_crste(struct gmap *sg, gpa_t raddr, union crste *host, uni
do {
/* _gmap_crstep_xchg_atomic() could have unshadowed this shadow gmap */
if (!sg->parent)
if (sg->invalidated)
return -EAGAIN;
oldcrste = READ_ONCE(*host);
newcrste = _crste_fc1(f->pfn, oldcrste.h.tt, f->writable, !p);
@ -1492,7 +1492,7 @@ static int _do_shadow_crste(struct gmap *sg, gpa_t raddr, union crste *host, uni
if (!newcrste.h.p && !f->writable)
return -EOPNOTSUPP;
} while (!_gmap_crstep_xchg_atomic(sg->parent, host, oldcrste, newcrste, f->gfn, false));
if (!sg->parent)
if (sg->invalidated)
return -EAGAIN;
newcrste = _crste_fc1(f->pfn, oldcrste.h.tt, 0, !p);
@ -1545,7 +1545,7 @@ static int _gaccess_do_shadow(struct kvm_s390_mmu_cache *mc, struct gmap *sg,
entries[i].pfn, i + 1, entries[i].writable);
if (rc)
return rc;
if (!sg->parent)
if (sg->invalidated)
return -EAGAIN;
}
@ -1601,6 +1601,7 @@ again:
scoped_guard(spinlock, &parent->children_lock) {
if (READ_ONCE(sg->parent) != parent)
return -EAGAIN;
sg->invalidated = false;
rc = _gaccess_do_shadow(vcpu->arch.mc, sg, saddr, walk);
}
if (rc == -ENOMEM)

3
arch/s390/kvm/gmap.c
View File

@ -181,6 +181,7 @@ void gmap_remove_child(struct gmap *child)
list_del(&child->list);
child->parent = NULL;
child->invalidated = true;
}
/**
@ -1069,6 +1070,7 @@ static void gmap_unshadow_level(struct gmap *sg, gfn_t r_gfn, int level)
if (level > TABLE_TYPE_PAGE_TABLE)
align = 1UL << (11 * level + _SEGMENT_SHIFT);
kvm_s390_vsie_gmap_notifier(sg, ALIGN_DOWN(gaddr, align), ALIGN(gaddr + 1, align));
sg->invalidated = true;
if (dat_entry_walk(NULL, r_gfn, sg->asce, 0, level, &crstep, &ptep))
return;
if (ptep) {
@ -1174,6 +1176,7 @@ static inline int __gmap_protect_asce_top_level(struct kvm_s390_mmu_cache *mc, s
scoped_guard(spinlock, &parent->children_lock) {
if (READ_ONCE(sg->parent) != parent)
return -EAGAIN;
sg->invalidated = false;
for (i = 0; i < CRST_TABLE_PAGES; i++) {
if (!context->f[i].valid)
continue;

1
arch/s390/kvm/gmap.h
View File

@ -60,6 +60,7 @@ enum gmap_flags {
struct gmap {
unsigned long flags;
unsigned char edat_level;
bool invalidated;
struct kvm *kvm;
union asce asce;
struct list_head list;

1
arch/x86/events/intel/uncore.c
View File

@ -67,6 +67,7 @@ int uncore_die_to_segment(int die)
return bus ? pci_domain_nr(bus) : -EINVAL;
}
/* Note: This API can only be used when NUMA information is available. */
int uncore_device_to_die(struct pci_dev *dev)
{
int node = pcibus_to_node(dev->bus);

17
arch/x86/events/intel/uncore_discovery.c
View File

@ -264,6 +264,7 @@ static int __parse_discovery_table(struct uncore_discovery_domain *domain,
struct uncore_unit_discovery unit;
void __iomem *io_addr;
unsigned long size;
int ret = 0;
int i;
size = UNCORE_DISCOVERY_GLOBAL_MAP_SIZE;
@ -273,21 +274,23 @@ static int __parse_discovery_table(struct uncore_discovery_domain *domain,
/* Read Global Discovery State */
memcpy_fromio(&global, io_addr, sizeof(struct uncore_global_discovery));
iounmap(io_addr);
if (uncore_discovery_invalid_unit(global)) {
pr_info("Invalid Global Discovery State: 0x%llx 0x%llx 0x%llx\n",
global.table1, global.ctl, global.table3);
iounmap(io_addr);
return -EINVAL;
}
iounmap(io_addr);
size = (1 + global.max_units) * global.stride * 8;
io_addr = ioremap(addr, size);
if (!io_addr)
return -ENOMEM;
if (domain->global_init && domain->global_init(global.ctl))
return -ENODEV;
if (domain->global_init && domain->global_init(global.ctl)) {
ret = -ENODEV;
goto out;
}
/* Parsing Unit Discovery State */
for (i = 0; i < global.max_units; i++) {
@ -307,8 +310,10 @@ static int __parse_discovery_table(struct uncore_discovery_domain *domain,
}
*parsed = true;
out:
iounmap(io_addr);
return 0;
return ret;
}
static int parse_discovery_table(struct uncore_discovery_domain *domain,
@ -366,7 +371,7 @@ static bool uncore_discovery_pci(struct uncore_discovery_domain *domain)
(val & UNCORE_DISCOVERY_DVSEC2_BIR_MASK) * UNCORE_DISCOVERY_BIR_STEP;
die = get_device_die_id(dev);
if (die < 0)
if ((die < 0) || (die >= uncore_max_dies()))
continue;
parse_discovery_table(domain, dev, die, bar_offset, &parsed);

61
arch/x86/events/intel/uncore_snbep.c
View File

@ -1459,13 +1459,7 @@ static int snbep_pci2phy_map_init(int devid, int nodeid_loc, int idmap_loc, bool
}
map->pbus_to_dieid[bus] = die_id = uncore_device_to_die(ubox_dev);
raw_spin_unlock(&pci2phy_map_lock);
if (WARN_ON_ONCE(die_id == -1)) {
err = -EINVAL;
break;
}
}
}
@ -6420,7 +6414,7 @@ static void spr_update_device_location(int type_id)
while ((dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, dev)) != NULL) {
die = uncore_device_to_die(dev);
die = uncore_pcibus_to_dieid(dev->bus);
if (die < 0)
continue;
@ -6444,6 +6438,11 @@ static void spr_update_device_location(int type_id)
int spr_uncore_pci_init(void)
{
int ret = snbep_pci2phy_map_init(0x3250, SKX_CPUNODEID, SKX_GIDNIDMAP, true);
if (ret)
return ret;
/*
* The discovery table of UPI on some SPR variant is broken,
* which impacts the detection of both UPI and M3UPI uncore PMON.
@ -6935,34 +6934,34 @@ static struct freerunning_counters dmr_iio_freerunning[] = {
static struct uncore_event_desc dmr_uncore_iio_freerunning_events[] = {
/* ITC Free Running Data BW counter for inbound traffic */
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port0, 0x10, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port1, 0x11, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port2, 0x12, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port3, 0x13, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port4, 0x14, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port5, 0x15, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port6, 0x16, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port7, 0x17, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port0, 0x10, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port1, 0x11, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port2, 0x12, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port3, 0x13, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port4, 0x14, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port5, 0x15, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port6, 0x16, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port7, 0x17, 3.814697266e-6),
/* ITC Free Running BW IN counters */
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port0, 0x20, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port1, 0x21, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port2, 0x22, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port3, 0x23, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port4, 0x24, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port5, 0x25, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port6, 0x26, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port7, 0x27, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port0, 0x20, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port1, 0x21, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port2, 0x22, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port3, 0x23, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port4, 0x24, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port5, 0x25, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port6, 0x26, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port7, 0x27, 3.814697266e-6),
/* ITC Free Running BW OUT counters */
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port0, 0x30, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port1, 0x31, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port2, 0x32, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port3, 0x33, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port4, 0x34, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port5, 0x35, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port6, 0x36, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port7, 0x37, "3.814697266e-6"),
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port0, 0x30, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port1, 0x31, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port2, 0x32, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port3, 0x33, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port4, 0x34, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port5, 0x35, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port6, 0x36, 3.814697266e-6),
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port7, 0x37, 3.814697266e-6),
/* Free Running Clock Counter */
INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x40"),

12
arch/x86/include/uapi/asm/kvm.h
View File

@ -197,13 +197,13 @@ struct kvm_msrs {
__u32 nmsrs; /* number of msrs in entries */
__u32 pad;
struct kvm_msr_entry entries[];
__DECLARE_FLEX_ARRAY(struct kvm_msr_entry, entries);
};
/* for KVM_GET_MSR_INDEX_LIST */
struct kvm_msr_list {
__u32 nmsrs; /* number of msrs in entries */
__u32 indices[];
__DECLARE_FLEX_ARRAY(__u32, indices);
};
/* Maximum size of any access bitmap in bytes */
@ -245,7 +245,7 @@ struct kvm_cpuid_entry {
struct kvm_cpuid {
__u32 nent;
__u32 padding;
struct kvm_cpuid_entry entries[];
__DECLARE_FLEX_ARRAY(struct kvm_cpuid_entry, entries);
};
struct kvm_cpuid_entry2 {
@ -267,7 +267,7 @@ struct kvm_cpuid_entry2 {
struct kvm_cpuid2 {
__u32 nent;
__u32 padding;
struct kvm_cpuid_entry2 entries[];
__DECLARE_FLEX_ARRAY(struct kvm_cpuid_entry2, entries);
};
/* for KVM_GET_PIT and KVM_SET_PIT */
@ -398,7 +398,7 @@ struct kvm_xsave {
* the contents of CPUID leaf 0xD on the host.
*/
__u32 region[1024];
__u32 extra[];
__DECLARE_FLEX_ARRAY(__u32, extra);
};
#define KVM_MAX_XCRS 16
@ -566,7 +566,7 @@ struct kvm_pmu_event_filter {
__u32 fixed_counter_bitmap;
__u32 flags;
__u32 pad[4];
__u64 events[];
__DECLARE_FLEX_ARRAY(__u64, events);
};
#define KVM_PMU_EVENT_ALLOW 0

8
arch/x86/kernel/cpu/mce/amd.c
View File

@ -604,6 +604,14 @@ bool amd_filter_mce(struct mce *m)
enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank);
struct cpuinfo_x86 *c = &boot_cpu_data;
/* Bogus hw errors on Cezanne A0. */
if (c->x86 == 0x19 &&
c->x86_model == 0x50 &&
c->x86_stepping == 0x0) {
if (!(m->status & MCI_STATUS_EN))
return true;
}
/* See Family 17h Models 10h-2Fh Erratum #1114. */
if (c->x86 == 0x17 &&
c->x86_model >= 0x10 && c->x86_model <= 0x2F &&

3
arch/x86/kernel/shstk.c
View File

@ -351,7 +351,8 @@ static int shstk_pop_sigframe(unsigned long *ssp)
need_to_check_vma = PAGE_ALIGN(*ssp) == *ssp;
if (need_to_check_vma)
mmap_read_lock_killable(current->mm);
if (mmap_read_lock_killable(current->mm))
return -EINTR;
err = get_shstk_data(&token_addr, (unsigned long __user *)*ssp);
if (unlikely(err))

6
crypto/af_alg.c
View File

@ -705,8 +705,8 @@ void af_alg_pull_tsgl(struct sock *sk, size_t used, struct scatterlist *dst)
* Assumption: caller created af_alg_count_tsgl(len)
* SG entries in dst.
*/
if (dst) {
/* reassign page to dst after offset */
if (dst && plen) {
/* reassign page to dst */
get_page(page);
sg_set_page(dst + j, page, plen, sg[i].offset);
j++;
@ -1229,6 +1229,8 @@ int af_alg_get_rsgl(struct sock *sk, struct msghdr *msg, int flags,
seglen = min_t(size_t, (maxsize - len),
msg_data_left(msg));
/* Never pin more pages than the remaining RX accounting budget. */
seglen = min_t(size_t, seglen, af_alg_rcvbuf(sk));
if (list_empty(&areq->rsgl_list)) {
rsgl = &areq->first_rsgl;

2
crypto/algif_aead.c
View File

@ -144,7 +144,7 @@ static int _aead_recvmsg(struct socket *sock, struct msghdr *msg,
if (usedpages < outlen) {
size_t less = outlen - usedpages;
if (used < less) {
if (used < less + (ctx->enc ? 0 : as)) {
err = -EINVAL;
goto free;
}

5
crypto/algif_skcipher.c
View File

@ -130,6 +130,11 @@ static int _skcipher_recvmsg(struct socket *sock, struct msghdr *msg,
* full block size buffers.
*/
if (ctx->more || len < ctx->used) {
if (len < bs) {
err = -EINVAL;
goto free;
}
len -= len % bs;
cflags |= CRYPTO_SKCIPHER_REQ_NOTFINAL;
}

8
crypto/asymmetric_keys/x509_cert_parser.c
View File

@ -609,10 +609,10 @@ int x509_process_extension(void *context, size_t hdrlen,
* 0x04 is where keyCertSign lands in this bit string
* 0x80 is where digitalSignature lands in this bit string
*/
if (v[0] != ASN1_BTS)
return -EBADMSG;
if (vlen < 4)
return -EBADMSG;
if (v[0] != ASN1_BTS)
return -EBADMSG;
if (v[2] >= 8)
return -EBADMSG;
if (v[3] & 0x80)
@ -645,10 +645,10 @@ int x509_process_extension(void *context, size_t hdrlen,
* (Expect 0xFF if the CA is TRUE)
* vlen should match the entire extension size
*/
if (v[0] != (ASN1_CONS_BIT | ASN1_SEQ))
return -EBADMSG;
if (vlen < 2)
return -EBADMSG;
if (v[0] != (ASN1_CONS_BIT | ASN1_SEQ))
return -EBADMSG;
if (v[1] != vlen - 2)
return -EBADMSG;
/* Empty SEQUENCE means CA:FALSE (default value omitted per DER) */

1
drivers/accel/ethosu/Kconfig
View File

@ -4,6 +4,7 @@ config DRM_ACCEL_ARM_ETHOSU
tristate "Arm Ethos-U65/U85 NPU"
depends on HAS_IOMEM
depends on DRM_ACCEL
depends on ARM || ARM64 || COMPILE_TEST
select DRM_GEM_DMA_HELPER
select DRM_SCHED
select GENERIC_ALLOCATOR

14
drivers/ata/ahci.c
View File

@ -68,6 +68,7 @@ enum board_ids {
/* board IDs for specific chipsets in alphabetical order */
board_ahci_al,
board_ahci_avn,
board_ahci_jmb585,
board_ahci_mcp65,
board_ahci_mcp77,
board_ahci_mcp89,
@ -212,6 +213,15 @@ static const struct ata_port_info ahci_port_info[] = {
.udma_mask = ATA_UDMA6,
.port_ops = &ahci_avn_ops,
},
/* JMicron JMB582/585: 64-bit DMA is broken, force 32-bit */
[board_ahci_jmb585] = {
AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR |
AHCI_HFLAG_32BIT_ONLY),
.flags = AHCI_FLAG_COMMON,
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
.port_ops = &ahci_ops,
},
[board_ahci_mcp65] = {
AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
AHCI_HFLAG_YES_NCQ),
@ -439,6 +449,10 @@ static const struct pci_device_id ahci_pci_tbl[] = {
/* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */
{ PCI_VDEVICE(INTEL, 0x4b63), board_ahci_pcs_quirk }, /* Elkhart Lake AHCI */
/* JMicron JMB582/585: force 32-bit DMA (broken 64-bit implementation) */
{ PCI_VDEVICE(JMICRON, 0x0582), board_ahci_jmb585 },
{ PCI_VDEVICE(JMICRON, 0x0585), board_ahci_jmb585 },
/* JMicron 360/1/3/5/6, match class to avoid IDE function */
{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },

4
drivers/base/class.c
View File

@ -127,7 +127,7 @@ static const struct kobj_type class_ktype = {
};
int class_create_file_ns(const struct class *cls, const struct class_attribute *attr,
const void *ns)
const struct ns_common *ns)
{
struct subsys_private *sp = class_to_subsys(cls);
int error;
@ -143,7 +143,7 @@ int class_create_file_ns(const struct class *cls, const struct class_attribute *
EXPORT_SYMBOL_GPL(class_create_file_ns);
void class_remove_file_ns(const struct class *cls, const struct class_attribute *attr,
const void *ns)
const struct ns_common *ns)
{
struct subsys_private *sp = class_to_subsys(cls);

7
drivers/base/core.c
View File

@ -2570,15 +2570,14 @@ static void device_release(struct kobject *kobj)
kfree(p);
}
static const void *device_namespace(const struct kobject *kobj)
static const struct ns_common *device_namespace(const struct kobject *kobj)
{
const struct device *dev = kobj_to_dev(kobj);
const void *ns = NULL;
if (dev->class && dev->class->namespace)
ns = dev->class->namespace(dev);
return dev->class->namespace(dev);
return ns;
return NULL;
}
static void device_get_ownership(const struct kobject *kobj, kuid_t *uid, kgid_t *gid)

6
drivers/edac/edac_mc.c
View File

@ -369,13 +369,13 @@ struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num,
if (!mci->layers)
goto error;
mci->dev.release = mci_release;
device_initialize(&mci->dev);
mci->pvt_info = kzalloc(sz_pvt, GFP_KERNEL);
if (!mci->pvt_info)
goto error;
mci->dev.release = mci_release;
device_initialize(&mci->dev);
/* setup index and various internal pointers */
mci->mc_idx = mc_num;
mci->tot_dimms = tot_dimms;

2
drivers/firmware/efi/efi-init.c
View File

@ -60,7 +60,7 @@ extern __weak const efi_config_table_type_t efi_arch_tables[];
* x86 defines its own instance of sysfb_primary_display and uses
* it even without EFI, everything else can get them from here.
*/
#if !defined(CONFIG_X86) && (defined(CONFIG_SYSFB) || defined(CONFIG_EFI_EARLYCON)) || defined(CONFIG_FIRMWARE_EDID)
#if !defined(CONFIG_X86) && (defined(CONFIG_SYSFB) || defined(CONFIG_EFI_EARLYCON) || defined(CONFIG_FIRMWARE_EDID))
struct sysfb_display_info sysfb_primary_display __section(".data");
EXPORT_SYMBOL_GPL(sysfb_primary_display);
#endif

10
drivers/firmware/microchip/mpfs-auto-update.c
View File

@ -113,10 +113,6 @@ static enum fw_upload_err mpfs_auto_update_prepare(struct fw_upload *fw_uploader
* be added here.
*/
priv->flash = mpfs_sys_controller_get_flash(priv->sys_controller);
if (!priv->flash)
return FW_UPLOAD_ERR_HW_ERROR;
erase_size = round_up(erase_size, (u64)priv->flash->erasesize);
/*
@ -427,6 +423,12 @@ static int mpfs_auto_update_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(priv->sys_controller),
"Could not register as a sub device of the system controller\n");
priv->flash = mpfs_sys_controller_get_flash(priv->sys_controller);
if (IS_ERR_OR_NULL(priv->flash)) {
dev_dbg(dev, "No flash connected to the system controller, auto-update not supported\n");
return -ENODEV;
}
priv->dev = dev;
platform_set_drvdata(pdev, priv);

7
drivers/firmware/thead,th1520-aon.c
View File

@ -170,10 +170,9 @@ int th1520_aon_power_update(struct th1520_aon_chan *aon_chan, u16 rsrc,
hdr->func = TH1520_AON_PM_FUNC_SET_RESOURCE_POWER_MODE;
hdr->size = TH1520_AON_RPC_MSG_NUM;
RPC_SET_BE16(&msg.resource, 0, rsrc);
RPC_SET_BE16(&msg.resource, 2,
(power_on ? TH1520_AON_PM_PW_MODE_ON :
TH1520_AON_PM_PW_MODE_OFF));
msg.resource = cpu_to_be16(rsrc);
msg.mode = cpu_to_be16(power_on ? TH1520_AON_PM_PW_MODE_ON :
TH1520_AON_PM_PW_MODE_OFF);
ret = th1520_aon_call_rpc(aon_chan, &msg);
if (ret)

2
drivers/gpio/gpio-bd72720.c
View File

@ -256,6 +256,8 @@ static int gpo_bd72720_probe(struct platform_device *pdev)
g->dev = dev;
g->chip.parent = parent;
g->regmap = dev_get_regmap(parent, NULL);
if (!g->regmap)
return -ENODEV;
return devm_gpiochip_add_data(dev, &g->chip, g);
}

4
drivers/gpio/gpio-tegra.c
View File

@ -595,7 +595,7 @@ static void tegra_gpio_irq_release_resources(struct irq_data *d)
struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
gpiochip_relres_irq(chip, d->hwirq);
tegra_gpio_enable(tgi, d->hwirq);
tegra_gpio_disable(tgi, d->hwirq);
}
static void tegra_gpio_irq_print_chip(struct irq_data *d, struct seq_file *s)
@ -698,7 +698,7 @@ static int tegra_gpio_probe(struct platform_device *pdev)
tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
if (!tgi)
return -ENODEV;
return -ENOMEM;
tgi->soc = of_device_get_match_data(&pdev->dev);
tgi->dev = &pdev->dev;

30
drivers/gpu/drm/i915/display/intel_psr.c
View File

@ -2678,9 +2678,9 @@ static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state,
static void clip_area_update(struct drm_rect *overlap_damage_area,
struct drm_rect *damage_area,
struct drm_rect *pipe_src)
struct drm_rect *display_area)
{
if (!drm_rect_intersect(damage_area, pipe_src))
if (!drm_rect_intersect(damage_area, display_area))
return;
if (overlap_damage_area->y1 == -1) {
@ -2731,6 +2731,7 @@ static bool intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_st
static void
intel_psr2_sel_fetch_et_alignment(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct drm_rect *display_area,
bool *cursor_in_su_area)
{
struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
@ -2758,7 +2759,7 @@ intel_psr2_sel_fetch_et_alignment(struct intel_atomic_state *state,
continue;
clip_area_update(&crtc_state->psr2_su_area, &new_plane_state->uapi.dst,
&crtc_state->pipe_src);
display_area);
*cursor_in_su_area = true;
}
}
@ -2855,6 +2856,12 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
struct intel_plane_state *new_plane_state, *old_plane_state;
struct intel_plane *plane;
struct drm_rect display_area = {
.x1 = 0,
.y1 = 0,
.x2 = crtc_state->hw.adjusted_mode.crtc_hdisplay,
.y2 = crtc_state->hw.adjusted_mode.crtc_vdisplay,
};
bool full_update = false, su_area_changed;
int i, ret;
@ -2868,7 +2875,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
crtc_state->psr2_su_area.x1 = 0;
crtc_state->psr2_su_area.y1 = -1;
crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state->pipe_src);
crtc_state->psr2_su_area.x2 = drm_rect_width(&display_area);
crtc_state->psr2_su_area.y2 = -1;
/*
@ -2906,14 +2913,14 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
damaged_area.y1 = old_plane_state->uapi.dst.y1;
damaged_area.y2 = old_plane_state->uapi.dst.y2;
clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
&crtc_state->pipe_src);
&display_area);
}
if (new_plane_state->uapi.visible) {
damaged_area.y1 = new_plane_state->uapi.dst.y1;
damaged_area.y2 = new_plane_state->uapi.dst.y2;
clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
&crtc_state->pipe_src);
&display_area);
}
continue;
} else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) {
@ -2921,7 +2928,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
damaged_area.y1 = new_plane_state->uapi.dst.y1;
damaged_area.y2 = new_plane_state->uapi.dst.y2;
clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
&crtc_state->pipe_src);
&display_area);
continue;
}
@ -2937,7 +2944,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1;
damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1;
clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &crtc_state->pipe_src);
clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &display_area);
}
/*
@ -2972,7 +2979,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
* cursor is added into affected planes even when
* cursor is not updated by itself.
*/
intel_psr2_sel_fetch_et_alignment(state, crtc, &cursor_in_su_area);
intel_psr2_sel_fetch_et_alignment(state, crtc, &display_area,
&cursor_in_su_area);
su_area_changed = intel_psr2_sel_fetch_pipe_alignment(crtc_state);
@ -3048,8 +3056,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
skip_sel_fetch_set_loop:
if (full_update)
clip_area_update(&crtc_state->psr2_su_area, &crtc_state->pipe_src,
&crtc_state->pipe_src);
clip_area_update(&crtc_state->psr2_su_area, &display_area,
&display_area);
psr2_man_trk_ctl_calc(crtc_state, full_update);
crtc_state->pipe_srcsz_early_tpt =

2
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
View File

@ -896,7 +896,7 @@ static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle)
rcu_read_lock();
vma = radix_tree_lookup(&eb->gem_context->handles_vma, handle);
if (likely(vma && vma->vm == vm))
if (likely(vma))
vma = i915_vma_tryget(vma);
else
vma = NULL;

26
drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
View File

@ -148,10 +148,12 @@ static void heartbeat(struct work_struct *wrk)
/* Just in case everything has gone horribly wrong, give it a kick */
intel_engine_flush_submission(engine);
rq = engine->heartbeat.systole;
if (rq && i915_request_completed(rq)) {
i915_request_put(rq);
engine->heartbeat.systole = NULL;
rq = xchg(&engine->heartbeat.systole, NULL);
if (rq) {
if (i915_request_completed(rq))
i915_request_put(rq);
else
engine->heartbeat.systole = rq;
}
if (!intel_engine_pm_get_if_awake(engine))
@ -232,8 +234,11 @@ static void heartbeat(struct work_struct *wrk)
unlock:
mutex_unlock(&ce->timeline->mutex);
out:
if (!engine->i915->params.enable_hangcheck || !next_heartbeat(engine))
i915_request_put(fetch_and_zero(&engine->heartbeat.systole));
if (!engine->i915->params.enable_hangcheck || !next_heartbeat(engine)) {
rq = xchg(&engine->heartbeat.systole, NULL);
if (rq)
i915_request_put(rq);
}
intel_engine_pm_put(engine);
}
@ -247,8 +252,13 @@ void intel_engine_unpark_heartbeat(struct intel_engine_cs *engine)
void intel_engine_park_heartbeat(struct intel_engine_cs *engine)
{
if (cancel_delayed_work(&engine->heartbeat.work))
i915_request_put(fetch_and_zero(&engine->heartbeat.systole));
if (cancel_delayed_work(&engine->heartbeat.work)) {
struct i915_request *rq;
rq = xchg(&engine->heartbeat.systole, NULL);
if (rq)
i915_request_put(rq);
}
}
void intel_gt_unpark_heartbeats(struct intel_gt *gt)

3
drivers/gpu/drm/vc4/vc4_bo.c
View File

@ -738,12 +738,15 @@ static int vc4_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct
return -EINVAL;
}
mutex_lock(&bo->madv_lock);
if (bo->madv != VC4_MADV_WILLNEED) {
DRM_DEBUG("mmapping of %s BO not allowed\n",
bo->madv == VC4_MADV_DONTNEED ?
"purgeable" : "purged");
mutex_unlock(&bo->madv_lock);
return -EINVAL;
}
mutex_unlock(&bo->madv_lock);
return drm_gem_dma_mmap(&bo->base, vma);
}

19
drivers/gpu/drm/vc4/vc4_gem.c
View File

@ -62,6 +62,7 @@ vc4_free_hang_state(struct drm_device *dev, struct vc4_hang_state *state)
for (i = 0; i < state->user_state.bo_count; i++)
drm_gem_object_put(state->bo[i]);
kfree(state->bo);
kfree(state);
}
@ -170,10 +171,8 @@ vc4_save_hang_state(struct drm_device *dev)
spin_lock_irqsave(&vc4->job_lock, irqflags);
exec[0] = vc4_first_bin_job(vc4);
exec[1] = vc4_first_render_job(vc4);
if (!exec[0] && !exec[1]) {
spin_unlock_irqrestore(&vc4->job_lock, irqflags);
return;
}
if (!exec[0] && !exec[1])
goto err_free_state;
/* Get the bos from both binner and renderer into hang state. */
state->bo_count = 0;
@ -190,10 +189,8 @@ vc4_save_hang_state(struct drm_device *dev)
kernel_state->bo = kzalloc_objs(*kernel_state->bo, state->bo_count,
GFP_ATOMIC);
if (!kernel_state->bo) {
spin_unlock_irqrestore(&vc4->job_lock, irqflags);
return;
}
if (!kernel_state->bo)
goto err_free_state;
k = 0;
for (i = 0; i < 2; i++) {
@ -285,6 +282,12 @@ vc4_save_hang_state(struct drm_device *dev)
vc4->hang_state = kernel_state;
spin_unlock_irqrestore(&vc4->job_lock, irqflags);
}
return;
err_free_state:
spin_unlock_irqrestore(&vc4->job_lock, irqflags);
kfree(kernel_state);
}
static void

1
drivers/gpu/drm/vc4/vc4_v3d.c
View File

@ -481,6 +481,7 @@ static int vc4_v3d_bind(struct device *dev, struct device *master, void *data)
pm_runtime_use_autosuspend(dev);
pm_runtime_set_autosuspend_delay(dev, 40); /* a little over 2 frames. */
pm_runtime_put_autosuspend(dev);
return 0;

3
drivers/gpu/drm/xe/xe_hw_engine.c
View File

@ -595,9 +595,8 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
maxcnt *= maxcnt_units_ns;
if (xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {
idledly = DIV_ROUND_CLOSEST(((maxcnt - 1) * maxcnt_units_ns),
idledly = DIV_ROUND_CLOSEST(((maxcnt - 1) * 1000),
idledly_units_ps);
idledly = DIV_ROUND_CLOSEST(idledly, 1000);
xe_mmio_write32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base), idledly);
}
}

3
drivers/hid/amd-sfh-hid/amd_sfh_pcie.c
View File

@ -413,7 +413,8 @@ static void sfh_init_work(struct work_struct *work)
rc = amd_sfh_hid_client_init(mp2);
if (rc) {
amd_sfh_clear_intr(mp2);
dev_err(&pdev->dev, "amd_sfh_hid_client_init failed err %d\n", rc);
if (rc != -EOPNOTSUPP)
dev_err(&pdev->dev, "amd_sfh_hid_client_init failed err %d\n", rc);
return;
}

6
drivers/hid/hid-debug.c
View File

@ -990,6 +990,9 @@ static const struct hid_usage_entry hid_usage_table[] = {
{ 0x0c, 0x01c9, "ALContactSync" },
{ 0x0c, 0x01ca, "ALNavigation" },
{ 0x0c, 0x01cb, "ALContextawareDesktopAssistant" },
{ 0x0c, 0x01cc, "ALActionOnSelection" },
{ 0x0c, 0x01cd, "ALContextualInsertion" },
{ 0x0c, 0x01ce, "ALContextualQuery" },
{ 0x0c, 0x0200, "GenericGUIApplicationControls" },
{ 0x0c, 0x0201, "ACNew" },
{ 0x0c, 0x0202, "ACOpen" },
@ -3375,6 +3378,9 @@ static const char *keys[KEY_MAX + 1] = {
[KEY_BRIGHTNESS_MIN] = "BrightnessMin",
[KEY_BRIGHTNESS_MAX] = "BrightnessMax",
[KEY_BRIGHTNESS_AUTO] = "BrightnessAuto",
[KEY_ACTION_ON_SELECTION] = "ActionOnSelection",
[KEY_CONTEXTUAL_INSERT] = "ContextualInsert",
[KEY_CONTEXTUAL_QUERY] = "ContextualQuery",
[KEY_KBDINPUTASSIST_PREV] = "KbdInputAssistPrev",
[KEY_KBDINPUTASSIST_NEXT] = "KbdInputAssistNext",
[KEY_KBDINPUTASSIST_PREVGROUP] = "KbdInputAssistPrevGroup",

7
drivers/hid/hid-ids.h
View File

@ -22,6 +22,9 @@
#define USB_DEVICE_ID_3M2256 0x0502
#define USB_DEVICE_ID_3M3266 0x0506
#define USB_VENDOR_ID_8BITDO 0x2dc8
#define USB_DEVICE_ID_8BITDO_PRO_3 0x6009
#define USB_VENDOR_ID_A4TECH 0x09da
#define USB_DEVICE_ID_A4TECH_WCP32PU 0x0006
#define USB_DEVICE_ID_A4TECH_X5_005D 0x000a
@ -1471,6 +1474,10 @@
#define USB_VENDOR_ID_VTL 0x0306
#define USB_DEVICE_ID_VTL_MULTITOUCH_FF3F 0xff3f
#define USB_VENDOR_ID_VXE 0x3554
#define USB_DEVICE_ID_VXE_DRAGONFLY_R1_PRO_DONGLE 0xf58a
#define USB_DEVICE_ID_VXE_DRAGONFLY_R1_PRO_WIRED 0xf58c
#define USB_VENDOR_ID_WACOM 0x056a
#define USB_DEVICE_ID_WACOM_GRAPHIRE_BLUETOOTH 0x81
#define USB_DEVICE_ID_WACOM_INTUOS4_BLUETOOTH 0x00BD

3
drivers/hid/hid-input.c
View File

@ -1227,6 +1227,9 @@ static void hidinput_configure_usage(struct hid_input *hidinput, struct hid_fiel
case 0x1bc: map_key_clear(KEY_MESSENGER); break;
case 0x1bd: map_key_clear(KEY_INFO); break;
case 0x1cb: map_key_clear(KEY_ASSISTANT); break;
case 0x1cc: map_key_clear(KEY_ACTION_ON_SELECTION); break;
case 0x1cd: map_key_clear(KEY_CONTEXTUAL_INSERT); break;
case 0x1ce: map_key_clear(KEY_CONTEXTUAL_QUERY); break;
case 0x201: map_key_clear(KEY_NEW); break;
case 0x202: map_key_clear(KEY_OPEN); break;
case 0x203: map_key_clear(KEY_CLOSE); break;

2
drivers/hid/hid-kysona.c
View File

@ -272,6 +272,8 @@ static void kysona_remove(struct hid_device *hdev)
static const struct hid_device_id kysona_devices[] = {
{ HID_USB_DEVICE(USB_VENDOR_ID_KYSONA, USB_DEVICE_ID_KYSONA_M600_DONGLE) },
{ HID_USB_DEVICE(USB_VENDOR_ID_KYSONA, USB_DEVICE_ID_KYSONA_M600_WIRED) },
{ HID_USB_DEVICE(USB_VENDOR_ID_VXE, USB_DEVICE_ID_VXE_DRAGONFLY_R1_PRO_DONGLE) },
{ HID_USB_DEVICE(USB_VENDOR_ID_VXE, USB_DEVICE_ID_VXE_DRAGONFLY_R1_PRO_WIRED) },
{ }
};
MODULE_DEVICE_TABLE(hid, kysona_devices);

1
drivers/hid/hid-quirks.c
View File

@ -25,6 +25,7 @@
*/
static const struct hid_device_id hid_quirks[] = {
{ HID_USB_DEVICE(USB_VENDOR_ID_8BITDO, USB_DEVICE_ID_8BITDO_PRO_3), HID_QUIRK_ALWAYS_POLL },
{ HID_USB_DEVICE(USB_VENDOR_ID_AASHIMA, USB_DEVICE_ID_AASHIMA_GAMEPAD), HID_QUIRK_BADPAD },
{ HID_USB_DEVICE(USB_VENDOR_ID_AASHIMA, USB_DEVICE_ID_AASHIMA_PREDATOR), HID_QUIRK_BADPAD },
{ HID_USB_DEVICE(USB_VENDOR_ID_ADATA_XPG, USB_VENDOR_ID_ADATA_XPG_WL_GAMING_MOUSE), HID_QUIRK_ALWAYS_POLL },

2
drivers/hid/hid-roccat.c
View File

@ -257,6 +257,7 @@ int roccat_report_event(int minor, u8 const *data)
if (!new_value)
return -ENOMEM;
mutex_lock(&device->readers_lock);
mutex_lock(&device->cbuf_lock);
report = &device->cbuf[device->cbuf_end];
@ -279,6 +280,7 @@ int roccat_report_event(int minor, u8 const *data)
}
mutex_unlock(&device->cbuf_lock);
mutex_unlock(&device->readers_lock);
wake_up_interruptible(&device->wait);
return 0;

7
drivers/hid/intel-thc-hid/intel-quicki2c/pci-quicki2c.c
View File

@ -26,6 +26,11 @@ static struct quicki2c_ddata ptl_ddata = {
.max_interrupt_delay = MAX_RX_INTERRUPT_DELAY,
};
static struct quicki2c_ddata nvl_ddata = {
.max_detect_size = MAX_RX_DETECT_SIZE_NVL,
.max_interrupt_delay = MAX_RX_INTERRUPT_DELAY,
};
/* THC QuickI2C ACPI method to get device properties */
/* HIDI2C device method */
static guid_t i2c_hid_guid =
@ -1032,6 +1037,8 @@ static const struct pci_device_id quicki2c_pci_tbl[] = {
{ PCI_DEVICE_DATA(INTEL, THC_PTL_U_DEVICE_ID_I2C_PORT2, &ptl_ddata) },
{ PCI_DEVICE_DATA(INTEL, THC_WCL_DEVICE_ID_I2C_PORT1, &ptl_ddata) },
{ PCI_DEVICE_DATA(INTEL, THC_WCL_DEVICE_ID_I2C_PORT2, &ptl_ddata) },
{ PCI_DEVICE_DATA(INTEL, THC_NVL_H_DEVICE_ID_I2C_PORT1, &nvl_ddata) },
{ PCI_DEVICE_DATA(INTEL, THC_NVL_H_DEVICE_ID_I2C_PORT2, &nvl_ddata) },
{ }
};
MODULE_DEVICE_TABLE(pci, quicki2c_pci_tbl);

4
drivers/hid/intel-thc-hid/intel-quicki2c/quicki2c-dev.h
View File

@ -15,6 +15,8 @@
#define PCI_DEVICE_ID_INTEL_THC_PTL_U_DEVICE_ID_I2C_PORT2 0xE44A
#define PCI_DEVICE_ID_INTEL_THC_WCL_DEVICE_ID_I2C_PORT1 0x4D48
#define PCI_DEVICE_ID_INTEL_THC_WCL_DEVICE_ID_I2C_PORT2 0x4D4A
#define PCI_DEVICE_ID_INTEL_THC_NVL_H_DEVICE_ID_I2C_PORT1 0xD348
#define PCI_DEVICE_ID_INTEL_THC_NVL_H_DEVICE_ID_I2C_PORT2 0xD34A
/* Packet size value, the unit is 16 bytes */
#define MAX_PACKET_SIZE_VALUE_LNL 256
@ -40,6 +42,8 @@
/* PTL Max packet size detection capability is 255 Bytes */
#define MAX_RX_DETECT_SIZE_PTL 255
/* NVL Max packet size detection capability is 64K Bytes */
#define MAX_RX_DETECT_SIZE_NVL 65535
/* Max interrupt delay capability is 2.56ms */
#define MAX_RX_INTERRUPT_DELAY 256

6
drivers/hid/intel-thc-hid/intel-quickspi/pci-quickspi.c
View File

@ -37,6 +37,10 @@ struct quickspi_driver_data arl = {
.max_packet_size_value = MAX_PACKET_SIZE_VALUE_MTL,
};
struct quickspi_driver_data nvl = {
.max_packet_size_value = MAX_PACKET_SIZE_VALUE_LNL,
};
/* THC QuickSPI ACPI method to get device properties */
/* HIDSPI Method: {6e2ac436-0fcf-41af-a265-b32a220dcfab} */
static guid_t hidspi_guid =
@ -982,6 +986,8 @@ static const struct pci_device_id quickspi_pci_tbl[] = {
{PCI_DEVICE_DATA(INTEL, THC_WCL_DEVICE_ID_SPI_PORT2, &ptl), },
{PCI_DEVICE_DATA(INTEL, THC_ARL_DEVICE_ID_SPI_PORT1, &arl), },
{PCI_DEVICE_DATA(INTEL, THC_ARL_DEVICE_ID_SPI_PORT2, &arl), },
{PCI_DEVICE_DATA(INTEL, THC_NVL_H_DEVICE_ID_SPI_PORT1, &nvl), },
{PCI_DEVICE_DATA(INTEL, THC_NVL_H_DEVICE_ID_SPI_PORT2, &nvl), },
{}
};
MODULE_DEVICE_TABLE(pci, quickspi_pci_tbl);

2
drivers/hid/intel-thc-hid/intel-quickspi/quickspi-dev.h
View File

@ -23,6 +23,8 @@
#define PCI_DEVICE_ID_INTEL_THC_WCL_DEVICE_ID_SPI_PORT2 0x4D4B
#define PCI_DEVICE_ID_INTEL_THC_ARL_DEVICE_ID_SPI_PORT1 0x7749
#define PCI_DEVICE_ID_INTEL_THC_ARL_DEVICE_ID_SPI_PORT2 0x774B
#define PCI_DEVICE_ID_INTEL_THC_NVL_H_DEVICE_ID_SPI_PORT1 0xD349
#define PCI_DEVICE_ID_INTEL_THC_NVL_H_DEVICE_ID_SPI_PORT2 0xD34B
/* HIDSPI special ACPI parameters DSM methods */
#define ACPI_QUICKSPI_REVISION_NUM 2

15
drivers/hv/mshv_root_main.c
View File

@ -630,7 +630,7 @@ static bool mshv_handle_gpa_intercept(struct mshv_vp *vp)
{
struct mshv_partition *p = vp->vp_partition;
struct mshv_mem_region *region;
bool ret;
bool ret = false;
u64 gfn;
#if defined(CONFIG_X86_64)
struct hv_x64_memory_intercept_message *msg =
@ -641,6 +641,8 @@ static bool mshv_handle_gpa_intercept(struct mshv_vp *vp)
(struct hv_arm64_memory_intercept_message *)
vp->vp_intercept_msg_page->u.payload;
#endif
enum hv_intercept_access_type access_type =
msg->header.intercept_access_type;
gfn = HVPFN_DOWN(msg->guest_physical_address);
@ -648,12 +650,19 @@ static bool mshv_handle_gpa_intercept(struct mshv_vp *vp)
if (!region)
return false;
if (access_type == HV_INTERCEPT_ACCESS_WRITE &&
!(region->hv_map_flags & HV_MAP_GPA_WRITABLE))
goto put_region;
if (access_type == HV_INTERCEPT_ACCESS_EXECUTE &&
!(region->hv_map_flags & HV_MAP_GPA_EXECUTABLE))
goto put_region;
/* Only movable memory ranges are supported for GPA intercepts */
if (region->mreg_type == MSHV_REGION_TYPE_MEM_MOVABLE)
ret = mshv_region_handle_gfn_fault(region, gfn);
else
ret = false;
put_region:
mshv_region_put(region);
return ret;

2
drivers/i2c/busses/i2c-imx.c
View File

@ -401,7 +401,7 @@ static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx)
static int i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, dma_addr_t phy_addr)
{
struct imx_i2c_dma *dma;
struct dma_slave_config dma_sconfig;
struct dma_slave_config dma_sconfig = {};
struct device *dev = i2c_imx->adapter.dev.parent;
int ret;

5
drivers/infiniband/core/device.c
View File

@ -509,12 +509,13 @@ static int ib_device_uevent(const struct device *device,
return 0;
}
static const void *net_namespace(const struct device *d)
static const struct ns_common *net_namespace(const struct device *d)
{
const struct ib_core_device *coredev =
container_of(d, struct ib_core_device, dev);
struct net *net = read_pnet(&coredev->rdma_net);
return read_pnet(&coredev->rdma_net);
return net ? to_ns_common(net) : NULL;
}
static struct class ib_class = {

7
drivers/infiniband/ulp/srp/ib_srp.c
View File

@ -43,6 +43,7 @@
#include <linux/jiffies.h>
#include <linux/lockdep.h>
#include <linux/inet.h>
#include <net/net_namespace.h>
#include <rdma/ib_cache.h>
#include <linux/atomic.h>
@ -1048,7 +1049,7 @@ static void srp_remove_target(struct srp_target_port *target)
scsi_remove_host(target->scsi_host);
srp_stop_rport_timers(target->rport);
srp_disconnect_target(target);
kobj_ns_drop(KOBJ_NS_TYPE_NET, target->net);
kobj_ns_drop(KOBJ_NS_TYPE_NET, to_ns_common(target->net));
for (i = 0; i < target->ch_count; i++) {
ch = &target->ch[i];
srp_free_ch_ib(target, ch);
@ -3713,7 +3714,7 @@ static ssize_t add_target_store(struct device *dev,
target = host_to_target(target_host);
target->net = kobj_ns_grab_current(KOBJ_NS_TYPE_NET);
target->net = to_net_ns(kobj_ns_grab_current(KOBJ_NS_TYPE_NET));
target->io_class = SRP_REV16A_IB_IO_CLASS;
target->scsi_host = target_host;
target->srp_host = host;
@ -3905,7 +3906,7 @@ put:
* earlier in this function.
*/
if (target->state != SRP_TARGET_REMOVED)
kobj_ns_drop(KOBJ_NS_TYPE_NET, target->net);
kobj_ns_drop(KOBJ_NS_TYPE_NET, to_ns_common(target->net));
scsi_host_put(target->scsi_host);
}

35
drivers/input/misc/uinput.c
View File

@ -25,8 +25,10 @@
#include <linux/module.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/lockdep.h>
#include <linux/miscdevice.h>
#include <linux/overflow.h>
#include <linux/spinlock.h>
#include <linux/input/mt.h>
#include "../input-compat.h"
@ -57,6 +59,7 @@ struct uinput_device {
struct input_dev *dev;
struct mutex mutex;
enum uinput_state state;
spinlock_t state_lock;
wait_queue_head_t waitq;
unsigned char ready;
unsigned char head;
@ -75,6 +78,8 @@ static int uinput_dev_event(struct input_dev *dev,
struct uinput_device *udev = input_get_drvdata(dev);
struct timespec64 ts;
lockdep_assert_held(&dev->event_lock);
ktime_get_ts64(&ts);
udev->buff[udev->head] = (struct input_event) {
@ -146,27 +151,26 @@ static void uinput_request_release_slot(struct uinput_device *udev,
static int uinput_request_send(struct uinput_device *udev,
struct uinput_request *request)
{
int retval;
unsigned long flags;
int retval = 0;
retval = mutex_lock_interruptible(&udev->mutex);
if (retval)
return retval;
spin_lock(&udev->state_lock);
if (udev->state != UIST_CREATED) {
retval = -ENODEV;
goto out;
}
init_completion(&request->done);
/*
* Tell our userspace application about this new request
* by queueing an input event.
*/
spin_lock_irqsave(&udev->dev->event_lock, flags);
uinput_dev_event(udev->dev, EV_UINPUT, request->code, request->id);
spin_unlock_irqrestore(&udev->dev->event_lock, flags);
out:
mutex_unlock(&udev->mutex);
spin_unlock(&udev->state_lock);
return retval;
}
@ -175,6 +179,13 @@ static int uinput_request_submit(struct uinput_device *udev,
{
int retval;
/*
* Initialize completion before allocating the request slot.
* Once the slot is allocated, uinput_flush_requests() may
* complete it at any time, so it must be initialized first.
*/
init_completion(&request->done);
retval = uinput_request_reserve_slot(udev, request);
if (retval)
return retval;
@ -289,7 +300,14 @@ static void uinput_destroy_device(struct uinput_device *udev)
struct input_dev *dev = udev->dev;
enum uinput_state old_state = udev->state;
/*
* Update state under state_lock so that concurrent
* uinput_request_send() sees the state change before we
* flush pending requests and tear down the device.
*/
spin_lock(&udev->state_lock);
udev->state = UIST_NEW_DEVICE;
spin_unlock(&udev->state_lock);
if (dev) {
name = dev->name;
@ -366,7 +384,9 @@ static int uinput_create_device(struct uinput_device *udev)
if (error)
goto fail2;
spin_lock(&udev->state_lock);
udev->state = UIST_CREATED;
spin_unlock(&udev->state_lock);
return 0;
@ -384,6 +404,7 @@ static int uinput_open(struct inode *inode, struct file *file)
return -ENOMEM;
mutex_init(&newdev->mutex);
spin_lock_init(&newdev->state_lock);
spin_lock_init(&newdev->requests_lock);
init_waitqueue_head(&newdev->requests_waitq);
init_waitqueue_head(&newdev->waitq);

6
drivers/iommu/iommu.c
View File

@ -2717,6 +2717,12 @@ static size_t __iommu_unmap(struct iommu_domain *domain,
pr_debug("unmapped: iova 0x%lx size 0x%zx\n",
iova, unmapped_page);
/*
* If the driver itself isn't using the gather, make sure
* it looks non-empty so iotlb_sync will still be called.
*/
if (iotlb_gather->start >= iotlb_gather->end)
iommu_iotlb_gather_add_range(iotlb_gather, iova, size);
iova += unmapped_page;
unmapped += unmapped_page;

19
drivers/mmc/host/vub300.c
View File

@ -369,11 +369,14 @@ struct vub300_mmc_host {
static void vub300_delete(struct kref *kref)
{ /* kref callback - softirq */
struct vub300_mmc_host *vub300 = kref_to_vub300_mmc_host(kref);
struct mmc_host *mmc = vub300->mmc;
usb_free_urb(vub300->command_out_urb);
vub300->command_out_urb = NULL;
usb_free_urb(vub300->command_res_urb);
vub300->command_res_urb = NULL;
usb_put_dev(vub300->udev);
mmc_free_host(mmc);
/*
* and hence also frees vub300
* which is contained at the end of struct mmc
@ -2112,7 +2115,7 @@ static int vub300_probe(struct usb_interface *interface,
goto error1;
}
/* this also allocates memory for our VUB300 mmc host device */
mmc = devm_mmc_alloc_host(&udev->dev, sizeof(*vub300));
mmc = mmc_alloc_host(sizeof(*vub300), &udev->dev);
if (!mmc) {
retval = -ENOMEM;
dev_err(&udev->dev, "not enough memory for the mmc_host\n");
@ -2269,7 +2272,7 @@ static int vub300_probe(struct usb_interface *interface,
dev_err(&vub300->udev->dev,
"Could not find two sets of bulk-in/out endpoint pairs\n");
retval = -EINVAL;
goto error4;
goto err_free_host;
}
retval =
usb_control_msg(vub300->udev, usb_rcvctrlpipe(vub300->udev, 0),
@ -2278,14 +2281,14 @@ static int vub300_probe(struct usb_interface *interface,
0x0000, 0x0000, &vub300->hc_info,
sizeof(vub300->hc_info), 1000);
if (retval < 0)
goto error4;
goto err_free_host;
retval =
usb_control_msg(vub300->udev, usb_sndctrlpipe(vub300->udev, 0),
SET_ROM_WAIT_STATES,
USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
firmware_rom_wait_states, 0x0000, NULL, 0, 1000);
if (retval < 0)
goto error4;
goto err_free_host;
dev_info(&vub300->udev->dev,
"operating_mode = %s %s %d MHz %s %d byte USB packets\n",
(mmc->caps & MMC_CAP_SDIO_IRQ) ? "IRQs" : "POLL",
@ -2300,7 +2303,7 @@ static int vub300_probe(struct usb_interface *interface,
0x0000, 0x0000, &vub300->system_port_status,
sizeof(vub300->system_port_status), 1000);
if (retval < 0) {
goto error4;
goto err_free_host;
} else if (sizeof(vub300->system_port_status) == retval) {
vub300->card_present =
(0x0001 & vub300->system_port_status.port_flags) ? 1 : 0;
@ -2308,7 +2311,7 @@ static int vub300_probe(struct usb_interface *interface,
(0x0010 & vub300->system_port_status.port_flags) ? 1 : 0;
} else {
retval = -EINVAL;
goto error4;
goto err_free_host;
}
usb_set_intfdata(interface, vub300);
INIT_DELAYED_WORK(&vub300->pollwork, vub300_pollwork_thread);
@ -2338,6 +2341,8 @@ static int vub300_probe(struct usb_interface *interface,
return 0;
error6:
timer_delete_sync(&vub300->inactivity_timer);
err_free_host:
mmc_free_host(mmc);
/*
* and hence also frees vub300
* which is contained at the end of struct mmc
@ -2365,8 +2370,8 @@ static void vub300_disconnect(struct usb_interface *interface)
usb_set_intfdata(interface, NULL);
/* prevent more I/O from starting */
vub300->interface = NULL;
kref_put(&vub300->kref, vub300_delete);
mmc_remove_host(mmc);
kref_put(&vub300->kref, vub300_delete);
pr_info("USB vub300 remote SDIO host controller[%d]"
" now disconnected", ifnum);
return;

4
drivers/net/bonding/bond_sysfs.c
View File

@ -808,7 +808,7 @@ int __net_init bond_create_sysfs(struct bond_net *bn)
sysfs_attr_init(&bn->class_attr_bonding_masters.attr);
ret = netdev_class_create_file_ns(&bn->class_attr_bonding_masters,
bn->net);
to_ns_common(bn->net));
/* Permit multiple loads of the module by ignoring failures to
* create the bonding_masters sysfs file. Bonding devices
* created by second or subsequent loads of the module will
@ -835,7 +835,7 @@ int __net_init bond_create_sysfs(struct bond_net *bn)
/* Remove /sys/class/net/bonding_masters. */
void __net_exit bond_destroy_sysfs(struct bond_net *bn)
{
netdev_class_remove_file_ns(&bn->class_attr_bonding_masters, bn->net);
netdev_class_remove_file_ns(&bn->class_attr_bonding_masters, to_ns_common(bn->net));
}
/* Initialize sysfs for each bond. This sets up and registers

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