mfd: bd71828, bd71815: Prepare for power-supply support
Add core support for ROHM BD718(15/28/78) PMIC's charger blocks. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Link: https://lore.kernel.org/r/20250821-bd71828-charger-v3-1-cc74ac4e0fb9@kemnade.info Signed-off-by: Lee Jones <lee@kernel.org>pull/1354/merge
Matti Vaittinen
Lee Jones
parent
b445c14ac7
commit
719d02a25a
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@ -45,8 +45,8 @@ static const struct resource bd71828_rtc_irqs[] = {
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static const struct resource bd71815_power_irqs[] = {
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DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_RMV, "bd71815-dcin-rmv"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_OUT, "bd71815-clps-out"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_IN, "bd71815-clps-in"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_OUT, "bd71815-dcin-clps-out"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_IN, "bd71815-dcin-clps-in"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_RES, "bd71815-dcin-ovp-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_DET, "bd71815-dcin-ovp-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_RES, "bd71815-dcin-mon-res"),
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@ -56,7 +56,7 @@ static const struct resource bd71815_power_irqs[] = {
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DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_RES, "bd71815-vsys-low-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_DET, "bd71815-vsys-low-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_DET, "bd71815-vsys-mon-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TEMP, "bd71815-chg-wdg-temp"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TIME, "bd71815-chg-wdg"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_RES, "bd71815-rechg-res"),
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@ -87,10 +87,10 @@ static const struct resource bd71815_power_irqs[] = {
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_DET, "bd71815-bat-oc2-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_RES, "bd71815-bat-oc3-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_DET, "bd71815-bat-oc3-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_RES, "bd71815-bat-low-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_DET, "bd71815-bat-low-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_RES, "bd71815-bat-hi-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_DET, "bd71815-bat-hi-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_RES, "bd71815-temp-bat-low-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_DET, "bd71815-temp-bat-low-det"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_RES, "bd71815-temp-bat-hi-res"),
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DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_DET, "bd71815-temp-bat-hi-det"),
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};
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static const struct mfd_cell bd71815_mfd_cells[] = {
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@ -109,7 +109,30 @@ static const struct mfd_cell bd71815_mfd_cells[] = {
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},
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};
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static const struct mfd_cell bd71828_mfd_cells[] = {
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static const struct resource bd71828_power_irqs[] = {
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DEFINE_RES_IRQ_NAMED(BD71828_INT_CHG_TOPOFF_TO_DONE,
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"bd71828-chg-done"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_DET, "bd71828-pwr-dcin-in"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_RMV, "bd71828-pwr-dcin-out"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_RES,
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"bd71828-vbat-normal"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_DET, "bd71828-vbat-low"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_DET, "bd71828-btemp-hi"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_RES, "bd71828-btemp-cool"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_DET, "bd71828-btemp-lo"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_RES,
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"bd71828-btemp-warm"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_DET,
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"bd71828-temp-hi"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_RES,
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"bd71828-temp-norm"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_DET,
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"bd71828-temp-125-over"),
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DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_RES,
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"bd71828-temp-125-under"),
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};
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static struct mfd_cell bd71828_mfd_cells[] = {
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{ .name = "bd71828-pmic", },
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{ .name = "bd71828-gpio", },
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{ .name = "bd71828-led", .of_compatible = "rohm,bd71828-leds" },
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@ -118,8 +141,11 @@ static const struct mfd_cell bd71828_mfd_cells[] = {
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* BD70528 clock gate are the register address and mask.
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*/
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{ .name = "bd71828-clk", },
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{ .name = "bd71827-power", },
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{
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.name = "bd71828-power",
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.resources = bd71828_power_irqs,
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.num_resources = ARRAY_SIZE(bd71828_power_irqs),
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}, {
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.name = "bd71828-rtc",
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.resources = bd71828_rtc_irqs,
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.num_resources = ARRAY_SIZE(bd71828_rtc_irqs),
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@ -189,6 +189,69 @@ enum {
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/* Charger/Battey */
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#define BD71828_REG_CHG_STATE 0x65
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#define BD71828_REG_CHG_FULL 0xd2
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#define BD71828_REG_CHG_EN 0x6F
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#define BD71828_REG_DCIN_STAT 0x68
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#define BD71828_MASK_DCIN_DET 0x01
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#define BD71828_REG_VDCIN_U 0x9c
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#define BD71828_MASK_CHG_EN 0x01
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#define BD71828_CHG_MASK_DCIN_U 0x0f
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#define BD71828_REG_BAT_STAT 0x67
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#define BD71828_REG_BAT_TEMP 0x6c
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#define BD71828_MASK_BAT_TEMP 0x07
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#define BD71828_BAT_TEMP_OPEN 0x07
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#define BD71828_MASK_BAT_DET 0x20
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#define BD71828_MASK_BAT_DET_DONE 0x10
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#define BD71828_REG_CHG_STATE 0x65
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#define BD71828_REG_VBAT_U 0x8c
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#define BD71828_MASK_VBAT_U 0x0f
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#define BD71828_REG_VBAT_REX_AVG_U 0x92
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#define BD71828_REG_OCV_PWRON_U 0x8A
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#define BD71828_REG_VBAT_MIN_AVG_U 0x8e
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#define BD71828_REG_VBAT_MIN_AVG_L 0x8f
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#define BD71828_REG_CC_CNT3 0xb5
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#define BD71828_REG_CC_CNT2 0xb6
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#define BD71828_REG_CC_CNT1 0xb7
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#define BD71828_REG_CC_CNT0 0xb8
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#define BD71828_REG_CC_CURCD_AVG_U 0xb2
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#define BD71828_MASK_CC_CURCD_AVG_U 0x3f
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#define BD71828_MASK_CC_CUR_DIR 0x80
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#define BD71828_REG_VM_BTMP_U 0xa1
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#define BD71828_REG_VM_BTMP_L 0xa2
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#define BD71828_MASK_VM_BTMP_U 0x0f
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#define BD71828_REG_COULOMB_CTRL 0xc4
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#define BD71828_REG_COULOMB_CTRL2 0xd2
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#define BD71828_MASK_REX_CC_CLR 0x01
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#define BD71828_MASK_FULL_CC_CLR 0x10
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#define BD71828_REG_CC_CNT_FULL3 0xbd
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#define BD71828_REG_CC_CNT_CHG3 0xc1
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#define BD71828_REG_VBAT_INITIAL1_U 0x86
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#define BD71828_REG_VBAT_INITIAL1_L 0x87
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#define BD71828_REG_VBAT_INITIAL2_U 0x88
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#define BD71828_REG_VBAT_INITIAL2_L 0x89
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#define BD71828_REG_IBAT_U 0xb0
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#define BD71828_REG_IBAT_L 0xb1
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#define BD71828_REG_IBAT_AVG_U 0xb2
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#define BD71828_REG_IBAT_AVG_L 0xb3
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#define BD71828_REG_VSYS_AVG_U 0x96
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#define BD71828_REG_VSYS_AVG_L 0x97
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#define BD71828_REG_VSYS_MIN_AVG_U 0x98
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#define BD71828_REG_VSYS_MIN_AVG_L 0x99
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#define BD71828_REG_CHG_SET1 0x75
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#define BD71828_REG_ALM_VBAT_LIMIT_U 0xaa
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#define BD71828_REG_BATCAP_MON_LIMIT_U 0xcc
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#define BD71828_REG_CONF 0x64
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#define BD71828_REG_DCIN_CLPS 0x71
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#define BD71828_REG_MEAS_CLEAR 0xaf
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/* LEDs */
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#define BD71828_REG_LED_CTRL 0x4A
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