arm64: dts: renesas: Add initial SoC DTSI for RZ/V2N
Add the initial Device Tree Source Include (DTSI) file for the Renesas RZ/V2N (R9A09G056) SoC. Include support for the following components: - CPU (Cortex-A55 cores with operating points) - External clocks (audio, qextal, rtxin) - Pin controller (GPIO support) - Clock Pulse Generator (CPG) - System controller (SYS) - Serial Communication Interface (SCIF) - Secure Digital Host Interface (SDHI 0/1/2) - Generic Interrupt Controller (GIC) - ARMv8 timer Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407191628.323613-12-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>pull/1253/head
Lad Prabhakar
Geert Uytterhoeven
parent
7ed3c77a42
commit
74e252ac27
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@ -0,0 +1,282 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/V2N SoC
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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#include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
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/* RZV2N_Px = Offset address of PFC_P_mn - 0x20 */
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#define RZV2N_P0 0
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#define RZV2N_P1 1
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#define RZV2N_P2 2
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#define RZV2N_P3 3
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#define RZV2N_P4 4
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#define RZV2N_P5 5
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#define RZV2N_P6 6
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#define RZV2N_P7 7
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#define RZV2N_P8 8
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#define RZV2N_P9 9
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#define RZV2N_PA 10
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#define RZV2N_PB 11
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#define RZV2N_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZV2N_P##b, p, f)
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#define RZV2N_GPIO(port, pin) RZG2L_GPIO(RZV2N_P##port, pin)
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/ {
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compatible = "renesas,r9a09g056";
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#address-cells = <2>;
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#size-cells = <2>;
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audio_extal_clk: audio-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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/*
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* The default cluster table is based on the assumption that the PLLCA55 clock
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* frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
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* 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be
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* clocked to 1.8GHz as well). The table below should be overridden in the board
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* DTS based on the PLLCA55 clock frequency.
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*/
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cluster0_opp: opp-table-0 {
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compatible = "operating-points-v2";
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opp-1700000000 {
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opp-hz = /bits/ 64 <1700000000>;
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opp-microvolt = <900000>;
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clock-latency-ns = <300000>;
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};
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opp-850000000 {
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opp-hz = /bits/ 64 <850000000>;
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opp-microvolt = <800000>;
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clock-latency-ns = <300000>;
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};
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opp-425000000 {
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opp-hz = /bits/ 64 <425000000>;
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opp-microvolt = <800000>;
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clock-latency-ns = <300000>;
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};
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opp-212500000 {
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opp-hz = /bits/ 64 <212500000>;
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opp-microvolt = <800000>;
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clock-latency-ns = <300000>;
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opp-suspend;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a55";
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reg = <0>;
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device_type = "cpu";
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next-level-cache = <&L3_CA55>;
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK0>;
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu1: cpu@100 {
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compatible = "arm,cortex-a55";
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reg = <0x100>;
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device_type = "cpu";
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next-level-cache = <&L3_CA55>;
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK1>;
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu2: cpu@200 {
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compatible = "arm,cortex-a55";
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reg = <0x200>;
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device_type = "cpu";
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next-level-cache = <&L3_CA55>;
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK2>;
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu3: cpu@300 {
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compatible = "arm,cortex-a55";
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reg = <0x300>;
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device_type = "cpu";
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next-level-cache = <&L3_CA55>;
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK3>;
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operating-points-v2 = <&cluster0_opp>;
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};
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L3_CA55: cache-controller-0 {
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compatible = "cache";
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cache-unified;
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cache-size = <0x100000>;
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cache-level = <3>;
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};
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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qextal_clk: qextal-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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rtxin_clk: rtxin-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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soc: soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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pinctrl: pinctrl@10410000 {
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compatible = "renesas,r9a09g056-pinctrl";
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reg = <0 0x10410000 0 0x10000>;
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clocks = <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 96>;
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power-domains = <&cpg>;
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resets = <&cpg 0xa5>, <&cpg 0xa6>;
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};
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cpg: clock-controller@10420000 {
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compatible = "renesas,r9a09g056-cpg";
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reg = <0 0x10420000 0 0x10000>;
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clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
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clock-names = "audio_extal", "rtxin", "qextal";
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#clock-cells = <2>;
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#reset-cells = <1>;
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#power-domain-cells = <0>;
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};
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sys: system-controller@10430000 {
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compatible = "renesas,r9a09g056-sys";
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reg = <0 0x10430000 0 0x10000>;
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clocks = <&cpg CPG_CORE R9A09G056_SYS_0_PCLK>;
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resets = <&cpg 0x30>;
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};
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scif: serial@11c01400 {
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compatible = "renesas,scif-r9a09g056",
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"renesas,scif-r9a09g057";
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reg = <0 0x11c01400 0 0x400>;
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interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 536 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 537 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eri", "rxi", "txi", "bri", "dri",
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"tei", "tei-dri", "rxi-edge", "txi-edge";
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clocks = <&cpg CPG_MOD 0x8f>;
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clock-names = "fck";
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power-domains = <&cpg>;
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resets = <&cpg 0x95>;
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status = "disabled";
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};
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gic: interrupt-controller@14900000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x14900000 0 0x20000>,
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<0x0 0x14940000 0 0x80000>;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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};
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sdhi0: mmc@15c00000 {
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compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057";
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reg = <0x0 0x15c00000 0 0x10000>;
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interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>,
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<&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>;
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clock-names = "core", "clkh", "cd", "aclk";
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resets = <&cpg 0xa7>;
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power-domains = <&cpg>;
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status = "disabled";
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sdhi0_vqmmc: vqmmc-regulator {
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regulator-name = "SDHI0-VQMMC";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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status = "disabled";
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};
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};
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sdhi1: mmc@15c10000 {
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compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057";
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reg = <0x0 0x15c10000 0 0x10000>;
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interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>,
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<&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>;
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clock-names = "core", "clkh", "cd", "aclk";
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resets = <&cpg 0xa8>;
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power-domains = <&cpg>;
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status = "disabled";
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sdhi1_vqmmc: vqmmc-regulator {
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regulator-name = "SDHI1-VQMMC";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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status = "disabled";
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};
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};
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sdhi2: mmc@15c20000 {
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compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057";
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reg = <0x0 0x15c20000 0 0x10000>;
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interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>,
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<&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>;
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clock-names = "core", "clkh", "cd", "aclk";
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resets = <&cpg 0xa9>;
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power-domains = <&cpg>;
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status = "disabled";
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sdhi2_vqmmc: vqmmc-regulator {
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regulator-name = "SDHI2-VQMMC";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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status = "disabled";
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
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<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
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};
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};
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