From a4ba1ea69f6b6d2b3eee7234deba986a82a77203 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 Sep 2023 14:06:28 +0300 Subject: [PATCH 01/82] drm/i915: define I915 during i915 driver build The xe driver will reuse i915 display code by compiling it separately as part of xe. We'll want to be able to distinguish between building the i915 display code for i915 and xe. Define I915 when building i915. Cc: David Airlie Cc: Daniel Vetter Cc: Joonas Lahtinen Cc: Rodrigo Vivi Cc: Tvrtko Ursulin Cc: Lucas De Marchi Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Acked-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/97558201836115b91cbe32840239df855d0c2e4c.1694514689.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index de4967c141f0..dec78efa452a 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -28,6 +28,10 @@ CFLAGS_i915_pci.o = $(call cc-disable-warning, override-init) CFLAGS_display/intel_display_device.o = $(call cc-disable-warning, override-init) CFLAGS_display/intel_fbdev.o = $(call cc-disable-warning, override-init) +# Support compiling the display code separately for both i915 and xe +# drivers. Define I915 when building i915. +subdir-ccflags-y += -DI915 + subdir-ccflags-y += -I$(srctree)/$(src) # Please keep these build lists sorted! From 197a30c4c62fb0ce4d6553443775f23987bada8e Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 Sep 2023 14:06:29 +0300 Subject: [PATCH 02/82] drm/i915/display: add I915 conditional build to intel_lvds.h Add stubs for !I915. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Acked-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/f06a88a69b7e326ff0914baca5e6a0e5f06e1867.1694514689.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_lvds.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_lvds.h b/drivers/gpu/drm/i915/display/intel_lvds.h index 9d3372dc503f..7ad5fa9c0434 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.h +++ b/drivers/gpu/drm/i915/display/intel_lvds.h @@ -13,10 +13,29 @@ enum pipe; struct drm_i915_private; +#ifdef I915 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv, i915_reg_t lvds_reg, enum pipe *pipe); void intel_lvds_init(struct drm_i915_private *dev_priv); struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv); bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv); +#else +static inline bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv, + i915_reg_t lvds_reg, enum pipe *pipe) +{ + return false; +} +static inline void intel_lvds_init(struct drm_i915_private *dev_priv) +{ +} +static inline struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv) +{ + return NULL; +} +static inline bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv) +{ + return false; +} +#endif #endif /* __INTEL_LVDS_H__ */ From f8b5f0efa0318e2a2764ae6a8f96b55d84715981 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 Sep 2023 14:06:30 +0300 Subject: [PATCH 03/82] drm/i915/display: add I915 conditional build to hsw_ips.h Add stubs for !I915. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Acked-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/04469b92be51b8394d74a508174f041aa7e011e8.1694514689.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/hsw_ips.h | 35 ++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/gpu/drm/i915/display/hsw_ips.h b/drivers/gpu/drm/i915/display/hsw_ips.h index 4eb83b350791..35364228e1c1 100644 --- a/drivers/gpu/drm/i915/display/hsw_ips.h +++ b/drivers/gpu/drm/i915/display/hsw_ips.h @@ -12,6 +12,7 @@ struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; +#ifdef I915 bool hsw_ips_disable(const struct intel_crtc_state *crtc_state); bool hsw_ips_pre_update(struct intel_atomic_state *state, struct intel_crtc *crtc); @@ -23,5 +24,39 @@ int hsw_ips_compute_config(struct intel_atomic_state *state, struct intel_crtc *crtc); void hsw_ips_get_config(struct intel_crtc_state *crtc_state); void hsw_ips_crtc_debugfs_add(struct intel_crtc *crtc); +#else +static inline bool hsw_ips_disable(const struct intel_crtc_state *crtc_state) +{ + return false; +} +static inline bool hsw_ips_pre_update(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + return false; +} +static inline void hsw_ips_post_update(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ +} +static inline bool hsw_crtc_supports_ips(struct intel_crtc *crtc) +{ + return false; +} +static inline bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state) +{ + return false; +} +static inline int hsw_ips_compute_config(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + return 0; +} +static inline void hsw_ips_get_config(struct intel_crtc_state *crtc_state) +{ +} +static inline void hsw_ips_crtc_debugfs_add(struct intel_crtc *crtc) +{ +} +#endif #endif /* __HSW_IPS_H__ */ From 818fdb16d40c4bba3daf2d208e32a8b3ee1b2f95 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 Sep 2023 14:06:31 +0300 Subject: [PATCH 04/82] drm/i915/display: add I915 conditional build to i9xx_plane.h Add stubs for !I915. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Acked-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/4ad1864c66adcf691906c37b554f640d04069fb2.1694514689.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/i9xx_plane.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.h b/drivers/gpu/drm/i915/display/i9xx_plane.h index 027b66053984..b3d724a144cb 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane.h @@ -15,6 +15,7 @@ struct intel_initial_plane_config; struct intel_plane; struct intel_plane_state; +#ifdef I915 unsigned int i965_plane_max_stride(struct intel_plane *plane, u32 pixel_format, u64 modifier, unsigned int rotation); @@ -25,4 +26,26 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe); void i9xx_get_initial_plane_config(struct intel_crtc *crtc, struct intel_initial_plane_config *plane_config); +#else +static inline unsigned int i965_plane_max_stride(struct intel_plane *plane, + u32 pixel_format, u64 modifier, + unsigned int rotation) +{ + return 0; +} +static inline int i9xx_check_plane_surface(struct intel_plane_state *plane_state) +{ + return 0; +} +static inline struct intel_plane * +intel_primary_plane_create(struct drm_i915_private *dev_priv, int pipe) +{ + return NULL; +} +static inline void i9xx_get_initial_plane_config(struct intel_crtc *crtc, + struct intel_initial_plane_config *plane_config) +{ +} +#endif + #endif From 3c0e538a6d307cf2f22737ee58bd3af64e74e82a Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 Sep 2023 14:06:32 +0300 Subject: [PATCH 05/82] drm/i915/display: add I915 conditional build to intel_lpe_audio.h Add stubs for !I915. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Acked-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/7c10d8c4a2a628cba17b3b0f89b657dfbc91eaa9.1694514689.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_lpe_audio.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.h b/drivers/gpu/drm/i915/display/intel_lpe_audio.h index 0beecac267ae..2c5fcb6e1fd0 100644 --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.h +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.h @@ -12,11 +12,29 @@ enum port; enum transcoder; struct drm_i915_private; +#ifdef I915 int intel_lpe_audio_init(struct drm_i915_private *dev_priv); void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv); void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv); void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder, enum port port, const void *eld, int ls_clock, bool dp_output); +#else +static inline int intel_lpe_audio_init(struct drm_i915_private *dev_priv) +{ + return -ENODEV; +} +static inline void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv) +{ +} +static inline void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv) +{ +} +static inline void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, + enum transcoder cpu_transcoder, enum port port, + const void *eld, int ls_clock, bool dp_output) +{ +} +#endif #endif /* __INTEL_LPE_AUDIO_H__ */ From 19ff503b866bddee53206ed59e7aa341f481d56f Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 Sep 2023 14:06:33 +0300 Subject: [PATCH 06/82] drm/i915/display: add I915 conditional build to intel_pch_refclk.h Add stubs for !I915. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Acked-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/4359b34cbcff6199b5e42b5311c815aa6f4a167c.1694514689.git.jani.nikula@intel.com --- .../gpu/drm/i915/display/intel_pch_refclk.h | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.h b/drivers/gpu/drm/i915/display/intel_pch_refclk.h index 9bcf56629f24..ae3403c0ced8 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.h +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.h @@ -11,6 +11,7 @@ struct drm_i915_private; struct intel_crtc_state; +#ifdef I915 void lpt_program_iclkip(const struct intel_crtc_state *crtc_state); void lpt_disable_iclkip(struct drm_i915_private *dev_priv); int lpt_get_iclkip(struct drm_i915_private *dev_priv); @@ -18,5 +19,27 @@ int lpt_iclkip(const struct intel_crtc_state *crtc_state); void intel_init_pch_refclk(struct drm_i915_private *dev_priv); void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv); +#else +static inline void lpt_program_iclkip(const struct intel_crtc_state *crtc_state) +{ +} +static inline void lpt_disable_iclkip(struct drm_i915_private *dev_priv) +{ +} +static inline int lpt_get_iclkip(struct drm_i915_private *dev_priv) +{ + return 0; +} +static inline int lpt_iclkip(const struct intel_crtc_state *crtc_state) +{ + return 0; +} +static inline void intel_init_pch_refclk(struct drm_i915_private *dev_priv) +{ +} +static inline void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) +{ +} +#endif #endif From 6df6daad84d84ed9fae500f47b0a1837220923df Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 Sep 2023 14:06:34 +0300 Subject: [PATCH 07/82] drm/i915/display: add I915 conditional build to intel_pch_display.h Add stubs for !I915. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Acked-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/02de0089de58c9fb19b6b56121f6c917f51b4561.1694514689.git.jani.nikula@intel.com --- .../gpu/drm/i915/display/intel_pch_display.h | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h b/drivers/gpu/drm/i915/display/intel_pch_display.h index 41a63413cb3d..35f8288af3d1 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.h +++ b/drivers/gpu/drm/i915/display/intel_pch_display.h @@ -15,6 +15,7 @@ struct intel_crtc; struct intel_crtc_state; struct intel_link_m_n; +#ifdef I915 bool intel_has_pch_trancoder(struct drm_i915_private *i915, enum pipe pch_transcoder); enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); @@ -41,5 +42,57 @@ void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n); void intel_pch_sanitize(struct drm_i915_private *i915); +#else +static inline bool intel_has_pch_trancoder(struct drm_i915_private *i915, + enum pipe pch_transcoder) +{ + return false; +} +static inline int intel_crtc_pch_transcoder(struct intel_crtc *crtc) +{ + return 0; +} +static inline void ilk_pch_pre_enable(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ +} +static inline void ilk_pch_enable(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ +} +static inline void ilk_pch_disable(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ +} +static inline void ilk_pch_post_disable(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ +} +static inline void ilk_pch_get_config(struct intel_crtc_state *crtc_state) +{ +} +static inline void lpt_pch_enable(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ +} +static inline void lpt_pch_disable(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ +} +static inline void lpt_pch_get_config(struct intel_crtc_state *crtc_state) +{ +} +static inline void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc, + struct intel_link_m_n *m_n) +{ +} +static inline void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc, + struct intel_link_m_n *m_n) +{ +} +static inline void intel_pch_sanitize(struct drm_i915_private *i915) +{ +} +#endif #endif From 8cd3a40c52ea222a5565e50aacec431140af259c Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 Sep 2023 14:06:35 +0300 Subject: [PATCH 08/82] drm/i915/display: add I915 conditional build to intel_sprite.h Add stubs for !I915. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Acked-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/b9680203b0b93dc3472260d7e4128984e533b421.1694514689.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_sprite.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.h b/drivers/gpu/drm/i915/display/intel_sprite.h index 91c6dca342b2..044a032e41b9 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.h +++ b/drivers/gpu/drm/i915/display/intel_sprite.h @@ -16,6 +16,7 @@ struct intel_crtc_state; struct intel_plane_state; enum pipe; +#ifdef I915 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe, int plane); int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, @@ -29,5 +30,12 @@ int hsw_plane_min_cdclk(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state); int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state); +#else +static inline struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv, + int pipe, int plane) +{ + return NULL; +} +#endif #endif /* __INTEL_SPRITE_H__ */ From cebaacae96cbbd443be948eda1c71a58542c1fce Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 Sep 2023 14:06:36 +0300 Subject: [PATCH 09/82] drm/i915/display: add I915 conditional build to intel_overlay.h Add stubs for !I915. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Acked-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/45a127d37816ac97dfe493beeed060e323047014.1694514689.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_overlay.h | 35 ++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_overlay.h b/drivers/gpu/drm/i915/display/intel_overlay.h index a167c28acd27..c3f68fce6f08 100644 --- a/drivers/gpu/drm/i915/display/intel_overlay.h +++ b/drivers/gpu/drm/i915/display/intel_overlay.h @@ -13,6 +13,7 @@ struct drm_i915_private; struct intel_overlay; struct intel_overlay_error_state; +#ifdef I915 void intel_overlay_setup(struct drm_i915_private *dev_priv); void intel_overlay_cleanup(struct drm_i915_private *dev_priv); int intel_overlay_switch_off(struct intel_overlay *overlay); @@ -25,5 +26,39 @@ struct intel_overlay_error_state * intel_overlay_capture_error_state(struct drm_i915_private *dev_priv); void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, struct intel_overlay_error_state *error); +#else +static inline void intel_overlay_setup(struct drm_i915_private *dev_priv) +{ +} +static inline void intel_overlay_cleanup(struct drm_i915_private *dev_priv) +{ +} +static inline int intel_overlay_switch_off(struct intel_overlay *overlay) +{ + return 0; +} +static inline int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + return 0; +} +static inline int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + return 0; +} +static inline void intel_overlay_reset(struct drm_i915_private *dev_priv) +{ +} +static inline struct intel_overlay_error_state * +intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) +{ + return NULL; +} +static inline void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, + struct intel_overlay_error_state *error) +{ +} +#endif #endif /* __INTEL_OVERLAY_H__ */ From 603dbd3e33d7bc88b7a04b3e82cf1b329b819e6b Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 Sep 2023 14:06:37 +0300 Subject: [PATCH 10/82] drm/i915/display: add I915 conditional build to g4x_dp.h Add stubs for !I915. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Acked-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/ba92fc1dee1f71018179dbe10b91982c9c93e7e6.1694514689.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/g4x_dp.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/i915/display/g4x_dp.h b/drivers/gpu/drm/i915/display/g4x_dp.h index a38b3e1e01d3..a10638ab749c 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.h +++ b/drivers/gpu/drm/i915/display/g4x_dp.h @@ -17,6 +17,7 @@ struct intel_crtc_state; struct intel_dp; struct intel_encoder; +#ifdef I915 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915); enum pipe vlv_active_pipe(struct intel_dp *intel_dp); void g4x_dp_set_clock(struct intel_encoder *encoder, @@ -26,5 +27,30 @@ bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv, enum pipe *pipe); bool g4x_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg, enum port port); +#else +static inline const struct dpll *vlv_get_dpll(struct drm_i915_private *i915) +{ + return NULL; +} +static inline int vlv_active_pipe(struct intel_dp *intel_dp) +{ + return 0; +} +static inline void g4x_dp_set_clock(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) +{ +} +static inline bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv, + i915_reg_t dp_reg, int port, + enum pipe *pipe) +{ + return false; +} +static inline bool g4x_dp_init(struct drm_i915_private *dev_priv, + i915_reg_t output_reg, int port) +{ + return false; +} +#endif #endif From bc872e300b64ac9bd45bde9a7311edfc3ac41993 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 Sep 2023 14:06:38 +0300 Subject: [PATCH 11/82] drm/i915/display: add I915 conditional build to intel_dpio_phy.h Add stubs for !I915. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Acked-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/978bc7263e8de10ffc1ef16086341dd629347c8e.1694514689.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_dpio_phy.h | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.h b/drivers/gpu/drm/i915/display/intel_dpio_phy.h index 9c7725dacb47..4d43dbbdf81c 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.h +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.h @@ -26,6 +26,7 @@ enum dpio_phy { DPIO_PHY2, }; +#ifdef I915 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, enum dpio_phy *phy, enum dpio_channel *ch); void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder, @@ -70,5 +71,100 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void vlv_phy_reset_lanes(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state); +#else +static inline void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, + enum dpio_phy *phy, enum dpio_channel *ch) +{ +} +static inline void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ +} +static inline void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy) +{ +} +static inline void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy) +{ +} +static inline bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, + enum dpio_phy phy) +{ + return false; +} +static inline bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, + enum dpio_phy phy) +{ + return true; +} +static inline u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count) +{ + return 0; +} +static inline void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, + u8 lane_lat_optim_mask) +{ +} +static inline u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder) +{ + return 0; +} +static inline enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port) +{ + return DPIO_CH0; +} +static inline enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port) +{ + return DPIO_PHY0; +} +static inline enum dpio_channel vlv_pipe_to_channel(enum pipe pipe) +{ + return DPIO_CH0; +} +static inline void chv_set_phy_signal_level(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + u32 deemph_reg_value, u32 margin_reg_value, + bool uniq_trans_scale) +{ +} +static inline void chv_data_lane_soft_reset(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + bool reset) +{ +} +static inline void chv_phy_pre_pll_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ +} +static inline void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ +} +static inline void chv_phy_release_cl2_override(struct intel_encoder *encoder) +{ +} +static inline void chv_phy_post_pll_disable(struct intel_encoder *encoder, + const struct intel_crtc_state *old_crtc_state) +{ +} + +static inline void vlv_set_phy_signal_level(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + u32 demph_reg_value, u32 preemph_reg_value, + u32 uniqtranscale_reg_value, u32 tx3_demph) +{ +} +static inline void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ +} +static inline void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ +} +static inline void vlv_phy_reset_lanes(struct intel_encoder *encoder, + const struct intel_crtc_state *old_crtc_state) +{ +} +#endif #endif /* __INTEL_DPIO_PHY_H__ */ From 3675c607a81e70c1697a72b713da83a6be0ead95 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 Sep 2023 14:06:39 +0300 Subject: [PATCH 12/82] drm/i915/display: add I915 conditional build to intel_crt.h Add stubs for !I915. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Acked-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/89a6daca98f87ed1a8a54367a977f146216330d2.1694514689.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_crt.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_crt.h b/drivers/gpu/drm/i915/display/intel_crt.h index c6071efd93ce..fe7690c2b948 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.h +++ b/drivers/gpu/drm/i915/display/intel_crt.h @@ -12,9 +12,23 @@ enum pipe; struct drm_encoder; struct drm_i915_private; +#ifdef I915 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, i915_reg_t adpa_reg, enum pipe *pipe); void intel_crt_init(struct drm_i915_private *dev_priv); void intel_crt_reset(struct drm_encoder *encoder); +#else +static inline bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, + i915_reg_t adpa_reg, enum pipe *pipe) +{ + return false; +} +static inline void intel_crt_init(struct drm_i915_private *dev_priv) +{ +} +static inline void intel_crt_reset(struct drm_encoder *encoder) +{ +} +#endif #endif /* __INTEL_CRT_H__ */ From ca116c0075d4d1b70abf2e0e961aea6f13423351 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 Sep 2023 14:06:40 +0300 Subject: [PATCH 13/82] drm/i915/display: add I915 conditional build to vlv_dsi.h Add stubs for !I915. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Acked-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/9f538824f15096b0c1444ee50d175a0a22d7bd5e.1694514689.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/vlv_dsi.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.h b/drivers/gpu/drm/i915/display/vlv_dsi.h index 0c2b279df9d4..cf9d7b82f288 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.h +++ b/drivers/gpu/drm/i915/display/vlv_dsi.h @@ -12,8 +12,21 @@ enum port; struct drm_i915_private; struct intel_dsi; +#ifdef I915 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port); enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt); void vlv_dsi_init(struct drm_i915_private *dev_priv); +#else +static inline void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) +{ +} +static inline enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) +{ + return 0; +} +static inline void vlv_dsi_init(struct drm_i915_private *dev_priv) +{ +} +#endif #endif /* __VLV_DSI_H__ */ From 7a4946840481ea62874b80ee374b6e85cb0d3e96 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 Sep 2023 14:06:41 +0300 Subject: [PATCH 14/82] drm/i915/display: add I915 conditional build to i9xx_wm.h Add stubs for !I915. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Acked-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/bf15b14d3d060fdb256c78d4b8514d642a8958e6.1694514689.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/i9xx_wm.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.h b/drivers/gpu/drm/i915/display/i9xx_wm.h index b87ae369685a..de0920730ab2 100644 --- a/drivers/gpu/drm/i915/display/i9xx_wm.h +++ b/drivers/gpu/drm/i915/display/i9xx_wm.h @@ -12,9 +12,26 @@ struct drm_i915_private; struct intel_crtc_state; struct intel_plane_state; +#ifdef I915 bool ilk_disable_lp_wm(struct drm_i915_private *i915); void ilk_wm_sanitize(struct drm_i915_private *i915); bool intel_set_memory_cxsr(struct drm_i915_private *i915, bool enable); void i9xx_wm_init(struct drm_i915_private *i915); +#else +static inline bool ilk_disable_lp_wm(struct drm_i915_private *i915) +{ + return false; +} +static inline void ilk_wm_sanitize(struct drm_i915_private *i915) +{ +} +static inline bool intel_set_memory_cxsr(struct drm_i915_private *i915, bool enable) +{ + return false; +} +static inline void i9xx_wm_init(struct drm_i915_private *i915) +{ +} +#endif #endif /* __I9XX_WM_H__ */ From 9543cc39db988527fbb54283aa7b49d810a46f9f Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 Sep 2023 14:06:42 +0300 Subject: [PATCH 15/82] drm/i915/display: add I915 conditional build to g4x_hdmi.h Add stubs for !I915. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Acked-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/ba2eea7ac081d0858a573062f197e00f3b186faf.1694514689.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/g4x_hdmi.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.h b/drivers/gpu/drm/i915/display/g4x_hdmi.h index 1e3ea7f3c846..817f55c7a3a1 100644 --- a/drivers/gpu/drm/i915/display/g4x_hdmi.h +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.h @@ -15,9 +15,21 @@ struct drm_atomic_state; struct drm_connector; struct drm_i915_private; +#ifdef I915 void g4x_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg, enum port port); int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state); +#else +static inline void g4x_hdmi_init(struct drm_i915_private *dev_priv, + i915_reg_t hdmi_reg, int port) +{ +} +static inline int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, + struct drm_atomic_state *state) +{ + return 0; +} +#endif #endif From 6842d38178e71051a8c7ce5bb32314ec2fa5cf17 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 Sep 2023 14:06:43 +0300 Subject: [PATCH 16/82] drm/i915/display: add I915 conditional build to intel_dvo.h Add stubs for !I915. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Acked-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/d43b27742297083b37d52222c4bb72b062ef4967.1694514689.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_dvo.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dvo.h b/drivers/gpu/drm/i915/display/intel_dvo.h index 3ed0fdf8efff..bf7a356422ab 100644 --- a/drivers/gpu/drm/i915/display/intel_dvo.h +++ b/drivers/gpu/drm/i915/display/intel_dvo.h @@ -8,6 +8,12 @@ struct drm_i915_private; +#ifdef I915 void intel_dvo_init(struct drm_i915_private *dev_priv); +#else +static inline void intel_dvo_init(struct drm_i915_private *dev_priv) +{ +} +#endif #endif /* __INTEL_DVO_H__ */ From e6a5ad9a75500506f2c516ef85eb03ec5c49140e Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 Sep 2023 14:06:44 +0300 Subject: [PATCH 17/82] drm/i915/display: add I915 conditional build to intel_sdvo.h Add stubs for !I915. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Acked-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/c34ea1f470590488acf40512da3892ca153f482a.1694514689.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_sdvo.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.h b/drivers/gpu/drm/i915/display/intel_sdvo.h index 2868852c85f2..d1815b4103d4 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.h +++ b/drivers/gpu/drm/i915/display/intel_sdvo.h @@ -14,9 +14,22 @@ struct drm_i915_private; enum pipe; enum port; +#ifdef I915 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, i915_reg_t sdvo_reg, enum pipe *pipe); bool intel_sdvo_init(struct drm_i915_private *dev_priv, i915_reg_t reg, enum port port); +#else +static inline bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, + i915_reg_t sdvo_reg, enum pipe *pipe) +{ + return false; +} +static inline bool intel_sdvo_init(struct drm_i915_private *dev_priv, + i915_reg_t reg, enum port port) +{ + return false; +} +#endif #endif /* __INTEL_SDVO_H__ */ From 7f5c64c0871ea63a420ca4cd05e9df2d4e5f9232 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 Sep 2023 14:06:45 +0300 Subject: [PATCH 18/82] drm/i915/display: add I915 conditional build to intel_tv.h Add stubs for !I915. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Acked-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/290e555ac87ea11cd6021c1338b75ad64c42ae98.1694514689.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_tv.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_tv.h b/drivers/gpu/drm/i915/display/intel_tv.h index 44518575ec5c..f08827b8bf2b 100644 --- a/drivers/gpu/drm/i915/display/intel_tv.h +++ b/drivers/gpu/drm/i915/display/intel_tv.h @@ -8,6 +8,12 @@ struct drm_i915_private; +#ifdef I915 void intel_tv_init(struct drm_i915_private *dev_priv); +#else +static inline void intel_tv_init(struct drm_i915_private *dev_priv) +{ +} +#endif #endif /* __INTEL_TV_H__ */ From 659eed2ef0e6bd9dc0d4e503a65e74726e330e1b Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 Sep 2023 14:06:46 +0300 Subject: [PATCH 19/82] drm/i915/display: add I915 conditional build to vlv_dsi_pll.h Add stubs for !I915. Not all the functions need to be stubbed. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Acked-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/930c8d332d425a54dae7af16aed26ec293f80afd.1694514689.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/vlv_dsi_pll.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.h b/drivers/gpu/drm/i915/display/vlv_dsi_pll.h index ab9291ad1e79..fbe5113dbeb9 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.h +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.h @@ -32,7 +32,16 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, struct intel_crtc_state *config); void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port); +#ifdef I915 void assert_dsi_pll_enabled(struct drm_i915_private *i915); void assert_dsi_pll_disabled(struct drm_i915_private *i915); +#else +static inline void assert_dsi_pll_enabled(struct drm_i915_private *i915) +{ +} +static inline void assert_dsi_pll_disabled(struct drm_i915_private *i915) +{ +} +#endif #endif /* __VLV_DSI_PLL_H__ */ From f52d1493dfbf9ba421bb3f84a798cc309128b728 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jouni=20H=C3=B6gander?= Date: Fri, 29 Sep 2023 14:20:47 +0300 Subject: [PATCH 20/82] drm/i915/display: Include i915_active header in frontbuffer tracking code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Intel frontbuffer tracking code is using i915_active functions -> include i915_active.h directly instead of relying getting indirectly included. Cc: Jani Nikula Signed-off-by: Jouni Högander Reviewed-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20230929112047.1151914-1-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_frontbuffer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c index 412a19a888a2..ec46716b2f49 100644 --- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c +++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c @@ -56,6 +56,7 @@ */ #include "gem/i915_gem_object_frontbuffer.h" +#include "i915_active.h" #include "i915_drv.h" #include "intel_display_trace.h" #include "intel_display_types.h" From 4c7690614c8bbd6cd29b949f9084ddb294ffe284 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Fri, 29 Sep 2023 16:50:23 -0400 Subject: [PATCH 21/82] drm/i915: Abstract display info away during probe The goal is to have this function ready for Xe to use directly. So, let's use the available macro. Cc: Jani Nikula Signed-off-by: Rodrigo Vivi Reviewed-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20230929205023.1202735-1-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/display/intel_display_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index a6a18eae7ae8..ce55b968e658 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -926,7 +926,7 @@ void intel_display_device_probe(struct drm_i915_private *i915) else info = probe_display(i915); - i915->display.info.__device_info = info; + DISPLAY_INFO(i915) = info; memcpy(DISPLAY_RUNTIME_INFO(i915), &DISPLAY_INFO(i915)->__runtime_defaults, From d38d753da7f7c9c4739e3e9ca3c986fa2c1b8c98 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Tue, 26 Sep 2023 12:51:06 -0400 Subject: [PATCH 22/82] drm/i915: Add missing CCS documentation Let's introduce the basic documentation about CCS. While doing that, also removed the legacy execution flag name. That flag simply doesn't exist for CCS and it is not needed on current context submission. Those flag names are only needed on legacy context, while on new ones we only need to pass the engine ID. It is worth mention that this documentation should probably live with the engine definitions rather than in the i915.rst file directly and that more updates are likely need in this section. But this should come later. v2: Overall improvements from Matt and Tvrtko. Fixes: 944823c94639 ("drm/i915/xehp: Define compute class and engine") Cc: Matt Roper Cc: Sushma Venkatesh Reddy Cc: Joonas Lahtinen Cc: Tvrtko Ursulin Signed-off-by: Rodrigo Vivi Acked-by: Tvrtko Ursulin Reviewed-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20230926165107.23440-1-rodrigo.vivi@intel.com --- Documentation/gpu/i915.rst | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 378e825754d5..13de8bcaaa29 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -267,19 +267,18 @@ i915 driver. Intel GPU Basics ---------------- -An Intel GPU has multiple engines. There are several engine types. +An Intel GPU has multiple engines. There are several engine types: -- RCS engine is for rendering 3D and performing compute, this is named - `I915_EXEC_RENDER` in user space. -- BCS is a blitting (copy) engine, this is named `I915_EXEC_BLT` in user - space. -- VCS is a video encode and decode engine, this is named `I915_EXEC_BSD` - in user space -- VECS is video enhancement engine, this is named `I915_EXEC_VEBOX` in user - space. -- The enumeration `I915_EXEC_DEFAULT` does not refer to specific engine; - instead it is to be used by user space to specify a default rendering - engine (for 3D) that may or may not be the same as RCS. +- Render Command Streamer (RCS). An engine for rendering 3D and + performing compute. +- Blitting Command Streamer (BCS). An engine for performing blitting and/or + copying operations. +- Video Command Streamer. An engine used for video encoding and decoding. Also + sometimes called 'BSD' in hardware documentation. +- Video Enhancement Command Streamer (VECS). An engine for video enhancement. + Also sometimes called 'VEBOX' in hardware documentation. +- Compute Command Streamer (CCS). An engine that has access to the media and + GPGPU pipelines, but not the 3D pipeline. The Intel GPU family is a family of integrated GPU's using Unified Memory Access. For having the GPU "do work", user space will feed the From 587e80dc1cb5f1f3f41b38356d3e3563c01d9d8e Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Tue, 26 Sep 2023 13:55:54 -0400 Subject: [PATCH 23/82] drm/i915: Add missing GSCCS documentation Introduce the basic documentation about GSC CS. This "GPU Basics" section is focused on explaining the hardware rather than the driver/uapi, so let's make sure GSC is also properly documented here. v2: Fixes from Matt: typos and acronym. Fixes: 5fd974d164b4 ("drm/i915/mtl: add initial definitions for GSC CS") Suggested-by: Matt Roper Cc: Daniele Ceraolo Spurio Cc: Tvrtko Ursulin Signed-off-by: Rodrigo Vivi Reviewed-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20230926175554.25968-1-rodrigo.vivi@intel.com --- Documentation/gpu/i915.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 13de8bcaaa29..0ca1550fd9dc 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -279,6 +279,10 @@ An Intel GPU has multiple engines. There are several engine types: Also sometimes called 'VEBOX' in hardware documentation. - Compute Command Streamer (CCS). An engine that has access to the media and GPGPU pipelines, but not the 3D pipeline. +- Graphics Security Controller (GSCCS). A dedicated engine for internal + communication with GSC controller on security related tasks like + High-bandwidth Digital Content Protection (HDCP), Protected Xe Path (PXP), + and HuC firmware authentication. The Intel GPU family is a family of integrated GPU's using Unified Memory Access. For having the GPU "do work", user space will feed the From de1ee4e4cd32ce044276ba809c985344cecdf7ac Mon Sep 17 00:00:00 2001 From: Vinod Govindapillai Date: Fri, 22 Sep 2023 16:30:02 +0300 Subject: [PATCH 24/82] drm/i915/lnl: possibility to enable FBC on first three planes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In LNL onwards, FBC can be associated to the first three planes. FBC will be enabled on planes first come first served basis until the userspace can select one of these FBC capable planes explicitly. v2: - avoid fbc->state.plane check in intel_fbc_check_plane (Ville) - simplify plane binding register writes (Matt) - Update the subject to reflect that fbc can be enabled only in the first three planes (Matt) v3: - use icl_is_hdr_plane(), use wrapper macro for plane binding register access, comments update and patch split (Ville) v4: - update to the plane binding register access macro Bspec: 69560 Signed-off-by: Vinod Govindapillai Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20230922133003.150578-2-vinod.govindapillai@intel.com --- drivers/gpu/drm/i915/display/intel_fbc.c | 3 +++ drivers/gpu/drm/i915/display/skl_universal_plane.c | 9 ++++++--- drivers/gpu/drm/i915/i915_reg.h | 2 ++ 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 1cb9eec29640..0f1dd8729bf1 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -593,6 +593,9 @@ static u32 ivb_dpfc_ctl(struct intel_fbc *fbc) if (IS_IVYBRIDGE(i915)) dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane); + if (DISPLAY_VER(i915) >= 20) + dpfc_ctl |= DPFC_CTL_PLANE_BINDING(fbc_state->plane->id); + if (fbc_state->fence_id >= 0) dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB; diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index b1f9adae190d..9cbf4686df1d 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1942,13 +1942,16 @@ static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe) return pipe - PIPE_A + INTEL_FBC_A; } -static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv, +static bool skl_plane_has_fbc(struct drm_i915_private *i915, enum intel_fbc_id fbc_id, enum plane_id plane_id) { - if ((DISPLAY_RUNTIME_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0) + if ((DISPLAY_RUNTIME_INFO(i915)->fbc_mask & BIT(fbc_id)) == 0) return false; - return plane_id == PLANE_PRIMARY; + if (DISPLAY_VER(i915) >= 20) + return icl_is_hdr_plane(i915, plane_id); + else + return plane_id == PLANE_PRIMARY; } static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e0ea2dc13556..1a9ca1e530bc 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1327,6 +1327,8 @@ #define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane)) #define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */ #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */ +#define DPFC_CTL_PLANE_BINDING_MASK REG_GENMASK(12, 11) /* lnl+ */ +#define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id)) #define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */ #define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */ #define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */ From f2a7b9cd5b06eba8cf12153507ff77cc80c7b45f Mon Sep 17 00:00:00 2001 From: Vinod Govindapillai Date: Fri, 22 Sep 2023 16:30:03 +0300 Subject: [PATCH 25/82] drm/i915/lnl: update the supported plane formats with FBC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit FBC is supported with RGB32 8:8:8:8 with or without alpha Bspec: 68904, 69560 Signed-off-by: Vinod Govindapillai Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20230922133003.150578-3-vinod.govindapillai@intel.com --- drivers/gpu/drm/i915/display/intel_fbc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 0f1dd8729bf1..5f13c6776c7d 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -903,6 +903,11 @@ static bool pixel_format_is_valid(const struct intel_plane_state *plane_state) if (IS_G4X(i915)) return false; return true; + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ABGR8888: + if (DISPLAY_VER(i915) >= 20) + return true; + fallthrough; default: return false; } @@ -1132,7 +1137,8 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, return 0; } - if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && + if (DISPLAY_VER(i915) < 20 && + plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && fb->format->has_alpha) { plane_state->no_fbc_reason = "per-pixel alpha not supported"; return 0; From fe63ea7c3dbb68a4a8f43a175c76e435b6ffb4ca Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 3 Oct 2023 15:42:07 +0300 Subject: [PATCH 26/82] drm/i915: convert INTEL_DISPLAY_ENABLED() into a function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There's no need for this to be a macro. Add some documentation too. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/480b9b697b2ffa0c8677115bd443ba633801c6c1.1696336887.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_crt.c | 2 +- .../gpu/drm/i915/display/intel_display_device.c | 17 +++++++++++++++++ .../gpu/drm/i915/display/intel_display_device.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- drivers/gpu/drm/i915/display/intel_dvo.c | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/display/intel_hotplug.c | 2 +- drivers/gpu/drm/i915/display/intel_panel.c | 2 +- drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +- drivers/gpu/drm/i915/display/intel_tv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 6 ------ 12 files changed, 27 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index d4bad0ddff41..913e5d230a4d 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -838,7 +838,7 @@ intel_crt_detect(struct drm_connector *connector, connector->base.id, connector->name, force); - if (!INTEL_DISPLAY_ENABLED(dev_priv)) + if (!intel_display_device_enabled(dev_priv)) return connector_status_disconnected; if (dev_priv->params.load_detect_test) { diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index ce55b968e658..dea64c99721e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -1091,3 +1091,20 @@ void intel_display_device_info_print(const struct intel_display_device_info *inf drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc)); drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc)); } + +/* + * Assuming the device has display hardware, should it be enabled? + * + * It's an error to call this function if the device does not have display + * hardware. + * + * Disabling display means taking over the display hardware, putting it to + * sleep, and preventing connectors from being connected via any means. + */ +bool intel_display_device_enabled(struct drm_i915_private *i915) +{ + /* Only valid when HAS_DISPLAY() is true */ + drm_WARN_ON(&i915->drm, !HAS_DISPLAY(i915)); + + return !i915->params.disable_display && !intel_opregion_headless_sku(i915); +} diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 44733c9d5812..8977bac8cb7f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -150,6 +150,7 @@ struct intel_display_device_info { } color; }; +bool intel_display_device_enabled(struct drm_i915_private *i915); void intel_display_device_probe(struct drm_i915_private *i915); void intel_display_device_info_runtime_init(struct drm_i915_private *i915); diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 11420595c4f9..f0f43aeabd21 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5358,7 +5358,7 @@ intel_dp_detect(struct drm_connector *connector, drm_WARN_ON(&dev_priv->drm, !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); - if (!INTEL_DISPLAY_ENABLED(dev_priv)) + if (!intel_display_device_enabled(dev_priv)) return connector_status_disconnected; /* Can't disconnect eDP */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 59a4a36264cf..c27f82872c55 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1056,7 +1056,7 @@ intel_dp_mst_detect(struct drm_connector *connector, struct intel_connector *intel_connector = to_intel_connector(connector); struct intel_dp *intel_dp = intel_connector->mst_port; - if (!INTEL_DISPLAY_ENABLED(i915)) + if (!intel_display_device_enabled(i915)) return connector_status_disconnected; if (drm_connector_is_unregistered(connector)) diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c index d9f427856fb8..55d6743374bd 100644 --- a/drivers/gpu/drm/i915/display/intel_dvo.c +++ b/drivers/gpu/drm/i915/display/intel_dvo.c @@ -319,7 +319,7 @@ intel_dvo_detect(struct drm_connector *_connector, bool force) drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", connector->base.base.id, connector->base.name); - if (!INTEL_DISPLAY_ENABLED(i915)) + if (!intel_display_device_enabled(i915)) return connector_status_disconnected; return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index af4102e91769..ac315f8e7820 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -2496,7 +2496,7 @@ intel_hdmi_detect(struct drm_connector *connector, bool force) drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", connector->base.id, connector->name); - if (!INTEL_DISPLAY_ENABLED(dev_priv)) + if (!intel_display_device_enabled(dev_priv)) return connector_status_disconnected; wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c index e8562f6f8bb4..0c0700c6ec66 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c @@ -763,7 +763,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work) void intel_hpd_poll_enable(struct drm_i915_private *dev_priv) { if (!HAS_DISPLAY(dev_priv) || - !INTEL_DISPLAY_ENABLED(dev_priv)) + !intel_display_device_enabled(dev_priv)) return; WRITE_ONCE(dev_priv->display.hotplug.poll_enabled, true); diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 086cb8dbe22c..483beedac5b8 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -680,7 +680,7 @@ intel_panel_detect(struct drm_connector *connector, bool force) { struct drm_i915_private *i915 = to_i915(connector->dev); - if (!INTEL_DISPLAY_ENABLED(i915)) + if (!intel_display_device_enabled(i915)) return connector_status_disconnected; return connector_status_connected; diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c index 950ba0431f5f..35137e978591 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.c +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c @@ -2121,7 +2121,7 @@ intel_sdvo_detect(struct drm_connector *connector, bool force) DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, connector->name); - if (!INTEL_DISPLAY_ENABLED(i915)) + if (!intel_display_device_enabled(i915)) return connector_status_disconnected; if (!intel_sdvo_set_target_output(intel_sdvo, diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c index 36b479b46b60..31a79fdfc812 100644 --- a/drivers/gpu/drm/i915/display/intel_tv.c +++ b/drivers/gpu/drm/i915/display/intel_tv.c @@ -1720,7 +1720,7 @@ intel_tv_detect(struct drm_connector *connector, drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] force=%d\n", connector->base.id, connector->name, force); - if (!INTEL_DISPLAY_ENABLED(i915)) + if (!intel_display_device_enabled(i915)) return connector_status_disconnected; if (force) { diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index cc229f08dfdb..8f1594d43ad6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -821,12 +821,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define NUM_L3_SLICES(i915) (IS_HASWELL_GT3(i915) ? \ 2 : HAS_L3_DPF(i915)) -/* Only valid when HAS_DISPLAY() is true */ -#define INTEL_DISPLAY_ENABLED(i915) \ - (drm_WARN_ON(&(i915)->drm, !HAS_DISPLAY(i915)), \ - !(i915)->params.disable_display && \ - !intel_opregion_headless_sku(i915)) - #define HAS_GUC_DEPRIVILEGE(i915) \ (INTEL_INFO(i915)->has_guc_deprivilege) From 5e72e75d30fcff599e306fc9987eed8639c4a84a Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 3 Oct 2023 15:42:08 +0300 Subject: [PATCH 27/82] drm/i915: move display info related macros to display MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Anything looking at display (runtime) info should be under display. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/41b53870ffa7bd41ccc337616c756c69326f05cf.1696336887.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_display_device.h | 9 +++++++++ drivers/gpu/drm/i915/i915_drv.h | 8 -------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 8977bac8cb7f..5b5c0e53307f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -98,6 +98,15 @@ struct drm_printer; (IS_DISPLAY_IP_RANGE((__i915), (ipver), (ipver)) && \ IS_DISPLAY_STEP((__i915), (from), (until))) +#define DISPLAY_INFO(i915) ((i915)->display.info.__device_info) +#define DISPLAY_RUNTIME_INFO(i915) (&(i915)->display.info.__runtime_info) + +#define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver) +#define DISPLAY_VER_FULL(i915) IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \ + DISPLAY_RUNTIME_INFO(i915)->ip.rel) +#define IS_DISPLAY_VER(i915, from, until) \ + (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) + struct intel_display_runtime_info { struct { u16 ver; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 8f1594d43ad6..e4d791ad6751 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -416,8 +416,6 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) #define INTEL_INFO(i915) ((i915)->__info) #define RUNTIME_INFO(i915) (&(i915)->__runtime) -#define DISPLAY_INFO(i915) ((i915)->display.info.__device_info) -#define DISPLAY_RUNTIME_INFO(i915) (&(i915)->display.info.__runtime_info) #define DRIVER_CAPS(i915) (&(i915)->caps) #define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id) @@ -436,12 +434,6 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) #define IS_MEDIA_VER(i915, from, until) \ (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) -#define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver) -#define DISPLAY_VER_FULL(i915) IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \ - DISPLAY_RUNTIME_INFO(i915)->ip.rel) -#define IS_DISPLAY_VER(i915, from, until) \ - (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) - #define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision) #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step) From b8eed6a4aee4f85ed0465b233b63e2b233a420b9 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 3 Oct 2023 15:42:09 +0300 Subject: [PATCH 28/82] drm/i915: separate display runtime info init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move display related functionality from intel_device_info_runtime_init() to intel_display_device_info_runtime_init() and call the latter from the top level. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/a2226a47a4450e75d867c2ac48665b387af0e42d.1696336887.git.jani.nikula@intel.com --- .../drm/i915/display/intel_display_device.c | 19 ++++++++++++++++++- drivers/gpu/drm/i915/i915_driver.c | 1 + drivers/gpu/drm/i915/intel_device_info.c | 17 ----------------- 3 files changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index dea64c99721e..11f4a6c54cc7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -939,7 +939,7 @@ void intel_display_device_probe(struct drm_i915_private *i915) } } -void intel_display_device_info_runtime_init(struct drm_i915_private *i915) +static void __intel_display_device_info_runtime_init(struct drm_i915_private *i915) { struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915); enum pipe pipe; @@ -1071,6 +1071,23 @@ display_fused_off: memset(display_runtime, 0, sizeof(*display_runtime)); } +void intel_display_device_info_runtime_init(struct drm_i915_private *i915) +{ + if (HAS_DISPLAY(i915)) + __intel_display_device_info_runtime_init(i915); + + /* Display may have been disabled by runtime init */ + if (!HAS_DISPLAY(i915)) { + i915->drm.driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC); + i915->display.info.__device_info = &no_display; + } + + /* Disable nuclear pageflip by default on pre-g4x */ + if (!i915->params.nuclear_pageflip && + DISPLAY_VER(i915) < 5 && !IS_G4X(i915)) + i915->drm.driver_features &= ~DRIVER_ATOMIC; +} + void intel_display_device_info_print(const struct intel_display_device_info *info, const struct intel_display_runtime_info *runtime, struct drm_printer *p) diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index d50347e5773a..f30a0861541c 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -338,6 +338,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) /* Try to make sure MCHBAR is enabled before poking at it */ intel_gmch_bar_setup(dev_priv); intel_device_info_runtime_init(dev_priv); + intel_display_device_info_runtime_init(dev_priv); for_each_gt(gt, dev_priv, i) { ret = intel_gt_init_mmio(gt); diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 61d788cd5abb..f0687776bb6d 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -364,8 +364,6 @@ void intel_device_info_runtime_init_early(struct drm_i915_private *i915) intel_device_info_subplatform_init(i915); } -static const struct intel_display_device_info no_display = {}; - /** * intel_device_info_runtime_init - initialize runtime info * @dev_priv: the i915 device @@ -386,21 +384,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) { struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); - if (HAS_DISPLAY(dev_priv)) - intel_display_device_info_runtime_init(dev_priv); - - /* Display may have been disabled by runtime init */ - if (!HAS_DISPLAY(dev_priv)) { - dev_priv->drm.driver_features &= ~(DRIVER_MODESET | - DRIVER_ATOMIC); - dev_priv->display.info.__device_info = &no_display; - } - - /* Disable nuclear pageflip by default on pre-g4x */ - if (!dev_priv->params.nuclear_pageflip && - DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) - dev_priv->drm.driver_features &= ~DRIVER_ATOMIC; - BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) { From 079d0b01bc5943dd19c7cb8fa9a99976217cc4c6 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 3 Oct 2023 15:42:10 +0300 Subject: [PATCH 29/82] drm/i915: separate subplatform init and runtime feature init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adjusting ->port_mask does not belong in intel_device_info_subplatform_init(), but rather intel_display_device_info_runtime_init(). Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/1035800e623e13d5e7baf1215b07e7cdad5eb764.1696336887.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_display_device.c | 7 +++++++ drivers/gpu/drm/i915/intel_device_info.c | 5 ----- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 11f4a6c54cc7..9f0266318a41 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -948,6 +948,13 @@ static void __intel_display_device_info_runtime_init(struct drm_i915_private *i9 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->cpu_transcoder_mask) < I915_MAX_TRANSCODERS); BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->port_mask) < I915_MAX_PORTS); + /* This covers both ULT and ULX */ + if (IS_HASWELL_ULT(i915) || IS_BROADWELL_ULT(i915)) + display_runtime->port_mask &= ~BIT(PORT_D); + + if (IS_ICL_WITH_PORT_F(i915)) + display_runtime->port_mask |= BIT(PORT_F); + /* Wa_14011765242: adl-s A0,A1 */ if (IS_ALDERLAKE_S(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_A2)) for_each_pipe(i915, pipe) diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index f0687776bb6d..64295e6702b0 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -27,7 +27,6 @@ #include #include -#include "display/intel_display_device.h" #include "gt/intel_gt_regs.h" #include "i915_drv.h" #include "i915_reg.h" @@ -240,19 +239,15 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915) if (find_devid(devid, subplatform_ult_ids, ARRAY_SIZE(subplatform_ult_ids))) { mask = BIT(INTEL_SUBPLATFORM_ULT); - if (IS_HASWELL(i915) || IS_BROADWELL(i915)) - DISPLAY_RUNTIME_INFO(i915)->port_mask &= ~BIT(PORT_D); } else if (find_devid(devid, subplatform_ulx_ids, ARRAY_SIZE(subplatform_ulx_ids))) { mask = BIT(INTEL_SUBPLATFORM_ULX); if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { /* ULX machines are also considered ULT. */ mask |= BIT(INTEL_SUBPLATFORM_ULT); - DISPLAY_RUNTIME_INFO(i915)->port_mask &= ~BIT(PORT_D); } } else if (find_devid(devid, subplatform_portf_ids, ARRAY_SIZE(subplatform_portf_ids))) { - DISPLAY_RUNTIME_INFO(i915)->port_mask |= BIT(PORT_F); mask = BIT(INTEL_SUBPLATFORM_PORTF); } else if (find_devid(devid, subplatform_uy_ids, ARRAY_SIZE(subplatform_uy_ids))) { From 027c57017795de145b8800f00665aae9a313ab26 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 3 Oct 2023 23:06:17 +0300 Subject: [PATCH 30/82] drm/i915: Stop requiring PLL index == PLL ID MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There's no good reason to keep around this PLL index == PLL ID footgun. Get rid of it. Both i915->shared_dplls[] and state->shared_dpll[] are indexed by the same thing now, which is just the index we get at initialization from dpll_mgr->dpll_info[]. The rest is all about PLL IDs now. v2: Add pll->index to mimic drm_crtc & co. Remove the comment saying ID should match the index v3: s/i/pll->index/ in debugfs loop (Jani) Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20231003200620.11633-2-ville.syrjala@linux.intel.com --- .../drm/i915/display/intel_display_debugfs.c | 4 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 63 +++++++++++-------- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 8 ++- .../gpu/drm/i915/display/intel_pch_refclk.c | 5 +- 4 files changed, 48 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index f05b52381a83..670a38aebd0c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -656,8 +656,8 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused) for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; - seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name, - pll->info->id); + seq_printf(m, "DPLL%i: %s, id: %i\n", pll->index, + pll->info->name, pll->info->id); seq_printf(m, " pipe_mask: 0x%x, active: 0x%x, on: %s\n", pll->state.pipe_mask, pll->active_mask, str_yes_no(pll->on)); diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 6d68b36292d3..614fdc21bde0 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -115,13 +115,13 @@ static void intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv, struct intel_shared_dpll_state *shared_dpll) { - enum intel_dpll_id i; + int i; /* Copy shared dpll state */ for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; - shared_dpll[i] = pll->state; + shared_dpll[pll->index] = pll->state; } } @@ -154,7 +154,17 @@ struct intel_shared_dpll * intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, enum intel_dpll_id id) { - return &dev_priv->display.dpll.shared_dplls[id]; + int i; + + for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { + struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; + + if (pll->info->id == id) + return pll; + } + + MISSING_CASE(id); + return NULL; } /* For ILK+ */ @@ -311,32 +321,36 @@ intel_find_shared_dpll(struct intel_atomic_state *state, unsigned long dpll_mask) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_shared_dpll *pll, *unused_pll = NULL; struct intel_shared_dpll_state *shared_dpll; - enum intel_dpll_id i; + struct intel_shared_dpll *unused_pll = NULL; + enum intel_dpll_id id; shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1)); - for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) { - pll = &dev_priv->display.dpll.shared_dplls[i]; + for_each_set_bit(id, &dpll_mask, I915_NUM_PLLS) { + struct intel_shared_dpll *pll; + + pll = intel_get_shared_dpll_by_id(dev_priv, id); + if (!pll) + continue; /* Only want to check enabled timings first */ - if (shared_dpll[i].pipe_mask == 0) { + if (shared_dpll[pll->index].pipe_mask == 0) { if (!unused_pll) unused_pll = pll; continue; } if (memcmp(pll_state, - &shared_dpll[i].hw_state, + &shared_dpll[pll->index].hw_state, sizeof(*pll_state)) == 0) { drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n", crtc->base.base.id, crtc->base.name, pll->info->name, - shared_dpll[i].pipe_mask, + shared_dpll[pll->index].pipe_mask, pll->active_mask); return pll; } @@ -383,14 +397,13 @@ intel_reference_shared_dpll(struct intel_atomic_state *state, const struct intel_dpll_hw_state *pll_state) { struct intel_shared_dpll_state *shared_dpll; - const enum intel_dpll_id id = pll->info->id; shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); - if (shared_dpll[id].pipe_mask == 0) - shared_dpll[id].hw_state = *pll_state; + if (shared_dpll[pll->index].pipe_mask == 0) + shared_dpll[pll->index].hw_state = *pll_state; - intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[id]); + intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]); } /** @@ -421,11 +434,10 @@ static void intel_unreference_shared_dpll(struct intel_atomic_state *state, const struct intel_shared_dpll *pll) { struct intel_shared_dpll_state *shared_dpll; - const enum intel_dpll_id id = pll->info->id; shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); - intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[id]); + intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]); } static void intel_put_dpll(struct intel_atomic_state *state, @@ -459,16 +471,15 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_shared_dpll_state *shared_dpll = state->shared_dpll; - enum intel_dpll_id i; + int i; if (!state->dpll_set) return; for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { - struct intel_shared_dpll *pll = - &dev_priv->display.dpll.shared_dplls[i]; + struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; - swap(pll->state, shared_dpll[i]); + swap(pll->state, shared_dpll[pll->index]); } } @@ -559,12 +570,12 @@ static int ibx_get_dpll(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_shared_dpll *pll; - enum intel_dpll_id i; + enum intel_dpll_id id; if (HAS_PCH_IBX(dev_priv)) { /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ - i = (enum intel_dpll_id) crtc->pipe; - pll = &dev_priv->display.dpll.shared_dplls[i]; + id = (enum intel_dpll_id) crtc->pipe; + pll = intel_get_shared_dpll_by_id(dev_priv, id); drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] using pre-allocated %s\n", @@ -4168,10 +4179,8 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv) else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) dpll_mgr = &pch_pll_mgr; - if (!dpll_mgr) { - dev_priv->display.dpll.num_shared_dpll = 0; + if (!dpll_mgr) return; - } dpll_info = dpll_mgr->dpll_info; @@ -4180,8 +4189,8 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv) i >= ARRAY_SIZE(dev_priv->display.dpll.shared_dplls))) break; - drm_WARN_ON(&dev_priv->drm, i != dpll_info[i].id); dev_priv->display.dpll.shared_dplls[i].info = &dpll_info[i]; + dev_priv->display.dpll.shared_dplls[i].index = i; } dev_priv->display.dpll.mgr = dpll_mgr; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index 04e6810954b2..53d5dfede5ec 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -262,8 +262,7 @@ struct dpll_info { const struct intel_shared_dpll_funcs *funcs; /** - * @id: unique indentifier for this DPLL; should match the index in the - * dev_priv->shared_dplls array + * @id: unique indentifier for this DPLL */ enum intel_dpll_id id; @@ -290,6 +289,11 @@ struct intel_shared_dpll { */ struct intel_shared_dpll_state state; + /** + * @index: index for atomic state + */ + u8 index; + /** * @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL */ diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c index 9583e86b602a..c6a03abf44ca 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c @@ -528,7 +528,10 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) /* Check if any DPLLs are using the SSC source */ for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { - u32 temp = intel_de_read(dev_priv, PCH_DPLL(i)); + struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; + u32 temp; + + temp = intel_de_read(dev_priv, PCH_DPLL(pll->info->id)); if (!(temp & DPLL_VCO_ENABLE)) continue; From 99e5a010e8153bf2454ceefe725fea5de72e7d64 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 3 Oct 2023 23:06:18 +0300 Subject: [PATCH 31/82] drm/i915: Decouple I915_NUM_PLLS from PLL IDs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Stop assuming the size of PLL ID based bitmask is restricted to I915_NUM_PLLS bits. This is the last thing coupling the two things together and thus artificially limiting PLL IDs. We could just pass any arbitrary (large enough) size to for_each_set_bit() and be done with it, but the WARN requiring the caller to not pass in a bogus bitmask seems potentially useful to keep around. So let's just calculate the full bitmask on the spot. And while at it let's assert that the PLL IDs will fit into the bitmask we use for them. TODO: could also get rid of I915_NUM_PLLS entirely and just dynamically allocate i915->shared_dplls[] and state->shared_dpll[]. But that would involve error handling in the modeset init path. Uff. v2: Warn about conflicting PLL IDs (Jani) Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20231003200620.11633-3-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 26 +++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 614fdc21bde0..5b0ad34132c6 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -314,6 +314,23 @@ out: mutex_unlock(&dev_priv->display.dpll.lock); } +static unsigned long +intel_dpll_mask_all(struct drm_i915_private *i915) +{ + unsigned long dpll_mask = 0; + int i; + + for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) { + struct intel_shared_dpll *pll = &i915->display.dpll.shared_dplls[i]; + + drm_WARN_ON(&i915->drm, dpll_mask & BIT(pll->info->id)); + + dpll_mask |= BIT(pll->info->id); + } + + return dpll_mask; +} + static struct intel_shared_dpll * intel_find_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, @@ -321,15 +338,16 @@ intel_find_shared_dpll(struct intel_atomic_state *state, unsigned long dpll_mask) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + unsigned long dpll_mask_all = intel_dpll_mask_all(dev_priv); struct intel_shared_dpll_state *shared_dpll; struct intel_shared_dpll *unused_pll = NULL; enum intel_dpll_id id; shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); - drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1)); + drm_WARN_ON(&dev_priv->drm, dpll_mask & ~dpll_mask_all); - for_each_set_bit(id, &dpll_mask, I915_NUM_PLLS) { + for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) { struct intel_shared_dpll *pll; pll = intel_get_shared_dpll_by_id(dev_priv, id); @@ -4189,6 +4207,10 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv) i >= ARRAY_SIZE(dev_priv->display.dpll.shared_dplls))) break; + /* must fit into unsigned long bitmask on 32bit */ + if (drm_WARN_ON(&dev_priv->drm, dpll_info[i].id >= 32)) + break; + dev_priv->display.dpll.shared_dplls[i].info = &dpll_info[i]; dev_priv->display.dpll.shared_dplls[i].index = i; } From 51d3e62927193c101e02ad3ef114dbcd8f49b34a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 3 Oct 2023 23:06:19 +0300 Subject: [PATCH 32/82] drm/i915: Introduce for_each_shared_dpll() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No one really cares how we store the shared_dplls. Currently it happens to be an array, but we could change that to a more flexible scheme at some point. Hide the implementation details behind an iterator macro. The slight downside is the pll variable moving out of the loop scope, but maybe someday soon we'll start to convert everything over to having declarations within for-statements... Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20231003200620.11633-4-ville.syrjala@linux.intel.com --- .../drm/i915/display/intel_display_debugfs.c | 5 +-- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 +++++++++---------- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++ .../gpu/drm/i915/display/intel_pch_refclk.c | 4 +- 4 files changed, 25 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 670a38aebd0c..f6d7c4d45fae 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -645,6 +645,7 @@ static int i915_display_info(struct seq_file *m, void *unused) static int i915_shared_dplls_info(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct intel_shared_dpll *pll; int i; drm_modeset_lock_all(&dev_priv->drm); @@ -653,9 +654,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused) dev_priv->display.dpll.ref_clks.nssc, dev_priv->display.dpll.ref_clks.ssc); - for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { - struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; - + for_each_shared_dpll(dev_priv, pll, i) { seq_printf(m, "DPLL%i: %s, id: %i\n", pll->index, pll->info->name, pll->info->id); seq_printf(m, " pipe_mask: 0x%x, active: 0x%x, on: %s\n", diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 5b0ad34132c6..f197f91e5bf7 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -115,14 +115,12 @@ static void intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv, struct intel_shared_dpll_state *shared_dpll) { + struct intel_shared_dpll *pll; int i; /* Copy shared dpll state */ - for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { - struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; - + for_each_shared_dpll(dev_priv, pll, i) shared_dpll[pll->index] = pll->state; - } } static struct intel_shared_dpll_state * @@ -154,11 +152,10 @@ struct intel_shared_dpll * intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, enum intel_dpll_id id) { + struct intel_shared_dpll *pll; int i; - for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { - struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; - + for_each_shared_dpll(dev_priv, pll, i) { if (pll->info->id == id) return pll; } @@ -317,12 +314,11 @@ out: static unsigned long intel_dpll_mask_all(struct drm_i915_private *i915) { + struct intel_shared_dpll *pll; unsigned long dpll_mask = 0; int i; - for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) { - struct intel_shared_dpll *pll = &i915->display.dpll.shared_dplls[i]; - + for_each_shared_dpll(i915, pll, i) { drm_WARN_ON(&i915->drm, dpll_mask & BIT(pll->info->id)); dpll_mask |= BIT(pll->info->id); @@ -489,16 +485,14 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_shared_dpll_state *shared_dpll = state->shared_dpll; + struct intel_shared_dpll *pll; int i; if (!state->dpll_set) return; - for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { - struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; - + for_each_shared_dpll(dev_priv, pll, i) swap(pll->state, shared_dpll[pll->index]); - } } static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, @@ -4401,10 +4395,11 @@ void intel_dpll_update_ref_clks(struct drm_i915_private *i915) void intel_dpll_readout_hw_state(struct drm_i915_private *i915) { + struct intel_shared_dpll *pll; int i; - for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) - readout_dpll_hw_state(i915, &i915->display.dpll.shared_dplls[i]); + for_each_shared_dpll(i915, pll, i) + readout_dpll_hw_state(i915, pll); } static void sanitize_dpll_state(struct drm_i915_private *i915, @@ -4428,10 +4423,11 @@ static void sanitize_dpll_state(struct drm_i915_private *i915, void intel_dpll_sanitize_state(struct drm_i915_private *i915) { + struct intel_shared_dpll *pll; int i; - for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) - sanitize_dpll_state(i915, &i915->display.dpll.shared_dplls[i]); + for_each_shared_dpll(i915, pll, i) + sanitize_dpll_state(i915, pll); } /** @@ -4542,9 +4538,9 @@ void intel_shared_dpll_state_verify(struct intel_crtc *crtc, void intel_shared_dpll_verify_disabled(struct drm_i915_private *i915) { + struct intel_shared_dpll *pll; int i; - for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) - verify_single_dpll_state(i915, &i915->display.dpll.shared_dplls[i], - NULL, NULL); + for_each_shared_dpll(i915, pll, i) + verify_single_dpll_state(i915, pll, NULL, NULL); } diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index 53d5dfede5ec..a18ab2680a8f 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -29,6 +29,10 @@ #include "intel_wakeref.h" +#define for_each_shared_dpll(__i915, __pll, __i) \ + for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \ + ((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++) + enum tc_port; struct drm_i915_private; struct intel_atomic_state; diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c index c6a03abf44ca..713cfba71475 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c @@ -492,6 +492,7 @@ static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) { struct intel_encoder *encoder; + struct intel_shared_dpll *pll; int i; u32 val, final; bool has_lvds = false; @@ -527,8 +528,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) } /* Check if any DPLLs are using the SSC source */ - for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { - struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; + for_each_shared_dpll(dev_priv, pll, i) { u32 temp; temp = intel_de_read(dev_priv, PCH_DPLL(pll->info->id)); From 25591b66d0a4f9277241cebe1a74b4f985bc27a9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 3 Oct 2023 23:06:20 +0300 Subject: [PATCH 33/82] drm/i915: s/dev_priv/i915/ in the shared_dpll code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do a s/dev_priv/i915/ pass over the shared_dpll code to get the variable names into sync with modern standards. v2: Rebase Reviewed-by: Jani Nikula #v1 Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20231003200620.11633-5-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 880 +++++++++--------- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 14 +- 2 files changed, 447 insertions(+), 447 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index f197f91e5bf7..86cdd8c9f2d8 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -107,19 +107,19 @@ struct intel_dpll_mgr { struct intel_crtc *crtc, struct intel_encoder *encoder); void (*update_ref_clks)(struct drm_i915_private *i915); - void (*dump_hw_state)(struct drm_i915_private *dev_priv, + void (*dump_hw_state)(struct drm_i915_private *i915, const struct intel_dpll_hw_state *hw_state); }; static void -intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv, +intel_atomic_duplicate_dpll_state(struct drm_i915_private *i915, struct intel_shared_dpll_state *shared_dpll) { struct intel_shared_dpll *pll; int i; /* Copy shared dpll state */ - for_each_shared_dpll(dev_priv, pll, i) + for_each_shared_dpll(i915, pll, i) shared_dpll[pll->index] = pll->state; } @@ -142,20 +142,20 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s) /** * intel_get_shared_dpll_by_id - get a DPLL given its id - * @dev_priv: i915 device instance + * @i915: i915 device instance * @id: pll id * * Returns: * A pointer to the DPLL with @id */ struct intel_shared_dpll * -intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, +intel_get_shared_dpll_by_id(struct drm_i915_private *i915, enum intel_dpll_id id) { struct intel_shared_dpll *pll; int i; - for_each_shared_dpll(dev_priv, pll, i) { + for_each_shared_dpll(i915, pll, i) { if (pll->info->id == id) return pll; } @@ -165,19 +165,19 @@ intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, } /* For ILK+ */ -void assert_shared_dpll(struct drm_i915_private *dev_priv, +void assert_shared_dpll(struct drm_i915_private *i915, struct intel_shared_dpll *pll, bool state) { bool cur_state; struct intel_dpll_hw_state hw_state; - if (drm_WARN(&dev_priv->drm, !pll, + if (drm_WARN(&i915->drm, !pll, "asserting DPLL %s with no DPLL\n", str_on_off(state))) return; - cur_state = intel_dpll_get_hw_state(dev_priv, pll, &hw_state); - I915_STATE_WARN(dev_priv, cur_state != state, + cur_state = intel_dpll_get_hw_state(i915, pll, &hw_state); + I915_STATE_WARN(i915, cur_state != state, "%s assertion failure (expected %s, current %s)\n", pll->info->name, str_on_off(state), str_on_off(cur_state)); @@ -228,41 +228,41 @@ intel_tc_pll_enable_reg(struct drm_i915_private *i915, void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_shared_dpll *pll = crtc_state->shared_dpll; unsigned int pipe_mask = BIT(crtc->pipe); unsigned int old_mask; - if (drm_WARN_ON(&dev_priv->drm, pll == NULL)) + if (drm_WARN_ON(&i915->drm, pll == NULL)) return; - mutex_lock(&dev_priv->display.dpll.lock); + mutex_lock(&i915->display.dpll.lock); old_mask = pll->active_mask; - if (drm_WARN_ON(&dev_priv->drm, !(pll->state.pipe_mask & pipe_mask)) || - drm_WARN_ON(&dev_priv->drm, pll->active_mask & pipe_mask)) + if (drm_WARN_ON(&i915->drm, !(pll->state.pipe_mask & pipe_mask)) || + drm_WARN_ON(&i915->drm, pll->active_mask & pipe_mask)) goto out; pll->active_mask |= pipe_mask; - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(&i915->drm, "enable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n", pll->info->name, pll->active_mask, pll->on, crtc->base.base.id, crtc->base.name); if (old_mask) { - drm_WARN_ON(&dev_priv->drm, !pll->on); - assert_shared_dpll_enabled(dev_priv, pll); + drm_WARN_ON(&i915->drm, !pll->on); + assert_shared_dpll_enabled(i915, pll); goto out; } - drm_WARN_ON(&dev_priv->drm, pll->on); + drm_WARN_ON(&i915->drm, pll->on); - drm_dbg_kms(&dev_priv->drm, "enabling %s\n", pll->info->name); - pll->info->funcs->enable(dev_priv, pll); + drm_dbg_kms(&i915->drm, "enabling %s\n", pll->info->name); + pll->info->funcs->enable(i915, pll); pll->on = true; out: - mutex_unlock(&dev_priv->display.dpll.lock); + mutex_unlock(&i915->display.dpll.lock); } /** @@ -274,41 +274,41 @@ out: void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_shared_dpll *pll = crtc_state->shared_dpll; unsigned int pipe_mask = BIT(crtc->pipe); /* PCH only available on ILK+ */ - if (DISPLAY_VER(dev_priv) < 5) + if (DISPLAY_VER(i915) < 5) return; if (pll == NULL) return; - mutex_lock(&dev_priv->display.dpll.lock); - if (drm_WARN(&dev_priv->drm, !(pll->active_mask & pipe_mask), + mutex_lock(&i915->display.dpll.lock); + if (drm_WARN(&i915->drm, !(pll->active_mask & pipe_mask), "%s not used by [CRTC:%d:%s]\n", pll->info->name, crtc->base.base.id, crtc->base.name)) goto out; - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(&i915->drm, "disable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n", pll->info->name, pll->active_mask, pll->on, crtc->base.base.id, crtc->base.name); - assert_shared_dpll_enabled(dev_priv, pll); - drm_WARN_ON(&dev_priv->drm, !pll->on); + assert_shared_dpll_enabled(i915, pll); + drm_WARN_ON(&i915->drm, !pll->on); pll->active_mask &= ~pipe_mask; if (pll->active_mask) goto out; - drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name); - pll->info->funcs->disable(dev_priv, pll); + drm_dbg_kms(&i915->drm, "disabling %s\n", pll->info->name); + pll->info->funcs->disable(i915, pll); pll->on = false; out: - mutex_unlock(&dev_priv->display.dpll.lock); + mutex_unlock(&i915->display.dpll.lock); } static unsigned long @@ -333,20 +333,20 @@ intel_find_shared_dpll(struct intel_atomic_state *state, const struct intel_dpll_hw_state *pll_state, unsigned long dpll_mask) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - unsigned long dpll_mask_all = intel_dpll_mask_all(dev_priv); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + unsigned long dpll_mask_all = intel_dpll_mask_all(i915); struct intel_shared_dpll_state *shared_dpll; struct intel_shared_dpll *unused_pll = NULL; enum intel_dpll_id id; shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); - drm_WARN_ON(&dev_priv->drm, dpll_mask & ~dpll_mask_all); + drm_WARN_ON(&i915->drm, dpll_mask & ~dpll_mask_all); for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) { struct intel_shared_dpll *pll; - pll = intel_get_shared_dpll_by_id(dev_priv, id); + pll = intel_get_shared_dpll_by_id(i915, id); if (!pll) continue; @@ -360,7 +360,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state, if (memcmp(pll_state, &shared_dpll[pll->index].hw_state, sizeof(*pll_state)) == 0) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n", crtc->base.base.id, crtc->base.name, pll->info->name, @@ -372,7 +372,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state, /* Ok no matching timings, maybe there's a free one? */ if (unused_pll) { - drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] allocated %s\n", + drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] allocated %s\n", crtc->base.base.id, crtc->base.name, unused_pll->info->name); return unused_pll; @@ -483,7 +483,7 @@ static void intel_put_dpll(struct intel_atomic_state *state, */ void intel_shared_dpll_swap_state(struct intel_atomic_state *state) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct drm_i915_private *i915 = to_i915(state->base.dev); struct intel_shared_dpll_state *shared_dpll = state->shared_dpll; struct intel_shared_dpll *pll; int i; @@ -491,11 +491,11 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state) if (!state->dpll_set) return; - for_each_shared_dpll(dev_priv, pll, i) + for_each_shared_dpll(i915, pll, i) swap(pll->state, shared_dpll[pll->index]); } -static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, +static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { @@ -503,48 +503,48 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, intel_wakeref_t wakeref; u32 val; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; - val = intel_de_read(dev_priv, PCH_DPLL(id)); + val = intel_de_read(i915, PCH_DPLL(id)); hw_state->dpll = val; - hw_state->fp0 = intel_de_read(dev_priv, PCH_FP0(id)); - hw_state->fp1 = intel_de_read(dev_priv, PCH_FP1(id)); + hw_state->fp0 = intel_de_read(i915, PCH_FP0(id)); + hw_state->fp1 = intel_de_read(i915, PCH_FP1(id)); - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); return val & DPLL_VCO_ENABLE; } -static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) +static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915) { u32 val; bool enabled; - val = intel_de_read(dev_priv, PCH_DREF_CONTROL); + val = intel_de_read(i915, PCH_DREF_CONTROL); enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | DREF_SUPERSPREAD_SOURCE_MASK)); - I915_STATE_WARN(dev_priv, !enabled, + I915_STATE_WARN(i915, !enabled, "PCH refclk assertion failure, should be active but is disabled\n"); } -static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, +static void ibx_pch_dpll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { const enum intel_dpll_id id = pll->info->id; /* PCH refclock must be enabled first */ - ibx_assert_pch_refclk_enabled(dev_priv); + ibx_assert_pch_refclk_enabled(i915); - intel_de_write(dev_priv, PCH_FP0(id), pll->state.hw_state.fp0); - intel_de_write(dev_priv, PCH_FP1(id), pll->state.hw_state.fp1); + intel_de_write(i915, PCH_FP0(id), pll->state.hw_state.fp0); + intel_de_write(i915, PCH_FP1(id), pll->state.hw_state.fp1); - intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); + intel_de_write(i915, PCH_DPLL(id), pll->state.hw_state.dpll); /* Wait for the clocks to stabilize. */ - intel_de_posting_read(dev_priv, PCH_DPLL(id)); + intel_de_posting_read(i915, PCH_DPLL(id)); udelay(150); /* The pixel multiplier can only be updated once the @@ -552,18 +552,18 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, * * So write it again. */ - intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); - intel_de_posting_read(dev_priv, PCH_DPLL(id)); + intel_de_write(i915, PCH_DPLL(id), pll->state.hw_state.dpll); + intel_de_posting_read(i915, PCH_DPLL(id)); udelay(200); } -static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, +static void ibx_pch_dpll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { const enum intel_dpll_id id = pll->info->id; - intel_de_write(dev_priv, PCH_DPLL(id), 0); - intel_de_posting_read(dev_priv, PCH_DPLL(id)); + intel_de_write(i915, PCH_DPLL(id), 0); + intel_de_posting_read(i915, PCH_DPLL(id)); udelay(200); } @@ -580,16 +580,16 @@ static int ibx_get_dpll(struct intel_atomic_state *state, { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_shared_dpll *pll; enum intel_dpll_id id; - if (HAS_PCH_IBX(dev_priv)) { + if (HAS_PCH_IBX(i915)) { /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ id = (enum intel_dpll_id) crtc->pipe; - pll = intel_get_shared_dpll_by_id(dev_priv, id); + pll = intel_get_shared_dpll_by_id(i915, id); - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] using pre-allocated %s\n", crtc->base.base.id, crtc->base.name, pll->info->name); @@ -612,10 +612,10 @@ static int ibx_get_dpll(struct intel_atomic_state *state, return 0; } -static void ibx_dump_hw_state(struct drm_i915_private *dev_priv, +static void ibx_dump_hw_state(struct drm_i915_private *i915, const struct intel_dpll_hw_state *hw_state) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(&i915->drm, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " "fp0: 0x%x, fp1: 0x%x\n", hw_state->dpll, @@ -644,57 +644,57 @@ static const struct intel_dpll_mgr pch_pll_mgr = { .dump_hw_state = ibx_dump_hw_state, }; -static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv, +static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { const enum intel_dpll_id id = pll->info->id; - intel_de_write(dev_priv, WRPLL_CTL(id), pll->state.hw_state.wrpll); - intel_de_posting_read(dev_priv, WRPLL_CTL(id)); + intel_de_write(i915, WRPLL_CTL(id), pll->state.hw_state.wrpll); + intel_de_posting_read(i915, WRPLL_CTL(id)); udelay(20); } -static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv, +static void hsw_ddi_spll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { - intel_de_write(dev_priv, SPLL_CTL, pll->state.hw_state.spll); - intel_de_posting_read(dev_priv, SPLL_CTL); + intel_de_write(i915, SPLL_CTL, pll->state.hw_state.spll); + intel_de_posting_read(i915, SPLL_CTL); udelay(20); } -static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, +static void hsw_ddi_wrpll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { const enum intel_dpll_id id = pll->info->id; - intel_de_rmw(dev_priv, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0); - intel_de_posting_read(dev_priv, WRPLL_CTL(id)); + intel_de_rmw(i915, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0); + intel_de_posting_read(i915, WRPLL_CTL(id)); /* * Try to set up the PCH reference clock once all DPLLs * that depend on it have been shut down. */ - if (dev_priv->display.dpll.pch_ssc_use & BIT(id)) - intel_init_pch_refclk(dev_priv); + if (i915->display.dpll.pch_ssc_use & BIT(id)) + intel_init_pch_refclk(i915); } -static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, +static void hsw_ddi_spll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { enum intel_dpll_id id = pll->info->id; - intel_de_rmw(dev_priv, SPLL_CTL, SPLL_PLL_ENABLE, 0); - intel_de_posting_read(dev_priv, SPLL_CTL); + intel_de_rmw(i915, SPLL_CTL, SPLL_PLL_ENABLE, 0); + intel_de_posting_read(i915, SPLL_CTL); /* * Try to set up the PCH reference clock once all DPLLs * that depend on it have been shut down. */ - if (dev_priv->display.dpll.pch_ssc_use & BIT(id)) - intel_init_pch_refclk(dev_priv); + if (i915->display.dpll.pch_ssc_use & BIT(id)) + intel_init_pch_refclk(i915); } -static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, +static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { @@ -702,35 +702,35 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, intel_wakeref_t wakeref; u32 val; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; - val = intel_de_read(dev_priv, WRPLL_CTL(id)); + val = intel_de_read(i915, WRPLL_CTL(id)); hw_state->wrpll = val; - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); return val & WRPLL_PLL_ENABLE; } -static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, +static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { intel_wakeref_t wakeref; u32 val; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; - val = intel_de_read(dev_priv, SPLL_CTL); + val = intel_de_read(i915, SPLL_CTL); hw_state->spll = val; - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); return val & SPLL_PLL_ENABLE; } @@ -941,7 +941,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */, *r2_out = best.r2; } -static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv, +static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) { @@ -952,8 +952,8 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv, switch (wrpll & WRPLL_REF_MASK) { case WRPLL_REF_SPECIAL_HSW: /* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */ - if (IS_HASWELL(dev_priv) && !IS_HASWELL_ULT(dev_priv)) { - refclk = dev_priv->display.dpll.ref_clks.nssc; + if (IS_HASWELL(i915) && !IS_HASWELL_ULT(i915)) { + refclk = i915->display.dpll.ref_clks.nssc; break; } fallthrough; @@ -963,7 +963,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv, * code only cares about 5% accuracy, and spread is a max of * 0.5% downspread. */ - refclk = dev_priv->display.dpll.ref_clks.ssc; + refclk = i915->display.dpll.ref_clks.ssc; break; case WRPLL_REF_LCPLL: refclk = 2700000; @@ -1019,7 +1019,7 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state, static int hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); int clock = crtc_state->port_clock; switch (clock / 2) { @@ -1028,7 +1028,7 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state) case 270000: return 0; default: - drm_dbg_kms(&dev_priv->drm, "Invalid clock for DP: %d\n", + drm_dbg_kms(&i915->drm, "Invalid clock for DP: %d\n", clock); return -EINVAL; } @@ -1037,7 +1037,7 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state) static struct intel_shared_dpll * hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); struct intel_shared_dpll *pll; enum intel_dpll_id pll_id; int clock = crtc_state->port_clock; @@ -1057,7 +1057,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state) return NULL; } - pll = intel_get_shared_dpll_by_id(dev_priv, pll_id); + pll = intel_get_shared_dpll_by_id(i915, pll_id); if (!pll) return NULL; @@ -1193,10 +1193,10 @@ static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915) i915->display.dpll.ref_clks.nssc = 135000; } -static void hsw_dump_hw_state(struct drm_i915_private *dev_priv, +static void hsw_dump_hw_state(struct drm_i915_private *i915, const struct intel_dpll_hw_state *hw_state) { - drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", + drm_dbg_kms(&i915->drm, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", hw_state->wrpll, hw_state->spll); } @@ -1214,17 +1214,17 @@ static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = { .get_freq = hsw_ddi_spll_get_freq, }; -static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv, +static void hsw_ddi_lcpll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { } -static void hsw_ddi_lcpll_disable(struct drm_i915_private *dev_priv, +static void hsw_ddi_lcpll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { } -static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *dev_priv, +static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { @@ -1288,60 +1288,60 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = { }, }; -static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv, +static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { const enum intel_dpll_id id = pll->info->id; - intel_de_rmw(dev_priv, DPLL_CTRL1, + intel_de_rmw(i915, DPLL_CTRL1, DPLL_CTRL1_HDMI_MODE(id) | DPLL_CTRL1_SSC(id) | DPLL_CTRL1_LINK_RATE_MASK(id), pll->state.hw_state.ctrl1 << (id * 6)); - intel_de_posting_read(dev_priv, DPLL_CTRL1); + intel_de_posting_read(i915, DPLL_CTRL1); } -static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, +static void skl_ddi_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { const struct skl_dpll_regs *regs = skl_dpll_regs; const enum intel_dpll_id id = pll->info->id; - skl_ddi_pll_write_ctrl1(dev_priv, pll); + skl_ddi_pll_write_ctrl1(i915, pll); - intel_de_write(dev_priv, regs[id].cfgcr1, pll->state.hw_state.cfgcr1); - intel_de_write(dev_priv, regs[id].cfgcr2, pll->state.hw_state.cfgcr2); - intel_de_posting_read(dev_priv, regs[id].cfgcr1); - intel_de_posting_read(dev_priv, regs[id].cfgcr2); + intel_de_write(i915, regs[id].cfgcr1, pll->state.hw_state.cfgcr1); + intel_de_write(i915, regs[id].cfgcr2, pll->state.hw_state.cfgcr2); + intel_de_posting_read(i915, regs[id].cfgcr1); + intel_de_posting_read(i915, regs[id].cfgcr2); /* the enable bit is always bit 31 */ - intel_de_rmw(dev_priv, regs[id].ctl, 0, LCPLL_PLL_ENABLE); + intel_de_rmw(i915, regs[id].ctl, 0, LCPLL_PLL_ENABLE); - if (intel_de_wait_for_set(dev_priv, DPLL_STATUS, DPLL_LOCK(id), 5)) - drm_err(&dev_priv->drm, "DPLL %d not locked\n", id); + if (intel_de_wait_for_set(i915, DPLL_STATUS, DPLL_LOCK(id), 5)) + drm_err(&i915->drm, "DPLL %d not locked\n", id); } -static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv, +static void skl_ddi_dpll0_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { - skl_ddi_pll_write_ctrl1(dev_priv, pll); + skl_ddi_pll_write_ctrl1(i915, pll); } -static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, +static void skl_ddi_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { const struct skl_dpll_regs *regs = skl_dpll_regs; const enum intel_dpll_id id = pll->info->id; /* the enable bit is always bit 31 */ - intel_de_rmw(dev_priv, regs[id].ctl, LCPLL_PLL_ENABLE, 0); - intel_de_posting_read(dev_priv, regs[id].ctl); + intel_de_rmw(i915, regs[id].ctl, LCPLL_PLL_ENABLE, 0); + intel_de_posting_read(i915, regs[id].ctl); } -static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv, +static void skl_ddi_dpll0_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { } -static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, +static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { @@ -1351,34 +1351,34 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, intel_wakeref_t wakeref; bool ret; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; ret = false; - val = intel_de_read(dev_priv, regs[id].ctl); + val = intel_de_read(i915, regs[id].ctl); if (!(val & LCPLL_PLL_ENABLE)) goto out; - val = intel_de_read(dev_priv, DPLL_CTRL1); + val = intel_de_read(i915, DPLL_CTRL1); hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; /* avoid reading back stale values if HDMI mode is not enabled */ if (val & DPLL_CTRL1_HDMI_MODE(id)) { - hw_state->cfgcr1 = intel_de_read(dev_priv, regs[id].cfgcr1); - hw_state->cfgcr2 = intel_de_read(dev_priv, regs[id].cfgcr2); + hw_state->cfgcr1 = intel_de_read(i915, regs[id].cfgcr1); + hw_state->cfgcr2 = intel_de_read(i915, regs[id].cfgcr2); } ret = true; out: - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } -static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv, +static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { @@ -1388,7 +1388,7 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv, u32 val; bool ret; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; @@ -1396,17 +1396,17 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv, ret = false; /* DPLL0 is always enabled since it drives CDCLK */ - val = intel_de_read(dev_priv, regs[id].ctl); - if (drm_WARN_ON(&dev_priv->drm, !(val & LCPLL_PLL_ENABLE))) + val = intel_de_read(i915, regs[id].ctl); + if (drm_WARN_ON(&i915->drm, !(val & LCPLL_PLL_ENABLE))) goto out; - val = intel_de_read(dev_priv, DPLL_CTRL1); + val = intel_de_read(i915, DPLL_CTRL1); hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; ret = true; out: - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } @@ -1896,10 +1896,10 @@ static void skl_update_dpll_ref_clks(struct drm_i915_private *i915) i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; } -static void skl_dump_hw_state(struct drm_i915_private *dev_priv, +static void skl_dump_hw_state(struct drm_i915_private *i915, const struct intel_dpll_hw_state *hw_state) { - drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: " + drm_dbg_kms(&i915->drm, "dpll_hw_state: " "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", hw_state->ctrl1, hw_state->cfgcr1, @@ -1937,129 +1937,129 @@ static const struct intel_dpll_mgr skl_pll_mgr = { .dump_hw_state = skl_dump_hw_state, }; -static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, - struct intel_shared_dpll *pll) +static void bxt_ddi_pll_enable(struct drm_i915_private *i915, + struct intel_shared_dpll *pll) { u32 temp; enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ enum dpio_phy phy; enum dpio_channel ch; - bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); + bxt_port_to_phy_channel(i915, port, &phy, &ch); /* Non-SSC reference */ - intel_de_rmw(dev_priv, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL); + intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL); - if (IS_GEMINILAKE(dev_priv)) { - intel_de_rmw(dev_priv, BXT_PORT_PLL_ENABLE(port), + if (IS_GEMINILAKE(i915)) { + intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_POWER_ENABLE); - if (wait_for_us((intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) & + if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_POWER_STATE), 200)) - drm_err(&dev_priv->drm, + drm_err(&i915->drm, "Power state not set for PLL:%d\n", port); } /* Disable 10 bit clock */ - intel_de_rmw(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), + intel_de_rmw(i915, BXT_PORT_PLL_EBB_4(phy, ch), PORT_PLL_10BIT_CLK_ENABLE, 0); /* Write P1 & P2 */ - intel_de_rmw(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch), + intel_de_rmw(i915, BXT_PORT_PLL_EBB_0(phy, ch), PORT_PLL_P1_MASK | PORT_PLL_P2_MASK, pll->state.hw_state.ebb0); /* Write M2 integer */ - intel_de_rmw(dev_priv, BXT_PORT_PLL(phy, ch, 0), + intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 0), PORT_PLL_M2_INT_MASK, pll->state.hw_state.pll0); /* Write N */ - intel_de_rmw(dev_priv, BXT_PORT_PLL(phy, ch, 1), + intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 1), PORT_PLL_N_MASK, pll->state.hw_state.pll1); /* Write M2 fraction */ - intel_de_rmw(dev_priv, BXT_PORT_PLL(phy, ch, 2), + intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 2), PORT_PLL_M2_FRAC_MASK, pll->state.hw_state.pll2); /* Write M2 fraction enable */ - intel_de_rmw(dev_priv, BXT_PORT_PLL(phy, ch, 3), + intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 3), PORT_PLL_M2_FRAC_ENABLE, pll->state.hw_state.pll3); /* Write coeff */ - temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 6)); + temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6)); temp &= ~PORT_PLL_PROP_COEFF_MASK; temp &= ~PORT_PLL_INT_COEFF_MASK; temp &= ~PORT_PLL_GAIN_CTL_MASK; temp |= pll->state.hw_state.pll6; - intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 6), temp); + intel_de_write(i915, BXT_PORT_PLL(phy, ch, 6), temp); /* Write calibration val */ - intel_de_rmw(dev_priv, BXT_PORT_PLL(phy, ch, 8), + intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 8), PORT_PLL_TARGET_CNT_MASK, pll->state.hw_state.pll8); - intel_de_rmw(dev_priv, BXT_PORT_PLL(phy, ch, 9), + intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 9), PORT_PLL_LOCK_THRESHOLD_MASK, pll->state.hw_state.pll9); - temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 10)); + temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10)); temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; temp &= ~PORT_PLL_DCO_AMP_MASK; temp |= pll->state.hw_state.pll10; - intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 10), temp); + intel_de_write(i915, BXT_PORT_PLL(phy, ch, 10), temp); /* Recalibrate with new settings */ - temp = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch)); + temp = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch)); temp |= PORT_PLL_RECALIBRATE; - intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), temp); + intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp); temp &= ~PORT_PLL_10BIT_CLK_ENABLE; temp |= pll->state.hw_state.ebb4; - intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), temp); + intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp); /* Enable PLL */ - intel_de_rmw(dev_priv, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE); - intel_de_posting_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); + intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE); + intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port)); - if (wait_for_us((intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK), + if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK), 200)) - drm_err(&dev_priv->drm, "PLL %d not locked\n", port); + drm_err(&i915->drm, "PLL %d not locked\n", port); - if (IS_GEMINILAKE(dev_priv)) { - temp = intel_de_read(dev_priv, BXT_PORT_TX_DW5_LN0(phy, ch)); + if (IS_GEMINILAKE(i915)) { + temp = intel_de_read(i915, BXT_PORT_TX_DW5_LN0(phy, ch)); temp |= DCC_DELAY_RANGE_2; - intel_de_write(dev_priv, BXT_PORT_TX_DW5_GRP(phy, ch), temp); + intel_de_write(i915, BXT_PORT_TX_DW5_GRP(phy, ch), temp); } /* * While we write to the group register to program all lanes at once we * can read only lane registers and we pick lanes 0/1 for that. */ - temp = intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN01(phy, ch)); + temp = intel_de_read(i915, BXT_PORT_PCS_DW12_LN01(phy, ch)); temp &= ~LANE_STAGGER_MASK; temp &= ~LANESTAGGER_STRAP_OVRD; temp |= pll->state.hw_state.pcsdw12; - intel_de_write(dev_priv, BXT_PORT_PCS_DW12_GRP(phy, ch), temp); + intel_de_write(i915, BXT_PORT_PCS_DW12_GRP(phy, ch), temp); } -static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, - struct intel_shared_dpll *pll) +static void bxt_ddi_pll_disable(struct drm_i915_private *i915, + struct intel_shared_dpll *pll) { enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ - intel_de_rmw(dev_priv, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0); - intel_de_posting_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); + intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0); + intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port)); - if (IS_GEMINILAKE(dev_priv)) { - intel_de_rmw(dev_priv, BXT_PORT_PLL_ENABLE(port), + if (IS_GEMINILAKE(i915)) { + intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), PORT_PLL_POWER_ENABLE, 0); - if (wait_for_us(!(intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) & + if (wait_for_us(!(intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_POWER_STATE), 200)) - drm_err(&dev_priv->drm, + drm_err(&i915->drm, "Power state not reset for PLL:%d\n", port); } } -static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, - struct intel_shared_dpll *pll, - struct intel_dpll_hw_state *hw_state) +static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915, + struct intel_shared_dpll *pll, + struct intel_dpll_hw_state *hw_state) { enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ intel_wakeref_t wakeref; @@ -2068,49 +2068,49 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, u32 val; bool ret; - bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); + bxt_port_to_phy_channel(i915, port, &phy, &ch); - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; ret = false; - val = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); + val = intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)); if (!(val & PORT_PLL_ENABLE)) goto out; - hw_state->ebb0 = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch)); + hw_state->ebb0 = intel_de_read(i915, BXT_PORT_PLL_EBB_0(phy, ch)); hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; - hw_state->ebb4 = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch)); + hw_state->ebb4 = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch)); hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; - hw_state->pll0 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0)); + hw_state->pll0 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 0)); hw_state->pll0 &= PORT_PLL_M2_INT_MASK; - hw_state->pll1 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 1)); + hw_state->pll1 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 1)); hw_state->pll1 &= PORT_PLL_N_MASK; - hw_state->pll2 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 2)); + hw_state->pll2 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 2)); hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; - hw_state->pll3 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 3)); + hw_state->pll3 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 3)); hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; - hw_state->pll6 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 6)); + hw_state->pll6 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6)); hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | PORT_PLL_INT_COEFF_MASK | PORT_PLL_GAIN_CTL_MASK; - hw_state->pll8 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 8)); + hw_state->pll8 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 8)); hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; - hw_state->pll9 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 9)); + hw_state->pll9 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 9)); hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; - hw_state->pll10 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 10)); + hw_state->pll10 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10)); hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | PORT_PLL_DCO_AMP_MASK; @@ -2119,20 +2119,20 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, * can read only lane registers. We configure all lanes the same way, so * here just read out lanes 0/1 and output a note if lanes 2/3 differ. */ - hw_state->pcsdw12 = intel_de_read(dev_priv, + hw_state->pcsdw12 = intel_de_read(i915, BXT_PORT_PCS_DW12_LN01(phy, ch)); - if (intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) - drm_dbg(&dev_priv->drm, + if (intel_de_read(i915, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) + drm_dbg(&i915->drm, "lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", hw_state->pcsdw12, - intel_de_read(dev_priv, + intel_de_read(i915, BXT_PORT_PCS_DW12_LN23(phy, ch))); hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; ret = true; out: - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } @@ -2323,15 +2323,15 @@ static int bxt_get_dpll(struct intel_atomic_state *state, { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_shared_dpll *pll; enum intel_dpll_id id; /* 1:1 mapping between ports and PLLs */ id = (enum intel_dpll_id) encoder->port; - pll = intel_get_shared_dpll_by_id(dev_priv, id); + pll = intel_get_shared_dpll_by_id(i915, id); - drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] using pre-allocated %s\n", + drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] using pre-allocated %s\n", crtc->base.base.id, crtc->base.name, pll->info->name); intel_reference_shared_dpll(state, crtc, @@ -2349,10 +2349,10 @@ static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915) /* DSI non-SSC ref 19.2MHz */ } -static void bxt_dump_hw_state(struct drm_i915_private *dev_priv, +static void bxt_dump_hw_state(struct drm_i915_private *i915, const struct intel_dpll_hw_state *hw_state) { - drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," + drm_dbg_kms(&i915->drm, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", hw_state->ebb0, @@ -2580,9 +2580,9 @@ static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = { static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state, struct skl_wrpll_params *pll_params) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); const struct icl_combo_pll_params *params = - dev_priv->display.dpll.ref_clks.nssc == 24000 ? + i915->display.dpll.ref_clks.nssc == 24000 ? icl_dp_combo_pll_24MHz_values : icl_dp_combo_pll_19_2MHz_values; int clock = crtc_state->port_clock; @@ -2602,12 +2602,12 @@ static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state, static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, struct skl_wrpll_params *pll_params) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); - if (DISPLAY_VER(dev_priv) >= 12) { - switch (dev_priv->display.dpll.ref_clks.nssc) { + if (DISPLAY_VER(i915) >= 12) { + switch (i915->display.dpll.ref_clks.nssc) { default: - MISSING_CASE(dev_priv->display.dpll.ref_clks.nssc); + MISSING_CASE(i915->display.dpll.ref_clks.nssc); fallthrough; case 19200: case 38400: @@ -2618,9 +2618,9 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, break; } } else { - switch (dev_priv->display.dpll.ref_clks.nssc) { + switch (i915->display.dpll.ref_clks.nssc) { default: - MISSING_CASE(dev_priv->display.dpll.ref_clks.nssc); + MISSING_CASE(i915->display.dpll.ref_clks.nssc); fallthrough; case 19200: case 38400: @@ -2876,8 +2876,8 @@ static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc, static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, struct intel_dpll_hw_state *pll_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); - int refclk_khz = dev_priv->display.dpll.ref_clks.nssc; + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + int refclk_khz = i915->display.dpll.ref_clks.nssc; int clock = crtc_state->port_clock; u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac; u32 iref_ndiv, iref_trim, iref_pulse_w; @@ -2887,7 +2887,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, u64 tmp; bool use_ssc = false; bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); - bool is_dkl = DISPLAY_VER(dev_priv) >= 12; + bool is_dkl = DISPLAY_VER(i915) >= 12; int ret; ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz, @@ -2985,8 +2985,8 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, DKL_PLL_DIV0_PROP_COEFF(prop_coeff) | DKL_PLL_DIV0_FBPREDIV(m1div) | DKL_PLL_DIV0_FBDIV_INT(m2div_int); - if (dev_priv->display.vbt.override_afc_startup) { - u8 val = dev_priv->display.vbt.override_afc_startup_val; + if (i915->display.vbt.override_afc_startup) { + u8 val = i915->display.vbt.override_afc_startup_val; pll_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(val); } @@ -3076,16 +3076,16 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, return 0; } -static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv, +static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) { u32 m1, m2_int, m2_frac, div1, div2, ref_clock; u64 tmp; - ref_clock = dev_priv->display.dpll.ref_clks.nssc; + ref_clock = i915->display.dpll.ref_clks.nssc; - if (DISPLAY_VER(dev_priv) >= 12) { + if (DISPLAY_VER(i915) >= 12) { m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK; m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT; m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK; @@ -3190,7 +3190,7 @@ static void icl_update_active_dpll(struct intel_atomic_state *state, static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct icl_port_dpll *port_dpll = @@ -3207,12 +3207,12 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state, if (ret) return ret; - icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state); + icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state); /* this is mainly for the fastset check */ icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT); - crtc_state->port_clock = icl_ddi_combo_pll_get_freq(dev_priv, NULL, + crtc_state->port_clock = icl_ddi_combo_pll_get_freq(i915, NULL, &port_dpll->hw_state); return 0; @@ -3222,7 +3222,7 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct icl_port_dpll *port_dpll = @@ -3230,13 +3230,13 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state, enum port port = encoder->port; unsigned long dpll_mask; - if (IS_ALDERLAKE_S(dev_priv)) { + if (IS_ALDERLAKE_S(i915)) { dpll_mask = BIT(DPLL_ID_DG1_DPLL3) | BIT(DPLL_ID_DG1_DPLL2) | BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); - } else if (IS_DG1(dev_priv)) { + } else if (IS_DG1(i915)) { if (port == PORT_D || port == PORT_E) { dpll_mask = BIT(DPLL_ID_DG1_DPLL2) | @@ -3246,13 +3246,13 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state, BIT(DPLL_ID_DG1_DPLL0) | BIT(DPLL_ID_DG1_DPLL1); } - } else if (IS_ROCKETLAKE(dev_priv)) { + } else if (IS_ROCKETLAKE(i915)) { dpll_mask = BIT(DPLL_ID_EHL_DPLL4) | BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); - } else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && - port != PORT_A) { + } else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && + port != PORT_A) { dpll_mask = BIT(DPLL_ID_EHL_DPLL4) | BIT(DPLL_ID_ICL_DPLL1) | @@ -3262,7 +3262,7 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state, } /* Eliminate DPLLs from consideration if reserved by HTI */ - dpll_mask &= ~intel_hti_dpll_mask(dev_priv); + dpll_mask &= ~intel_hti_dpll_mask(i915); port_dpll->pll = intel_find_shared_dpll(state, crtc, &port_dpll->hw_state, @@ -3281,7 +3281,7 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state, static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct drm_i915_private *i915 = to_i915(state->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct icl_port_dpll *port_dpll = @@ -3294,7 +3294,7 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state, if (ret) return ret; - icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state); + icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state); port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state); @@ -3304,7 +3304,7 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state, /* this is mainly for the fastset check */ icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY); - crtc_state->port_clock = icl_ddi_mg_pll_get_freq(dev_priv, NULL, + crtc_state->port_clock = icl_ddi_mg_pll_get_freq(i915, NULL, &port_dpll->hw_state); return 0; @@ -3314,7 +3314,7 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct drm_i915_private *i915 = to_i915(state->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct icl_port_dpll *port_dpll = @@ -3333,7 +3333,7 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state, port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; - dpll_id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, + dpll_id = icl_tc_port_to_pll_id(intel_port_to_tc(i915, encoder->port)); port_dpll->pll = intel_find_shared_dpll(state, crtc, &port_dpll->hw_state, @@ -3360,12 +3360,12 @@ static int icl_compute_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + struct drm_i915_private *i915 = to_i915(state->base.dev); + enum phy phy = intel_port_to_phy(i915, encoder->port); - if (intel_phy_is_combo(dev_priv, phy)) + if (intel_phy_is_combo(i915, phy)) return icl_compute_combo_phy_dpll(state, crtc); - else if (intel_phy_is_tc(dev_priv, phy)) + else if (intel_phy_is_tc(i915, phy)) return icl_compute_tc_phy_dplls(state, crtc); MISSING_CASE(phy); @@ -3377,12 +3377,12 @@ static int icl_get_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + struct drm_i915_private *i915 = to_i915(state->base.dev); + enum phy phy = intel_port_to_phy(i915, encoder->port); - if (intel_phy_is_combo(dev_priv, phy)) + if (intel_phy_is_combo(i915, phy)) return icl_get_combo_phy_dpll(state, crtc, encoder); - else if (intel_phy_is_tc(dev_priv, phy)) + else if (intel_phy_is_tc(i915, phy)) return icl_get_tc_phy_dplls(state, crtc, encoder); MISSING_CASE(phy); @@ -3416,7 +3416,7 @@ static void icl_put_dplls(struct intel_atomic_state *state, } } -static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv, +static bool mg_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { @@ -3426,46 +3426,46 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv, bool ret = false; u32 val; - i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll); + i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; - val = intel_de_read(dev_priv, enable_reg); + val = intel_de_read(i915, enable_reg); if (!(val & PLL_ENABLE)) goto out; - hw_state->mg_refclkin_ctl = intel_de_read(dev_priv, + hw_state->mg_refclkin_ctl = intel_de_read(i915, MG_REFCLKIN_CTL(tc_port)); hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; hw_state->mg_clktop2_coreclkctl1 = - intel_de_read(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port)); + intel_de_read(i915, MG_CLKTOP2_CORECLKCTL1(tc_port)); hw_state->mg_clktop2_coreclkctl1 &= MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; hw_state->mg_clktop2_hsclkctl = - intel_de_read(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port)); + intel_de_read(i915, MG_CLKTOP2_HSCLKCTL(tc_port)); hw_state->mg_clktop2_hsclkctl &= MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK; - hw_state->mg_pll_div0 = intel_de_read(dev_priv, MG_PLL_DIV0(tc_port)); - hw_state->mg_pll_div1 = intel_de_read(dev_priv, MG_PLL_DIV1(tc_port)); - hw_state->mg_pll_lf = intel_de_read(dev_priv, MG_PLL_LF(tc_port)); - hw_state->mg_pll_frac_lock = intel_de_read(dev_priv, + hw_state->mg_pll_div0 = intel_de_read(i915, MG_PLL_DIV0(tc_port)); + hw_state->mg_pll_div1 = intel_de_read(i915, MG_PLL_DIV1(tc_port)); + hw_state->mg_pll_lf = intel_de_read(i915, MG_PLL_LF(tc_port)); + hw_state->mg_pll_frac_lock = intel_de_read(i915, MG_PLL_FRAC_LOCK(tc_port)); - hw_state->mg_pll_ssc = intel_de_read(dev_priv, MG_PLL_SSC(tc_port)); + hw_state->mg_pll_ssc = intel_de_read(i915, MG_PLL_SSC(tc_port)); - hw_state->mg_pll_bias = intel_de_read(dev_priv, MG_PLL_BIAS(tc_port)); + hw_state->mg_pll_bias = intel_de_read(i915, MG_PLL_BIAS(tc_port)); hw_state->mg_pll_tdc_coldst_bias = - intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port)); + intel_de_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port)); - if (dev_priv->display.dpll.ref_clks.nssc == 38400) { + if (i915->display.dpll.ref_clks.nssc == 38400) { hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART; hw_state->mg_pll_bias_mask = 0; } else { @@ -3478,11 +3478,11 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv, ret = true; out: - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } -static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, +static bool dkl_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { @@ -3492,12 +3492,12 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, bool ret = false; u32 val; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; - val = intel_de_read(dev_priv, intel_tc_pll_enable_reg(dev_priv, pll)); + val = intel_de_read(i915, intel_tc_pll_enable_reg(i915, pll)); if (!(val & PLL_ENABLE)) goto out; @@ -3505,12 +3505,12 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, * All registers read here have the same HIP_INDEX_REG even though * they are on different building blocks */ - hw_state->mg_refclkin_ctl = intel_dkl_phy_read(dev_priv, + hw_state->mg_refclkin_ctl = intel_dkl_phy_read(i915, DKL_REFCLKIN_CTL(tc_port)); hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; hw_state->mg_clktop2_hsclkctl = - intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port)); + intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port)); hw_state->mg_clktop2_hsclkctl &= MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | @@ -3518,42 +3518,42 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK; hw_state->mg_clktop2_coreclkctl1 = - intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port)); + intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port)); hw_state->mg_clktop2_coreclkctl1 &= MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; - hw_state->mg_pll_div0 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV0(tc_port)); + hw_state->mg_pll_div0 = intel_dkl_phy_read(i915, DKL_PLL_DIV0(tc_port)); val = DKL_PLL_DIV0_MASK; - if (dev_priv->display.vbt.override_afc_startup) + if (i915->display.vbt.override_afc_startup) val |= DKL_PLL_DIV0_AFC_STARTUP_MASK; hw_state->mg_pll_div0 &= val; - hw_state->mg_pll_div1 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port)); + hw_state->mg_pll_div1 = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port)); hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK | DKL_PLL_DIV1_TDC_TARGET_CNT_MASK); - hw_state->mg_pll_ssc = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port)); + hw_state->mg_pll_ssc = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port)); hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | DKL_PLL_SSC_STEP_LEN_MASK | DKL_PLL_SSC_STEP_NUM_MASK | DKL_PLL_SSC_EN); - hw_state->mg_pll_bias = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port)); + hw_state->mg_pll_bias = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port)); hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H | DKL_PLL_BIAS_FBDIV_FRAC_MASK); hw_state->mg_pll_tdc_coldst_bias = - intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); + intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port)); hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK | DKL_PLL_TDC_FEED_FWD_GAIN_MASK); ret = true; out: - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } -static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv, +static bool icl_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state, i915_reg_t enable_reg) @@ -3563,94 +3563,94 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv, bool ret = false; u32 val; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; - val = intel_de_read(dev_priv, enable_reg); + val = intel_de_read(i915, enable_reg); if (!(val & PLL_ENABLE)) goto out; - if (IS_ALDERLAKE_S(dev_priv)) { - hw_state->cfgcr0 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR0(id)); - hw_state->cfgcr1 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR1(id)); - } else if (IS_DG1(dev_priv)) { - hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id)); - hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id)); - } else if (IS_ROCKETLAKE(dev_priv)) { - hw_state->cfgcr0 = intel_de_read(dev_priv, + if (IS_ALDERLAKE_S(i915)) { + hw_state->cfgcr0 = intel_de_read(i915, ADLS_DPLL_CFGCR0(id)); + hw_state->cfgcr1 = intel_de_read(i915, ADLS_DPLL_CFGCR1(id)); + } else if (IS_DG1(i915)) { + hw_state->cfgcr0 = intel_de_read(i915, DG1_DPLL_CFGCR0(id)); + hw_state->cfgcr1 = intel_de_read(i915, DG1_DPLL_CFGCR1(id)); + } else if (IS_ROCKETLAKE(i915)) { + hw_state->cfgcr0 = intel_de_read(i915, RKL_DPLL_CFGCR0(id)); - hw_state->cfgcr1 = intel_de_read(dev_priv, + hw_state->cfgcr1 = intel_de_read(i915, RKL_DPLL_CFGCR1(id)); - } else if (DISPLAY_VER(dev_priv) >= 12) { - hw_state->cfgcr0 = intel_de_read(dev_priv, + } else if (DISPLAY_VER(i915) >= 12) { + hw_state->cfgcr0 = intel_de_read(i915, TGL_DPLL_CFGCR0(id)); - hw_state->cfgcr1 = intel_de_read(dev_priv, + hw_state->cfgcr1 = intel_de_read(i915, TGL_DPLL_CFGCR1(id)); - if (dev_priv->display.vbt.override_afc_startup) { - hw_state->div0 = intel_de_read(dev_priv, TGL_DPLL0_DIV0(id)); + if (i915->display.vbt.override_afc_startup) { + hw_state->div0 = intel_de_read(i915, TGL_DPLL0_DIV0(id)); hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK; } } else { - if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && + if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && id == DPLL_ID_EHL_DPLL4) { - hw_state->cfgcr0 = intel_de_read(dev_priv, + hw_state->cfgcr0 = intel_de_read(i915, ICL_DPLL_CFGCR0(4)); - hw_state->cfgcr1 = intel_de_read(dev_priv, + hw_state->cfgcr1 = intel_de_read(i915, ICL_DPLL_CFGCR1(4)); } else { - hw_state->cfgcr0 = intel_de_read(dev_priv, + hw_state->cfgcr0 = intel_de_read(i915, ICL_DPLL_CFGCR0(id)); - hw_state->cfgcr1 = intel_de_read(dev_priv, + hw_state->cfgcr1 = intel_de_read(i915, ICL_DPLL_CFGCR1(id)); } } ret = true; out: - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } -static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv, +static bool combo_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { - i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll); + i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); - return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg); + return icl_pll_get_hw_state(i915, pll, hw_state, enable_reg); } -static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv, +static bool tbt_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { - return icl_pll_get_hw_state(dev_priv, pll, hw_state, TBT_PLL_ENABLE); + return icl_pll_get_hw_state(i915, pll, hw_state, TBT_PLL_ENABLE); } -static void icl_dpll_write(struct drm_i915_private *dev_priv, +static void icl_dpll_write(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { struct intel_dpll_hw_state *hw_state = &pll->state.hw_state; const enum intel_dpll_id id = pll->info->id; i915_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG; - if (IS_ALDERLAKE_S(dev_priv)) { + if (IS_ALDERLAKE_S(i915)) { cfgcr0_reg = ADLS_DPLL_CFGCR0(id); cfgcr1_reg = ADLS_DPLL_CFGCR1(id); - } else if (IS_DG1(dev_priv)) { + } else if (IS_DG1(i915)) { cfgcr0_reg = DG1_DPLL_CFGCR0(id); cfgcr1_reg = DG1_DPLL_CFGCR1(id); - } else if (IS_ROCKETLAKE(dev_priv)) { + } else if (IS_ROCKETLAKE(i915)) { cfgcr0_reg = RKL_DPLL_CFGCR0(id); cfgcr1_reg = RKL_DPLL_CFGCR1(id); - } else if (DISPLAY_VER(dev_priv) >= 12) { + } else if (DISPLAY_VER(i915) >= 12) { cfgcr0_reg = TGL_DPLL_CFGCR0(id); cfgcr1_reg = TGL_DPLL_CFGCR1(id); div0_reg = TGL_DPLL0_DIV0(id); } else { - if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && + if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && id == DPLL_ID_EHL_DPLL4) { cfgcr0_reg = ICL_DPLL_CFGCR0(4); cfgcr1_reg = ICL_DPLL_CFGCR1(4); @@ -3660,18 +3660,18 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv, } } - intel_de_write(dev_priv, cfgcr0_reg, hw_state->cfgcr0); - intel_de_write(dev_priv, cfgcr1_reg, hw_state->cfgcr1); - drm_WARN_ON_ONCE(&dev_priv->drm, dev_priv->display.vbt.override_afc_startup && + intel_de_write(i915, cfgcr0_reg, hw_state->cfgcr0); + intel_de_write(i915, cfgcr1_reg, hw_state->cfgcr1); + drm_WARN_ON_ONCE(&i915->drm, i915->display.vbt.override_afc_startup && !i915_mmio_reg_valid(div0_reg)); - if (dev_priv->display.vbt.override_afc_startup && + if (i915->display.vbt.override_afc_startup && i915_mmio_reg_valid(div0_reg)) - intel_de_rmw(dev_priv, div0_reg, + intel_de_rmw(i915, div0_reg, TGL_DPLL0_DIV0_AFC_STARTUP_MASK, hw_state->div0); - intel_de_posting_read(dev_priv, cfgcr1_reg); + intel_de_posting_read(i915, cfgcr1_reg); } -static void icl_mg_pll_write(struct drm_i915_private *dev_priv, +static void icl_mg_pll_write(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { struct intel_dpll_hw_state *hw_state = &pll->state.hw_state; @@ -3683,38 +3683,38 @@ static void icl_mg_pll_write(struct drm_i915_private *dev_priv, * during the calc/readout phase if the mask depends on some other HW * state like refclk, see icl_calc_mg_pll_state(). */ - intel_de_rmw(dev_priv, MG_REFCLKIN_CTL(tc_port), + intel_de_rmw(i915, MG_REFCLKIN_CTL(tc_port), MG_REFCLKIN_CTL_OD_2_MUX_MASK, hw_state->mg_refclkin_ctl); - intel_de_rmw(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port), + intel_de_rmw(i915, MG_CLKTOP2_CORECLKCTL1(tc_port), MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK, hw_state->mg_clktop2_coreclkctl1); - intel_de_rmw(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port), + intel_de_rmw(i915, MG_CLKTOP2_HSCLKCTL(tc_port), MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK, hw_state->mg_clktop2_hsclkctl); - intel_de_write(dev_priv, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); - intel_de_write(dev_priv, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); - intel_de_write(dev_priv, MG_PLL_LF(tc_port), hw_state->mg_pll_lf); - intel_de_write(dev_priv, MG_PLL_FRAC_LOCK(tc_port), + intel_de_write(i915, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); + intel_de_write(i915, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); + intel_de_write(i915, MG_PLL_LF(tc_port), hw_state->mg_pll_lf); + intel_de_write(i915, MG_PLL_FRAC_LOCK(tc_port), hw_state->mg_pll_frac_lock); - intel_de_write(dev_priv, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc); + intel_de_write(i915, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc); - intel_de_rmw(dev_priv, MG_PLL_BIAS(tc_port), + intel_de_rmw(i915, MG_PLL_BIAS(tc_port), hw_state->mg_pll_bias_mask, hw_state->mg_pll_bias); - intel_de_rmw(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port), + intel_de_rmw(i915, MG_PLL_TDC_COLDST_BIAS(tc_port), hw_state->mg_pll_tdc_coldst_bias_mask, hw_state->mg_pll_tdc_coldst_bias); - intel_de_posting_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port)); + intel_de_posting_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port)); } -static void dkl_pll_write(struct drm_i915_private *dev_priv, +static void dkl_pll_write(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { struct intel_dpll_hw_state *hw_state = &pll->state.hw_state; @@ -3726,83 +3726,83 @@ static void dkl_pll_write(struct drm_i915_private *dev_priv, * though on different building block */ /* All the registers are RMW */ - val = intel_dkl_phy_read(dev_priv, DKL_REFCLKIN_CTL(tc_port)); + val = intel_dkl_phy_read(i915, DKL_REFCLKIN_CTL(tc_port)); val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK; val |= hw_state->mg_refclkin_ctl; - intel_dkl_phy_write(dev_priv, DKL_REFCLKIN_CTL(tc_port), val); + intel_dkl_phy_write(i915, DKL_REFCLKIN_CTL(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port)); + val = intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port)); val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; val |= hw_state->mg_clktop2_coreclkctl1; - intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), val); + intel_dkl_phy_write(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port)); + val = intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port)); val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK); val |= hw_state->mg_clktop2_hsclkctl; - intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), val); + intel_dkl_phy_write(i915, DKL_CLKTOP2_HSCLKCTL(tc_port), val); val = DKL_PLL_DIV0_MASK; - if (dev_priv->display.vbt.override_afc_startup) + if (i915->display.vbt.override_afc_startup) val |= DKL_PLL_DIV0_AFC_STARTUP_MASK; - intel_dkl_phy_rmw(dev_priv, DKL_PLL_DIV0(tc_port), val, + intel_dkl_phy_rmw(i915, DKL_PLL_DIV0(tc_port), val, hw_state->mg_pll_div0); - val = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port)); + val = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port)); val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK | DKL_PLL_DIV1_TDC_TARGET_CNT_MASK); val |= hw_state->mg_pll_div1; - intel_dkl_phy_write(dev_priv, DKL_PLL_DIV1(tc_port), val); + intel_dkl_phy_write(i915, DKL_PLL_DIV1(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port)); + val = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port)); val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | DKL_PLL_SSC_STEP_LEN_MASK | DKL_PLL_SSC_STEP_NUM_MASK | DKL_PLL_SSC_EN); val |= hw_state->mg_pll_ssc; - intel_dkl_phy_write(dev_priv, DKL_PLL_SSC(tc_port), val); + intel_dkl_phy_write(i915, DKL_PLL_SSC(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port)); + val = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port)); val &= ~(DKL_PLL_BIAS_FRAC_EN_H | DKL_PLL_BIAS_FBDIV_FRAC_MASK); val |= hw_state->mg_pll_bias; - intel_dkl_phy_write(dev_priv, DKL_PLL_BIAS(tc_port), val); + intel_dkl_phy_write(i915, DKL_PLL_BIAS(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); + val = intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port)); val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK | DKL_PLL_TDC_FEED_FWD_GAIN_MASK); val |= hw_state->mg_pll_tdc_coldst_bias; - intel_dkl_phy_write(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), val); + intel_dkl_phy_write(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port), val); - intel_dkl_phy_posting_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); + intel_dkl_phy_posting_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port)); } -static void icl_pll_power_enable(struct drm_i915_private *dev_priv, +static void icl_pll_power_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, i915_reg_t enable_reg) { - intel_de_rmw(dev_priv, enable_reg, 0, PLL_POWER_ENABLE); + intel_de_rmw(i915, enable_reg, 0, PLL_POWER_ENABLE); /* * The spec says we need to "wait" but it also says it should be * immediate. */ - if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_POWER_STATE, 1)) - drm_err(&dev_priv->drm, "PLL %d Power not enabled\n", + if (intel_de_wait_for_set(i915, enable_reg, PLL_POWER_STATE, 1)) + drm_err(&i915->drm, "PLL %d Power not enabled\n", pll->info->id); } -static void icl_pll_enable(struct drm_i915_private *dev_priv, +static void icl_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, i915_reg_t enable_reg) { - intel_de_rmw(dev_priv, enable_reg, 0, PLL_ENABLE); + intel_de_rmw(i915, enable_reg, 0, PLL_ENABLE); /* Timeout is actually 600us. */ - if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 1)) - drm_err(&dev_priv->drm, "PLL %d not locked\n", pll->info->id); + if (intel_de_wait_for_set(i915, enable_reg, PLL_LOCK, 1)) + drm_err(&i915->drm, "PLL %d not locked\n", pll->info->id); } static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct intel_shared_dpll *pll) @@ -3829,12 +3829,12 @@ static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct inte drm_dbg_kms(&i915->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val); } -static void combo_pll_enable(struct drm_i915_private *dev_priv, +static void combo_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { - i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll); + i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); - if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && + if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && pll->info->id == DPLL_ID_EHL_DPLL4) { /* @@ -3842,13 +3842,13 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv, * This can be done by taking a reference on DPLL4 power * domain. */ - pll->wakeref = intel_display_power_get(dev_priv, + pll->wakeref = intel_display_power_get(i915, POWER_DOMAIN_DC_OFF); } - icl_pll_power_enable(dev_priv, pll, enable_reg); + icl_pll_power_enable(i915, pll, enable_reg); - icl_dpll_write(dev_priv, pll); + icl_dpll_write(i915, pll); /* * DVFS pre sequence would be here, but in our driver the cdclk code @@ -3856,19 +3856,19 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv, * nothing here. */ - icl_pll_enable(dev_priv, pll, enable_reg); + icl_pll_enable(i915, pll, enable_reg); - adlp_cmtg_clock_gating_wa(dev_priv, pll); + adlp_cmtg_clock_gating_wa(i915, pll); /* DVFS post sequence would be here. See the comment above. */ } -static void tbt_pll_enable(struct drm_i915_private *dev_priv, +static void tbt_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { - icl_pll_power_enable(dev_priv, pll, TBT_PLL_ENABLE); + icl_pll_power_enable(i915, pll, TBT_PLL_ENABLE); - icl_dpll_write(dev_priv, pll); + icl_dpll_write(i915, pll); /* * DVFS pre sequence would be here, but in our driver the cdclk code @@ -3876,22 +3876,22 @@ static void tbt_pll_enable(struct drm_i915_private *dev_priv, * nothing here. */ - icl_pll_enable(dev_priv, pll, TBT_PLL_ENABLE); + icl_pll_enable(i915, pll, TBT_PLL_ENABLE); /* DVFS post sequence would be here. See the comment above. */ } -static void mg_pll_enable(struct drm_i915_private *dev_priv, +static void mg_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { - i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll); + i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); - icl_pll_power_enable(dev_priv, pll, enable_reg); + icl_pll_power_enable(i915, pll, enable_reg); - if (DISPLAY_VER(dev_priv) >= 12) - dkl_pll_write(dev_priv, pll); + if (DISPLAY_VER(i915) >= 12) + dkl_pll_write(i915, pll); else - icl_mg_pll_write(dev_priv, pll); + icl_mg_pll_write(i915, pll); /* * DVFS pre sequence would be here, but in our driver the cdclk code @@ -3899,12 +3899,12 @@ static void mg_pll_enable(struct drm_i915_private *dev_priv, * nothing here. */ - icl_pll_enable(dev_priv, pll, enable_reg); + icl_pll_enable(i915, pll, enable_reg); /* DVFS post sequence would be here. See the comment above. */ } -static void icl_pll_disable(struct drm_i915_private *dev_priv, +static void icl_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, i915_reg_t enable_reg) { @@ -3916,50 +3916,50 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv, * nothing here. */ - intel_de_rmw(dev_priv, enable_reg, PLL_ENABLE, 0); + intel_de_rmw(i915, enable_reg, PLL_ENABLE, 0); /* Timeout is actually 1us. */ - if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK, 1)) - drm_err(&dev_priv->drm, "PLL %d locked\n", pll->info->id); + if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 1)) + drm_err(&i915->drm, "PLL %d locked\n", pll->info->id); /* DVFS post sequence would be here. See the comment above. */ - intel_de_rmw(dev_priv, enable_reg, PLL_POWER_ENABLE, 0); + intel_de_rmw(i915, enable_reg, PLL_POWER_ENABLE, 0); /* * The spec says we need to "wait" but it also says it should be * immediate. */ - if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_POWER_STATE, 1)) - drm_err(&dev_priv->drm, "PLL %d Power not disabled\n", + if (intel_de_wait_for_clear(i915, enable_reg, PLL_POWER_STATE, 1)) + drm_err(&i915->drm, "PLL %d Power not disabled\n", pll->info->id); } -static void combo_pll_disable(struct drm_i915_private *dev_priv, +static void combo_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { - i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll); + i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); - icl_pll_disable(dev_priv, pll, enable_reg); + icl_pll_disable(i915, pll, enable_reg); - if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && + if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && pll->info->id == DPLL_ID_EHL_DPLL4) - intel_display_power_put(dev_priv, POWER_DOMAIN_DC_OFF, + intel_display_power_put(i915, POWER_DOMAIN_DC_OFF, pll->wakeref); } -static void tbt_pll_disable(struct drm_i915_private *dev_priv, +static void tbt_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { - icl_pll_disable(dev_priv, pll, TBT_PLL_ENABLE); + icl_pll_disable(i915, pll, TBT_PLL_ENABLE); } -static void mg_pll_disable(struct drm_i915_private *dev_priv, +static void mg_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { - i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll); + i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); - icl_pll_disable(dev_priv, pll, enable_reg); + icl_pll_disable(i915, pll, enable_reg); } static void icl_update_dpll_ref_clks(struct drm_i915_private *i915) @@ -3968,10 +3968,10 @@ static void icl_update_dpll_ref_clks(struct drm_i915_private *i915) i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; } -static void icl_dump_hw_state(struct drm_i915_private *dev_priv, +static void icl_dump_hw_state(struct drm_i915_private *i915, const struct intel_dpll_hw_state *hw_state) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(&i915->drm, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, div0: 0x%x, " "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, " @@ -4153,42 +4153,42 @@ static const struct intel_dpll_mgr adlp_pll_mgr = { /** * intel_shared_dpll_init - Initialize shared DPLLs - * @dev_priv: i915 device + * @i915: i915 device * - * Initialize shared DPLLs for @dev_priv. + * Initialize shared DPLLs for @i915. */ -void intel_shared_dpll_init(struct drm_i915_private *dev_priv) +void intel_shared_dpll_init(struct drm_i915_private *i915) { const struct intel_dpll_mgr *dpll_mgr = NULL; const struct dpll_info *dpll_info; int i; - mutex_init(&dev_priv->display.dpll.lock); + mutex_init(&i915->display.dpll.lock); - if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv)) + if (DISPLAY_VER(i915) >= 14 || IS_DG2(i915)) /* No shared DPLLs on DG2; port PLLs are part of the PHY */ dpll_mgr = NULL; - else if (IS_ALDERLAKE_P(dev_priv)) + else if (IS_ALDERLAKE_P(i915)) dpll_mgr = &adlp_pll_mgr; - else if (IS_ALDERLAKE_S(dev_priv)) + else if (IS_ALDERLAKE_S(i915)) dpll_mgr = &adls_pll_mgr; - else if (IS_DG1(dev_priv)) + else if (IS_DG1(i915)) dpll_mgr = &dg1_pll_mgr; - else if (IS_ROCKETLAKE(dev_priv)) + else if (IS_ROCKETLAKE(i915)) dpll_mgr = &rkl_pll_mgr; - else if (DISPLAY_VER(dev_priv) >= 12) + else if (DISPLAY_VER(i915) >= 12) dpll_mgr = &tgl_pll_mgr; - else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) + else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) dpll_mgr = &ehl_pll_mgr; - else if (DISPLAY_VER(dev_priv) >= 11) + else if (DISPLAY_VER(i915) >= 11) dpll_mgr = &icl_pll_mgr; - else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) + else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) dpll_mgr = &bxt_pll_mgr; - else if (DISPLAY_VER(dev_priv) == 9) + else if (DISPLAY_VER(i915) == 9) dpll_mgr = &skl_pll_mgr; - else if (HAS_DDI(dev_priv)) + else if (HAS_DDI(i915)) dpll_mgr = &hsw_pll_mgr; - else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) + else if (HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915)) dpll_mgr = &pch_pll_mgr; if (!dpll_mgr) @@ -4197,20 +4197,20 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv) dpll_info = dpll_mgr->dpll_info; for (i = 0; dpll_info[i].name; i++) { - if (drm_WARN_ON(&dev_priv->drm, - i >= ARRAY_SIZE(dev_priv->display.dpll.shared_dplls))) + if (drm_WARN_ON(&i915->drm, + i >= ARRAY_SIZE(i915->display.dpll.shared_dplls))) break; /* must fit into unsigned long bitmask on 32bit */ - if (drm_WARN_ON(&dev_priv->drm, dpll_info[i].id >= 32)) + if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32)) break; - dev_priv->display.dpll.shared_dplls[i].info = &dpll_info[i]; - dev_priv->display.dpll.shared_dplls[i].index = i; + i915->display.dpll.shared_dplls[i].info = &dpll_info[i]; + i915->display.dpll.shared_dplls[i].index = i; } - dev_priv->display.dpll.mgr = dpll_mgr; - dev_priv->display.dpll.num_shared_dpll = i; + i915->display.dpll.mgr = dpll_mgr; + i915->display.dpll.num_shared_dpll = i; } /** @@ -4231,10 +4231,10 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; + struct drm_i915_private *i915 = to_i915(state->base.dev); + const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; - if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr)) + if (drm_WARN_ON(&i915->drm, !dpll_mgr)) return -EINVAL; return dpll_mgr->compute_dplls(state, crtc, encoder); @@ -4264,10 +4264,10 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; + struct drm_i915_private *i915 = to_i915(state->base.dev); + const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; - if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr)) + if (drm_WARN_ON(&i915->drm, !dpll_mgr)) return -EINVAL; return dpll_mgr->get_dplls(state, crtc, encoder); @@ -4287,8 +4287,8 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state, void intel_release_shared_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; + struct drm_i915_private *i915 = to_i915(state->base.dev); + const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; /* * FIXME: this function is called for every platform having a @@ -4316,10 +4316,10 @@ void intel_update_active_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; - if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr)) + if (drm_WARN_ON(&i915->drm, !dpll_mgr)) return; dpll_mgr->update_active_dpll(state, crtc, encoder); @@ -4432,21 +4432,21 @@ void intel_dpll_sanitize_state(struct drm_i915_private *i915) /** * intel_dpll_dump_hw_state - write hw_state to dmesg - * @dev_priv: i915 drm device + * @i915: i915 drm device * @hw_state: hw state to be written to the log * * Write the relevant values in @hw_state to dmesg using drm_dbg_kms. */ -void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, +void intel_dpll_dump_hw_state(struct drm_i915_private *i915, const struct intel_dpll_hw_state *hw_state) { - if (dev_priv->display.dpll.mgr) { - dev_priv->display.dpll.mgr->dump_hw_state(dev_priv, hw_state); + if (i915->display.dpll.mgr) { + i915->display.dpll.mgr->dump_hw_state(i915, hw_state); } else { /* fallback for platforms that don't use the shared dpll * infrastructure */ - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(&i915->drm, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " "fp0: 0x%x, fp1: 0x%x\n", hw_state->dpll, @@ -4457,7 +4457,7 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, } static void -verify_single_dpll_state(struct drm_i915_private *dev_priv, +verify_single_dpll_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_crtc *crtc, struct intel_crtc_state *new_crtc_state) @@ -4468,22 +4468,22 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv, memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); - drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name); + drm_dbg_kms(&i915->drm, "%s\n", pll->info->name); - active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state); + active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state); if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) { - I915_STATE_WARN(dev_priv, !pll->on && pll->active_mask, + I915_STATE_WARN(i915, !pll->on && pll->active_mask, "pll in active use but not on in sw tracking\n"); - I915_STATE_WARN(dev_priv, pll->on && !pll->active_mask, + I915_STATE_WARN(i915, pll->on && !pll->active_mask, "pll is on but not used by any active pipe\n"); - I915_STATE_WARN(dev_priv, pll->on != active, + I915_STATE_WARN(i915, pll->on != active, "pll on state mismatch (expected %i, found %i)\n", pll->on, active); } if (!crtc) { - I915_STATE_WARN(dev_priv, + I915_STATE_WARN(i915, pll->active_mask & ~pll->state.pipe_mask, "more active pll users than references: 0x%x vs 0x%x\n", pll->active_mask, pll->state.pipe_mask); @@ -4494,19 +4494,19 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv, pipe_mask = BIT(crtc->pipe); if (new_crtc_state->hw.active) - I915_STATE_WARN(dev_priv, !(pll->active_mask & pipe_mask), + I915_STATE_WARN(i915, !(pll->active_mask & pipe_mask), "pll active mismatch (expected pipe %c in active mask 0x%x)\n", pipe_name(crtc->pipe), pll->active_mask); else - I915_STATE_WARN(dev_priv, pll->active_mask & pipe_mask, + I915_STATE_WARN(i915, pll->active_mask & pipe_mask, "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n", pipe_name(crtc->pipe), pll->active_mask); - I915_STATE_WARN(dev_priv, !(pll->state.pipe_mask & pipe_mask), + I915_STATE_WARN(i915, !(pll->state.pipe_mask & pipe_mask), "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n", pipe_mask, pll->state.pipe_mask); - I915_STATE_WARN(dev_priv, + I915_STATE_WARN(i915, pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state, sizeof(dpll_hw_state)), "pll hw state mismatch\n"); @@ -4516,10 +4516,10 @@ void intel_shared_dpll_state_verify(struct intel_crtc *crtc, struct intel_crtc_state *old_crtc_state, struct intel_crtc_state *new_crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); if (new_crtc_state->shared_dpll) - verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, + verify_single_dpll_state(i915, new_crtc_state->shared_dpll, crtc, new_crtc_state); if (old_crtc_state->shared_dpll && @@ -4527,10 +4527,10 @@ void intel_shared_dpll_state_verify(struct intel_crtc *crtc, u8 pipe_mask = BIT(crtc->pipe); struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; - I915_STATE_WARN(dev_priv, pll->active_mask & pipe_mask, + I915_STATE_WARN(i915, pll->active_mask & pipe_mask, "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", pipe_name(crtc->pipe), pll->active_mask); - I915_STATE_WARN(dev_priv, pll->state.pipe_mask & pipe_mask, + I915_STATE_WARN(i915, pll->state.pipe_mask & pipe_mask, "pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n", pipe_name(crtc->pipe), pll->state.pipe_mask); } diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index a18ab2680a8f..75d2ff977b4e 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -327,9 +327,9 @@ struct intel_shared_dpll { /* shared dpll functions */ struct intel_shared_dpll * -intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, +intel_get_shared_dpll_by_id(struct drm_i915_private *i915, enum intel_dpll_id id); -void assert_shared_dpll(struct drm_i915_private *dev_priv, +void assert_shared_dpll(struct drm_i915_private *i915, struct intel_shared_dpll *pll, bool state); #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) @@ -359,12 +359,12 @@ bool intel_dpll_get_hw_state(struct drm_i915_private *i915, void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state); void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state); void intel_shared_dpll_swap_state(struct intel_atomic_state *state); -void intel_shared_dpll_init(struct drm_i915_private *dev_priv); -void intel_dpll_update_ref_clks(struct drm_i915_private *dev_priv); -void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv); -void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv); +void intel_shared_dpll_init(struct drm_i915_private *i915); +void intel_dpll_update_ref_clks(struct drm_i915_private *i915); +void intel_dpll_readout_hw_state(struct drm_i915_private *i915); +void intel_dpll_sanitize_state(struct drm_i915_private *i915); -void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, +void intel_dpll_dump_hw_state(struct drm_i915_private *i915, const struct intel_dpll_hw_state *hw_state); enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port); bool intel_dpll_is_combophy(enum intel_dpll_id id); From 5ed8c7bcf9a58372d3be3d9cd167e45497efaae2 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 2 Oct 2023 11:47:02 +0300 Subject: [PATCH 34/82] drm/i915/mocs: use to_gt() instead of direct &i915->gt MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Have to give up the const on i915 pointer, but it's not big of a deal considering non-const i915 gets passed all over the place. Signed-off-by: Jani Nikula Reviewed-by: Gustavo Sousa Reviewed-by: Andi Shyti Acked-by: Michał Winiarski Link: https://patchwork.freedesktop.org/patch/msgid/63e644f056c7745eb0e8e165c990c392a38ec85c.1696236329.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/gt/intel_mocs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 07269ff3be13..353f93baaca0 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -487,7 +487,7 @@ static bool has_mocs(const struct drm_i915_private *i915) return !IS_DGFX(i915); } -static unsigned int get_mocs_settings(const struct drm_i915_private *i915, +static unsigned int get_mocs_settings(struct drm_i915_private *i915, struct drm_i915_mocs_table *table) { unsigned int flags; @@ -495,7 +495,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, memset(table, 0, sizeof(struct drm_i915_mocs_table)); table->unused_entries_index = I915_MOCS_PTE; - if (IS_GFX_GT_IP_RANGE(&i915->gt0, IP_VER(12, 70), IP_VER(12, 71))) { + if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) { table->size = ARRAY_SIZE(mtl_mocs_table); table->table = mtl_mocs_table; table->n_entries = MTL_NUM_MOCS_ENTRIES; From 39fa9a7d5fb7d8316b9c7c56a1f8e473008244e8 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 2 Oct 2023 11:47:03 +0300 Subject: [PATCH 35/82] drm/i915: allocate i915->gt0 dynamically MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Convert i915->gt0 to a pointer, and allocate it dynamically. Signed-off-by: Jani Nikula Reviewed-by: Gustavo Sousa Reviewed-by: Andi Shyti Acked-by: Michał Winiarski Link: https://patchwork.freedesktop.org/patch/msgid/01bf968aa431b77d491790178cbeece18b5fc4c0.1696236329.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/gt/intel_gt.c | 8 +++++++- drivers/gpu/drm/i915/i915_drv.h | 8 ++++---- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 93062c35e072..a3d68ff4b191 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -62,7 +62,13 @@ void intel_gt_common_init_early(struct intel_gt *gt) /* Preliminary initialization of Tile 0 */ int intel_root_gt_init_early(struct drm_i915_private *i915) { - struct intel_gt *gt = to_gt(i915); + struct intel_gt *gt; + + gt = drmm_kzalloc(&i915->drm, sizeof(*gt), GFP_KERNEL); + if (!gt) + return -ENOMEM; + + i915->gt0 = gt; gt->i915 = i915; gt->uncore = &i915->uncore; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index da2217c16153..70240f71d886 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -318,10 +318,10 @@ struct drm_i915_private { struct i915_hwmon *hwmon; /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ - struct intel_gt gt0; + struct intel_gt *gt0; /* - * i915->gt[0] == &i915->gt0 + * i915->gt[0] == i915->gt0 */ struct intel_gt *gt[I915_MAX_GT]; @@ -382,9 +382,9 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) return pci_get_drvdata(pdev); } -static inline struct intel_gt *to_gt(struct drm_i915_private *i915) +static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) { - return &i915->gt0; + return i915->gt0; } /* Simple iterator over all initialised engines */ From 14aebb78b994fd307ec26f82f9f8ccea2a12c6a1 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 2 Oct 2023 11:47:04 +0300 Subject: [PATCH 36/82] drm/i915/gt: remove i915->gt0 in favour of i915->gt[0] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since gt0 == i915->gt[0], just drop the former. Signed-off-by: Jani Nikula Reviewed-by: Gustavo Sousa Reviewed-by: Andi Shyti Acked-by: Michał Winiarski Link: https://patchwork.freedesktop.org/patch/msgid/5319364f4c9416fed218382d020a57c5b0a17bee.1696236329.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/gt/intel_gt.c | 4 +--- drivers/gpu/drm/i915/i915_drv.h | 8 +------- drivers/gpu/drm/i915/selftests/mock_gem_device.c | 1 - 3 files changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index a3d68ff4b191..bb6c3f68f7d2 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -68,7 +68,7 @@ int intel_root_gt_init_early(struct drm_i915_private *i915) if (!gt) return -ENOMEM; - i915->gt0 = gt; + i915->gt[0] = gt; gt->i915 = i915; gt->uncore = &i915->uncore; @@ -917,8 +917,6 @@ int intel_gt_probe_all(struct drm_i915_private *i915) if (ret) return ret; - i915->gt[0] = gt; - if (!HAS_EXTRA_GT_LIST(i915)) return 0; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 70240f71d886..20bbad165d76 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -317,12 +317,6 @@ struct drm_i915_private { struct i915_hwmon *hwmon; - /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ - struct intel_gt *gt0; - - /* - * i915->gt[0] == i915->gt0 - */ struct intel_gt *gt[I915_MAX_GT]; struct kobject *sysfs_gt; @@ -384,7 +378,7 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) { - return i915->gt0; + return i915->gt[0]; } /* Simple iterator over all initialised engines */ diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c index 7de6477803f8..af349fd9abc2 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c @@ -114,7 +114,6 @@ static struct dev_pm_domain pm_domain = { static void mock_gt_probe(struct drm_i915_private *i915) { - i915->gt[0] = to_gt(i915); i915->gt[0]->name = "Mock GT"; } From cf37c0979e558213e2a2f87c2c3dfe644a66b210 Mon Sep 17 00:00:00 2001 From: Niko Tsirakis Date: Mon, 2 Oct 2023 20:47:09 +0000 Subject: [PATCH 37/82] drm/i915/display/lspcon: Increase LSPCON mode settle timeout This is to eliminate all cases of "*ERROR* LSPCON mode hasn't settled", followed by link training errors. Intel engineers recommended increasing this timeout and that does resolve the issue. On some CometLake-based device designs the Parade PS175 takes more than 400ms to settle in PCON mode. 100 reboot trials on one device resulted in a median settle time of 440ms and a maximum of 444ms. Even after increasing the timeout to 500ms, 2% of devices still had this error. So this increases the timeout to 800ms. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9443 Signed-off-by: Pablo Ceballos Signed-off-by: Niko Tsirakis Reviewed-by: Jani Nikula Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20231002204709.761089-1-ntsirakis@google.com --- drivers/gpu/drm/i915/display/intel_lspcon.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 152a22a8ffd2..1d048fa98561 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -153,6 +153,18 @@ static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon) return current_mode; } +static int lspcon_get_mode_settle_timeout(struct intel_lspcon *lspcon) +{ + /* + * On some CometLake-based device designs the Parade PS175 takes more + * than 400ms to settle in PCON mode. 100 reboot trials on one device + * resulted in a median settle time of 440ms and a maximum of 444ms. + * Even after increasing the timeout to 500ms, 2% of devices still had + * this error. So this sets the timeout to 800ms. + */ + return lspcon->vendor == LSPCON_VENDOR_PARADE ? 800 : 400; +} + static enum drm_lspcon_mode lspcon_wait_mode(struct intel_lspcon *lspcon, enum drm_lspcon_mode mode) { @@ -167,7 +179,8 @@ static enum drm_lspcon_mode lspcon_wait_mode(struct intel_lspcon *lspcon, drm_dbg_kms(&i915->drm, "Waiting for LSPCON mode %s to settle\n", lspcon_mode_name(mode)); - wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, 400); + wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, + lspcon_get_mode_settle_timeout(lspcon)); if (current_mode != mode) drm_err(&i915->drm, "LSPCON mode hasn't settled\n"); From 07f9cfe2ef6c086a3760430d7c0a224584d495a4 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 29 Sep 2023 18:49:29 +0300 Subject: [PATCH 38/82] drm/i915/dp_mst: Make sure pbn_div is up-to-date after sink reconnect Atm the MST encoder config computation may use an out-of-date pbn_div value, if the sink is unplugged and a sink is replugged with different link rate/lane count capabilities. The current way of reinitializing pbn_div depends on pbn_div getting cleared via intel_atomic_check() -> drm_dp_mst_atomic_check() -> drm_dp_mst_atomic_check_payload_alloc_limits(), however the clearing won't happen if the sink got unplugged (and hence drm_dp_mst_topology_mgr::mst_state being false). To fix the above, simply update pbn_div unconditionally during config computation, making pbn_div always match the link rate and lane count. Cc: Lyude Paul Reviewed-by: Lyude Paul Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20230929154929.343947-1-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index a21cc9d0689e..73e397736463 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -94,12 +94,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, crtc_state->lane_count = limits->max_lane_count; crtc_state->port_clock = limits->max_rate; - // TODO: Handle pbn_div changes by adding a new MST helper - if (!mst_state->pbn_div) { - mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr, - crtc_state->port_clock, - crtc_state->lane_count); - } + mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr, + crtc_state->port_clock, + crtc_state->lane_count); for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) { drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); From 5846cdfd3d58852cdc991e589de7535151a47a4e Mon Sep 17 00:00:00 2001 From: Uma Shankar Date: Fri, 29 Sep 2023 13:13:06 +0530 Subject: [PATCH 39/82] drm/i915/display: Created exclusive version of vga decode setup Current vga arbiter implementation in i915 needs a re-design. The current approach would cause real problems if anyone actually needs to talk another GPU using legacy VGA resources. The main issue is that X becomes a slideshow if it thinks there are multiple GPUs that have VGA decoding enabled as it insists on adjusting the VGA routing pretty much for every little operation involving any of the GPUs. The cleanup will be planned for i915. Meanwhile to focus on Xe upstreaming and have a cleaner separation, the said functionality is being moved to a different file exclusive for i915. Xe driver will re-use rest of the display code from i915. v2: Addressed Jani Nikula's review comments. v3: Dropped a duplicate function (Jani) v4: Updated commit message with reasoning as sugested by Ville. Signed-off-by: Uma Shankar Reviewed-by: Arun R Murthy Link: https://patchwork.freedesktop.org/patch/msgid/20230929074306.1533859-1-uma.shankar@intel.com --- drivers/gpu/drm/i915/display/intel_vga.c | 18 +----------------- drivers/gpu/drm/i915/soc/intel_gmch.c | 14 ++++++++++++++ drivers/gpu/drm/i915/soc/intel_gmch.h | 2 ++ 3 files changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c index 286a0bdd28c6..4b98833bfa8c 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.c +++ b/drivers/gpu/drm/i915/display/intel_vga.c @@ -3,11 +3,9 @@ * Copyright © 2019 Intel Corporation */ -#include #include #include