drm/amd/display: dc/dce: add initial DCE6 support (v10)
[Why]
DCE6 chipsets have a lot in common with DCE8, let's start from this
[How]
DCE6 targets are added replicating existing DCE8 implementation.
NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
initial build prototype due to missing DCE6 macros/registers/masks
DCE6 specific macros/registers/masks will be added with later commits
(v2b) removed dce_version cases in dc/dce/dce_clock_source.c and
updated dce60 due to following kernel 5.0 commits:
24f7dd7 ("drm/amd/display: move pplib/smu notification to dccg block")
9566b67 ("drm/amd/display: remove safe_to_lower flag from dc, use 2 functions instead")
4244381 ("drm/amd/display: clean up base dccg struct")
4c5e8b5 ("drm/amd/display: split dccg clock manager into asic folders")
84e7fc0 ("drm/amd/display: rename dccg to clk_mgr")
77f6916 ("drm/amd/display: Remove duplicate header")
9f7ddbe ("drm/amd/display: fix optimize_bandwidth func pointer for dce80")
4ece61a ("drm/amd/display: set clocks to 0 on suspend on dce80")
(v3b) updated dce60 due to following kernel 5.1 commits:
380604e ("drm/amd/display: Use 100 Hz precision for pipe pixel clocks")
32e6136 ("drm/amd/display: Fix 64-bit division for 32-bit builds")
1877ccf ("drm/amd/display: Change from aux_engine to dce_aux")
c69dffa ("drm/amd/display: fix eDP fast bootup for pre-raven asic")
(v4b) updated dce60 due to following kernel 5.2 commits:
e5c4197 ("drm/amd/display: Add plane capabilities to dc_caps")
813d20d ("drm/amd/display: Fix multi-thread writing to 1 state")
ea36ad3 ("drm/amd/display: expand plane caps to include fp16 and scaling capability")
afcd526 ("drm/amd/display: Add fast_validate parameter")
(v5b) updated dce60 due to following kernel 5.3 commits:
e7e10c4 ("drm/amd/display: stop external access to internal optc sync params")
78cc70b ("drm/amd/display: Engine-specific encoder allocation")
dc88b4a ("drm/amd/display: make clk mgr soc specific")
4fc4dca ("drm/amd: drop use of drmp.h in os_types.h")
(v6b) updated dce60 due to following kernel 5.4 commits:
54a9bcb ("drm/amd/display: Fix a typo - dce_aduio_mask --> dce_audio_mask")
9adc805 ("drm/amd/display: make firmware info only load once during dc_bios create")
(v7b) updated dce60 due to following kernel 5.5 commits:
cabe144 ("drm/amd/display: memory leak")
8276dd8 ("drm/amd/display: update register field access mechanism")
f6040a4 ("drm/amd/display: configurable aux timeout support")
bf7f5ac ("drm/amd/display: map TRANSMITTER_UNIPHY_x to LINK_REGS_x")
(v8b) updated dce60 due to following kernel 5.6 commits:
d9e3267 ("drm/amd/display: cleanup of construct and destruct funcs")
f42ea55 ("drm/amd/display: add separate of private hwss functions")
(v9b) updated dce60 due to following kernel 5.8 commits:
bba8289 ("drm/amd/display: code clean up in dce80_hw_sequencer.c")
904fb6e ("drm/amd/display: move panel power seq to new panel struct")
d4caa72 ("drm/amd/display: change from panel to panel cntl")
(v10) Fix up PLL handling for DCE6:
DCE6.0 supports 2 PLLs. DCE6.1 supports 3 PLLs. (Alex)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
pull/508/merge
Mauro Rossi
Alex Deucher
parent
f233c09842
commit
7c15fd86aa
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@ -43,6 +43,10 @@ DC_LIBS += dce110
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DC_LIBS += dce100
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DC_LIBS += dce80
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ifdef CONFIG_DRM_AMD_DC_SI
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DC_LIBS += dce60
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endif
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ifdef CONFIG_DRM_AMD_DC_HDCP
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DC_LIBS += hdcp
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endif
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@ -0,0 +1,34 @@
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#
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# Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
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#
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# Permission is hereby granted, free of charge, to any person obtaining a
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# copy of this software and associated documentation files (the "Software"),
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# to deal in the Software without restriction, including without limitation
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# the rights to use, copy, modify, merge, publish, distribute, sublicense,
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# and/or sell copies of the Software, and to permit persons to whom the
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# Software is furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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# OTHER DEALINGS IN THE SOFTWARE.
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#
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#
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# Makefile for the 'controller' sub-component of DAL.
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# It provides the control and status of HW CRTC block.
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DCE60 = dce60_timing_generator.o dce60_hw_sequencer.o \
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dce60_resource.o
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AMD_DAL_DCE60 = $(addprefix $(AMDDALPATH)/dc/dce60/,$(DCE60))
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AMD_DISPLAY_FILES += $(AMD_DAL_DCE60)
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@ -0,0 +1,54 @@
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/*
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* Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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#include "dc.h"
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#include "core_types.h"
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#include "dce60_hw_sequencer.h"
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#include "dce/dce_hwseq.h"
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#include "dce110/dce110_hw_sequencer.h"
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#include "dce100/dce100_hw_sequencer.h"
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/* include DCE8 register header files */
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#include "dce/dce_6_0_d.h"
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#include "dce/dce_6_0_sh_mask.h"
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/*******************************************************************************
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* Private definitions
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******************************************************************************/
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/***************************PIPE_CONTROL***********************************/
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void dce60_hw_sequencer_construct(struct dc *dc)
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{
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dce110_hw_sequencer_construct(dc);
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dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;
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dc->hwss.pipe_control_lock = dce_pipe_control_lock;
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dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
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dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
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}
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@ -0,0 +1,37 @@
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/*
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* Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_HWSS_DCE60_H__
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#define __DC_HWSS_DCE60_H__
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#include "core_types.h"
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#include "hw_sequencer_private.h"
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struct dc;
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void dce60_hw_sequencer_construct(struct dc *dc);
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#endif /* __DC_HWSS_DCE60_H__ */
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,47 @@
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/*
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* Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_RESOURCE_DCE60_H__
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#define __DC_RESOURCE_DCE60_H__
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#include "core_types.h"
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struct dc;
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struct resource_pool;
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struct resource_pool *dce60_create_resource_pool(
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uint8_t num_virtual_links,
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struct dc *dc);
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struct resource_pool *dce61_create_resource_pool(
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uint8_t num_virtual_links,
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struct dc *dc);
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struct resource_pool *dce64_create_resource_pool(
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uint8_t num_virtual_links,
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struct dc *dc);
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#endif /* __DC_RESOURCE_DCE60_H__ */
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@ -0,0 +1,247 @@
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/*
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* Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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/* include DCE6 register header files */
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#include "dce/dce_6_0_d.h"
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#include "dce/dce_6_0_sh_mask.h"
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#include "dc_types.h"
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#include "include/grph_object_id.h"
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#include "include/logger_interface.h"
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#include "../dce110/dce110_timing_generator.h"
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#include "dce60_timing_generator.h"
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#include "timing_generator.h"
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enum black_color_format {
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BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0, /* used as index in array */
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BLACK_COLOR_FORMAT_RGB_LIMITED,
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BLACK_COLOR_FORMAT_YUV_TV,
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BLACK_COLOR_FORMAT_YUV_CV,
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BLACK_COLOR_FORMAT_YUV_SUPER_AA,
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BLACK_COLOR_FORMAT_COUNT
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};
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static const struct dce110_timing_generator_offsets reg_offsets[] = {
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{
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.crtc = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
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.dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
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},
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{
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.crtc = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
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.dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
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},
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{
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.crtc = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
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.dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
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},
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{
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.crtc = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
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.dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
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},
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{
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.crtc = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
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.dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
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},
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{
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.crtc = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
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.dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
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}
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};
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#define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10
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#define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
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#define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1)
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#define CRTC_REG(reg) (reg + tg110->offsets.crtc)
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#define DCP_REG(reg) (reg + tg110->offsets.dcp)
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#define DMIF_REG(reg) (reg + tg110->offsets.dmif)
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static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz)
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{
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uint64_t pix_dur;
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uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
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+ DCE110TG_FROM_TG(tg)->offsets.dmif;
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uint32_t value = dm_read_reg(tg->ctx, addr);
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if (pix_clk_100hz == 0)
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return;
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pix_dur = div_u64(10000000000ull, pix_clk_100hz);
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set_reg_field_value(
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value,
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pix_dur,
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DPG_PIPE_ARBITRATION_CONTROL1,
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PIXEL_DURATION);
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dm_write_reg(tg->ctx, addr, value);
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}
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static void program_timing(struct timing_generator *tg,
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const struct dc_crtc_timing *timing,
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int vready_offset,
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int vstartup_start,
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int vupdate_offset,
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int vupdate_width,
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const enum signal_type signal,
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bool use_vbios)
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{
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if (!use_vbios)
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program_pix_dur(tg, timing->pix_clk_100hz);
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dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios);
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}
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static void dce60_timing_generator_enable_advanced_request(
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struct timing_generator *tg,
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bool enable,
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const struct dc_crtc_timing *timing)
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{
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struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
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uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
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uint32_t value = dm_read_reg(tg->ctx, addr);
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if (enable) {
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set_reg_field_value(
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value,
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0,
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CRTC_START_LINE_CONTROL,
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CRTC_LEGACY_REQUESTOR_EN);
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} else {
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set_reg_field_value(
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value,
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1,
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CRTC_START_LINE_CONTROL,
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CRTC_LEGACY_REQUESTOR_EN);
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}
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if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
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set_reg_field_value(
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value,
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3,
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CRTC_START_LINE_CONTROL,
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CRTC_ADVANCED_START_LINE_POSITION);
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set_reg_field_value(
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value,
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0,
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CRTC_START_LINE_CONTROL,
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CRTC_PREFETCH_EN);
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} else {
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set_reg_field_value(
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value,
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4,
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CRTC_START_LINE_CONTROL,
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CRTC_ADVANCED_START_LINE_POSITION);
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set_reg_field_value(
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value,
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1,
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CRTC_START_LINE_CONTROL,
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CRTC_PREFETCH_EN);
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}
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set_reg_field_value(
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value,
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1,
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CRTC_START_LINE_CONTROL,
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CRTC_PROGRESSIVE_START_LINE_EARLY);
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set_reg_field_value(
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value,
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1,
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CRTC_START_LINE_CONTROL,
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CRTC_INTERLACE_START_LINE_EARLY);
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dm_write_reg(tg->ctx, addr, value);
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}
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static const struct timing_generator_funcs dce60_tg_funcs = {
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.validate_timing = dce110_tg_validate_timing,
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.program_timing = program_timing,
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.enable_crtc = dce110_timing_generator_enable_crtc,
|
||||
.disable_crtc = dce110_timing_generator_disable_crtc,
|
||||
.is_counter_moving = dce110_timing_generator_is_counter_moving,
|
||||
.get_position = dce110_timing_generator_get_position,
|
||||
.get_frame_count = dce110_timing_generator_get_vblank_counter,
|
||||
.get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos,
|
||||
.set_early_control = dce110_timing_generator_set_early_control,
|
||||
.wait_for_state = dce110_tg_wait_for_state,
|
||||
.set_blank = dce110_tg_set_blank,
|
||||
.is_blanked = dce110_tg_is_blanked,
|
||||
.set_colors = dce110_tg_set_colors,
|
||||
.set_overscan_blank_color =
|
||||
dce110_timing_generator_set_overscan_color_black,
|
||||
.set_blank_color = dce110_timing_generator_program_blank_color,
|
||||
.disable_vga = dce110_timing_generator_disable_vga,
|
||||
.did_triggered_reset_occur =
|
||||
dce110_timing_generator_did_triggered_reset_occur,
|
||||
.setup_global_swap_lock =
|
||||
dce110_timing_generator_setup_global_swap_lock,
|
||||
.enable_reset_trigger = dce110_timing_generator_enable_reset_trigger,
|
||||
.disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
|
||||
.tear_down_global_swap_lock =
|
||||
dce110_timing_generator_tear_down_global_swap_lock,
|
||||
.set_drr = dce110_timing_generator_set_drr,
|
||||
.set_static_screen_control =
|
||||
dce110_timing_generator_set_static_screen_control,
|
||||
.set_test_pattern = dce110_timing_generator_set_test_pattern,
|
||||
.arm_vert_intr = dce110_arm_vert_intr,
|
||||
|
||||
/* DCE6.0 overrides */
|
||||
.enable_advanced_request =
|
||||
dce60_timing_generator_enable_advanced_request,
|
||||
.configure_crc = dce110_configure_crc,
|
||||
.get_crc = dce110_get_crc,
|
||||
};
|
||||
|
||||
void dce60_timing_generator_construct(
|
||||
struct dce110_timing_generator *tg110,
|
||||
struct dc_context *ctx,
|
||||
uint32_t instance,
|
||||
const struct dce110_timing_generator_offsets *offsets)
|
||||
{
|
||||
tg110->controller_id = CONTROLLER_ID_D0 + instance;
|
||||
tg110->base.inst = instance;
|
||||
tg110->offsets = *offsets;
|
||||
tg110->derived_offsets = reg_offsets[instance];
|
||||
|
||||
tg110->base.funcs = &dce60_tg_funcs;
|
||||
|
||||
tg110->base.ctx = ctx;
|
||||
tg110->base.bp = ctx->dc_bios;
|
||||
|
||||
tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
|
||||
tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
|
||||
|
||||
tg110->min_h_blank = 56;
|
||||
tg110->min_h_front_porch = 4;
|
||||
tg110->min_h_back_porch = 4;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DC_TIMING_GENERATOR_DCE60_H__
|
||||
#define __DC_TIMING_GENERATOR_DCE60_H__
|
||||
|
||||
#include "timing_generator.h"
|
||||
#include "../include/grph_object_id.h"
|
||||
|
||||
/* DCE6.0 implementation inherits from DCE11.0 */
|
||||
void dce60_timing_generator_construct(
|
||||
struct dce110_timing_generator *tg,
|
||||
struct dc_context *ctx,
|
||||
uint32_t instance,
|
||||
const struct dce110_timing_generator_offsets *offsets);
|
||||
|
||||
#endif /* __DC_TIMING_GENERATOR_DCE60_H__ */
|
||||
Loading…
Reference in New Issue