- Use a freezable workqueue for RTC sync because the sync can happen at any time
and trigger suspend assertion checks in the i2c subsystem.
- Correct a previous RTC validation change to check only bit 6 in register D
because some Intel machines use bits 0-5.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmAfxt8ACgkQEsHwGGHe
VUqGnQ//W1gu/MyIGauA2Ds6WHtvgguyOLUfjQbykSXXHol9aygcdray6Zhca/+D
6bf7gudkIQVYy6A38dD6tH1/2brHelY9SsxJ/MOhKJ2zh3wistdV4tJsH682Dp8G
9BgmLYkc/QRuSMh04GKL+UoXxdv3IsDy6q2dZfMoQj6cDwx65JL2qdIp4HvAYZ+B
FwF8BJxakLGr4ZHRurYQaT/+OKwc6rrF1/ix8zGl6sN8BATZTbcn0SVHWiiaoNlj
TVXDLoVUHWw1X3xWdLwZlhD0SPsc1f3nO8Y+q/86zbf0r9YUJVq5dhuAqRRcAl2L
CQDDmOUJLmtf6S2ZOcbQIRbC0gjQulMGoEOVZclYa8x1eeUywBwyHSZwVVzhvyVC
jvtXu9yW7Y0kAbKbQnL42hwVJra+0fIwIG1ay3h2kZzlBKazxSom2JozFuhcQ/6M
gNbHk8QZ4FPDNVl/gN6hxDtKcVv6ObvZGZnNbr6xjRCUSJ57O/kcmq/vkwYeRof/
vS2SPaY6OifrBYQVuH10CxpE4HJBA309eQ1vdwHtfq5+IcJE50XBNNm5VG1xu5h3
RQQINsQXg8+mERT1Jkpyy/JTTnBje2Hp0qxyC6FYRwDsBjNv8HjrhZT/H2rTWioG
a3D9BZ0tcnJK/pu47FlA9gKQ2WMrnSJ7K2nHjHam5su0iIZTRk4=
=UHNm
-----END PGP SIGNATURE-----
Merge tag 'timers_urgent_for_v5.11_rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer fixes from Borislav Petkov:
"Two more timers-related fixes for v5.11:
- Use a freezable workqueue for RTC sync because the sync can happen
at any time and trigger suspend assertion checks in the i2c
subsystem.
- Correct a previous RTC validation change to check only bit 6 in
register D because some Intel machines use bits 0-5"
* tag 'timers_urgent_for_v5.11_rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
ntp: Use freezable workqueue for RTC synchronization
rtc: mc146818: Dont test for bit 0-5 in Register D
pull/634/merge
commit
814daadbf0
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@ -805,8 +805,8 @@ cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq)
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spin_lock_irq(&rtc_lock);
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/* Ensure that the RTC is accessible. Bit 0-6 must be 0! */
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if ((CMOS_READ(RTC_VALID) & 0x7f) != 0) {
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/* Ensure that the RTC is accessible. Bit 6 must be 0! */
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if ((CMOS_READ(RTC_VALID) & 0x40) != 0) {
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spin_unlock_irq(&rtc_lock);
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dev_warn(dev, "not accessible\n");
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retval = -ENXIO;
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@ -21,8 +21,8 @@ unsigned int mc146818_get_time(struct rtc_time *time)
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again:
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spin_lock_irqsave(&rtc_lock, flags);
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/* Ensure that the RTC is accessible. Bit 0-6 must be 0! */
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if (WARN_ON_ONCE((CMOS_READ(RTC_VALID) & 0x7f) != 0)) {
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/* Ensure that the RTC is accessible. Bit 6 must be 0! */
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if (WARN_ON_ONCE((CMOS_READ(RTC_VALID) & 0x40) != 0)) {
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spin_unlock_irqrestore(&rtc_lock, flags);
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memset(time, 0xff, sizeof(*time));
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return 0;
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@ -502,7 +502,7 @@ static struct hrtimer sync_hrtimer;
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static enum hrtimer_restart sync_timer_callback(struct hrtimer *timer)
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{
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queue_work(system_power_efficient_wq, &sync_work);
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queue_work(system_freezable_power_efficient_wq, &sync_work);
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return HRTIMER_NORESTART;
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}
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@ -668,7 +668,7 @@ void ntp_notify_cmos_timer(void)
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* just a pointless work scheduled.
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*/
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if (ntp_synced() && !hrtimer_is_queued(&sync_hrtimer))
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queue_work(system_power_efficient_wq, &sync_work);
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queue_work(system_freezable_power_efficient_wq, &sync_work);
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}
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static void __init ntp_init_cmos_sync(void)
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Loading…
Reference in New Issue