OpenRISC updates for 6.16

Just a few documentation updates from the community.
 
  - Device tree documentation conversion from txt to yaml.
  - Documentation addition to help users getting started with initramfs
    on OpenRISC.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEE2cRzVK74bBA6Je/xw7McLV5mJ+QFAmg8H/8ACgkQw7McLV5m
 J+R1mg//dG1Kpu/jEfJawfgzU0ck+rtrtVZ/ybYByHPTzlavvqX1UTf0+x1JXnT+
 VtoQqFrEVdefRXZqLWr34L6RpSt/6hfvOAGF7reGml5JqWRxWgrpNjnE20ej/UhY
 61vMotnM+wrpQ9ystGTnXy+ufkkMAyUzOAVKTjXkixrK+gW4Y8AQgfD/IJosS1vB
 DwUzgSeO/ZpcwLBKxTpkJi1JONdyVa4oxDNTlq9MdMcvWAyPSF4Bn9HQsjCjHRl3
 MVpm/10b59JH1RxoNqjjnaWN9YUGHUATI1umTY7BrpwTgl2g5qkGKTjC1iM2g2ys
 B0xuND89wZbcVGnbUclIslb7bcyaKD/1MD6h/bW1DZ/NUfwloWKDFRtDkHTlkxbp
 Kza+6B81sITnclZPH9WUA4zx/9+PkDLdGNr52lEzCRFqYA2KgxjEpaz7bAp9hsp9
 DT28CzyfW2rREDJu6PrLzwUr1r3yjcGdNKDXl2XoqdBGFkSbs4gnD866kpJa5Ik+
 jU+N7jjjma8BdxZQ6PD65AugEhAlzumfGf01ZJjJ2ugNvBTjGpqskGlepS7gOh4d
 B9l6YdS1ko9v87k0uqnz75w/2XVaGnOToi2vAOTxkNnBJV3YRQVRimn38w0EB8lz
 9yvr29B/GeRQuxxW1E0Qvaymjiix82v8JSzYwFDRtwF1jpmpK7Y=
 =XBzJ
 -----END PGP SIGNATURE-----

Merge tag 'for-linus' of https://github.com/openrisc/linux

Pull OpenRISC updates from Stafford Horne:
 "Just a few documentation updates from the community:

   - Device tree documentation conversion from txt to yaml

   - Documentation addition to help users getting started with initramfs
     on OpenRISC

* tag 'for-linus' of https://github.com/openrisc/linux:
  dt-bindings: interrupt-controller: Convert openrisc,ompic to DT schema
  dt-bindings: interrupt-controller: Convert opencores,or1k-pic to DT schema
  Documentation:openrisc: Add build instructions with initramfs

Documentation/arch/openrisc/openrisc_port.rst

@@ -40,6 +40,12 @@ Build the Linux kernel as usual::
 	make ARCH=openrisc CROSS_COMPILE="or1k-linux-" defconfig
 	make ARCH=openrisc CROSS_COMPILE="or1k-linux-"
 
+If you want to embed initramfs in the kernel, also pass ``CONFIG_INITRAMFS_SOURCE``. For example::
+
+	make ARCH=openrisc CROSS_COMPILE="or1k-linux-" CONFIG_INITRAMFS_SOURCE="path/to/rootfs path/to/devnodes"
+
+For more information on this, please check Documentation/filesystems/ramfs-rootfs-initramfs.rst.
+
 3) Running on FPGA (optional)
 
 The OpenRISC community typically uses FuseSoC to manage building and programming

Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.txt

@@ -1,23 +0,0 @@
-OpenRISC 1000 Programmable Interrupt Controller
-
-Required properties:
-
-- compatible : should be "opencores,or1k-pic-level" for variants with
-  level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
-  edge triggered interrupt lines or "opencores,or1200-pic" for machines
-  with the non-spec compliant or1200 type implementation.
-
-  "opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",
-  but this is only for backwards compatibility.
-
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
-  interrupt source. The value shall be 1.
-
-Example:
-
-intc: interrupt-controller {
-	compatible = "opencores,or1k-pic-level";
-	interrupt-controller;
-	#interrupt-cells = <1>;
-};

Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.yaml

@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/opencores,or1k-pic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: OpenRISC 1000 Programmable Interrupt Controller
+
+maintainers:
+  - Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+
+properties:
+  compatible:
+    enum:
+      - opencores,or1k-pic-level
+      - opencores,or1k-pic-edge
+      - opencores,or1200-pic
+      - opencores,or1k-pic
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 1
+
+required:
+  - compatible
+  - interrupt-controller
+  - '#interrupt-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    interrupt-controller {
+        compatible = "opencores,or1k-pic-level";
+        interrupt-controller;
+        #interrupt-cells = <1>;
+    };

Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt

@@ -1,22 +0,0 @@
-Open Multi-Processor Interrupt Controller
-
-Required properties:
-
-- compatible : This should be "openrisc,ompic"
-- reg : Specifies base physical address and size of the register space. The
-  size is based on the number of cores the controller has been configured
-  to handle, this should be set to 8 bytes per cpu core.
-- interrupt-controller : Identifies the node as an interrupt controller.
-- #interrupt-cells : This should be set to 0 as this will not be an irq
-  parent.
-- interrupts : Specifies the interrupt line to which the ompic is wired.
-
-Example:
-
-ompic: interrupt-controller@98000000 {
-	compatible = "openrisc,ompic";
-	reg = <0x98000000 16>;
-	interrupt-controller;
-	#interrupt-cells = <0>;
-	interrupts = <1>;
-};

Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.yaml

@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/openrisc,ompic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Open Multi-Processor Interrupt Controller
+
+maintainers:
+  - Stafford Horne <shorne@gmail.com>
+
+properties:
+  compatible:
+    items:
+      - const: openrisc,ompic
+
+  reg:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 0
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupt-controller
+  - '#interrupt-cells'
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    interrupt-controller@98000000 {
+        compatible = "openrisc,ompic";
+        reg = <0x98000000 16>;
+        interrupt-controller;
+        #interrupt-cells = <0>;
+        interrupts = <1>;
+    };