r8152: Add helper functions for SRAM2
Add the following helper functions for SRAM2 access to simplify the code and improve readability: - sram2_write() - write data to SRAM2 address - sram2_read() - read data from SRAM2 address - sram2_write_w0w1() - read-modify-write operation Signed-off-by: Chih Kai Hsu <hsu.chih.kai@realtek.com> Reviewed-by: Hayes Wang <hayeswang@realtek.com> Link: https://patch.msgid.link/20260401115542.34601-1-nic_swsd@realtek.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>master
Chih Kai Hsu
Jakub Kicinski
parent
7eaff1eff0
commit
86f5dd4e0f
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@ -213,6 +213,8 @@
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#define OCP_PHY_PATCH_STAT 0xb800
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#define OCP_PHY_PATCH_CMD 0xb820
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#define OCP_PHY_LOCK 0xb82e
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#define OCP_SRAM2_ADDR 0xb87c
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#define OCP_SRAM2_DATA 0xb87e
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#define OCP_ADC_IOFFSET 0xbcfc
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#define OCP_ADC_CFG 0xbc06
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#define OCP_SYSCLK_CFG 0xc416
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@ -1764,6 +1766,27 @@ static void sram_set_bits(struct r8152 *tp, u16 addr, u16 set)
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sram_write_w0w1(tp, addr, 0, set);
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}
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static void sram2_write(struct r8152 *tp, u16 addr, u16 data)
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{
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ocp_reg_write(tp, OCP_SRAM2_ADDR, addr);
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ocp_reg_write(tp, OCP_SRAM2_DATA, data);
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}
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static u16 sram2_read(struct r8152 *tp, u16 addr)
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{
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ocp_reg_write(tp, OCP_SRAM2_ADDR, addr);
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return ocp_reg_read(tp, OCP_SRAM2_DATA);
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}
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static void sram2_write_w0w1(struct r8152 *tp, u16 addr, u16 clear, u16 set)
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{
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u16 data;
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data = sram2_read(tp, addr);
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data = (data & ~clear) | set;
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ocp_reg_write(tp, OCP_SRAM2_DATA, data);
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}
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static void r8152_mdio_clr_bit(struct r8152 *tp, u16 addr, u16 clear)
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{
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int data;
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@ -7195,16 +7218,12 @@ static void r8156_hw_phy_cfg(struct r8152 *tp)
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ocp_reg_write(tp, 0xad4c, 0x00a8);
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ocp_reg_write(tp, 0xac5c, 0x01ff);
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ocp_reg_w0w1(tp, 0xac8a, 0xf0, BIT(4) | BIT(5));
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ocp_reg_write(tp, 0xb87c, 0x8157);
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ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0500);
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ocp_reg_write(tp, 0xb87c, 0x8159);
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ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0700);
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sram2_write_w0w1(tp, 0x8157, 0xff00, 0x0500);
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sram2_write_w0w1(tp, 0x8159, 0xff00, 0x0700);
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/* AAGC */
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ocp_reg_write(tp, 0xb87c, 0x80a2);
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ocp_reg_write(tp, 0xb87e, 0x0153);
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ocp_reg_write(tp, 0xb87c, 0x809c);
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ocp_reg_write(tp, 0xb87e, 0x0153);
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sram2_write(tp, 0x80a2, 0x0153);
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sram2_write(tp, 0x809c, 0x0153);
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/* EEE parameter */
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ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);
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@ -7402,82 +7421,48 @@ static void r8156b_hw_phy_cfg(struct r8152 *tp)
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ocp_reg_write(tp, 0xacc8, 0xa0d3);
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ocp_reg_write(tp, 0xad08, 0x0007);
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ocp_reg_write(tp, 0xb87c, 0x8560);
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ocp_reg_write(tp, 0xb87e, 0x19cc);
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ocp_reg_write(tp, 0xb87c, 0x8562);
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ocp_reg_write(tp, 0xb87e, 0x19cc);
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ocp_reg_write(tp, 0xb87c, 0x8564);
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ocp_reg_write(tp, 0xb87e, 0x19cc);
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ocp_reg_write(tp, 0xb87c, 0x8566);
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ocp_reg_write(tp, 0xb87e, 0x147d);
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ocp_reg_write(tp, 0xb87c, 0x8568);
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ocp_reg_write(tp, 0xb87e, 0x147d);
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ocp_reg_write(tp, 0xb87c, 0x856a);
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ocp_reg_write(tp, 0xb87e, 0x147d);
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ocp_reg_write(tp, 0xb87c, 0x8ffe);
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ocp_reg_write(tp, 0xb87e, 0x0907);
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ocp_reg_write(tp, 0xb87c, 0x80d6);
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ocp_reg_write(tp, 0xb87e, 0x2801);
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ocp_reg_write(tp, 0xb87c, 0x80f2);
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ocp_reg_write(tp, 0xb87e, 0x2801);
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ocp_reg_write(tp, 0xb87c, 0x80f4);
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ocp_reg_write(tp, 0xb87e, 0x6077);
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sram2_write(tp, 0x8560, 0x19cc);
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sram2_write(tp, 0x8562, 0x19cc);
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sram2_write(tp, 0x8564, 0x19cc);
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sram2_write(tp, 0x8566, 0x147d);
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sram2_write(tp, 0x8568, 0x147d);
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sram2_write(tp, 0x856a, 0x147d);
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sram2_write(tp, 0x8ffe, 0x0907);
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sram2_write(tp, 0x80d6, 0x2801);
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sram2_write(tp, 0x80f2, 0x2801);
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sram2_write(tp, 0x80f4, 0x6077);
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ocp_reg_write(tp, 0xb506, 0x01e7);
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ocp_reg_write(tp, 0xb87c, 0x8013);
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ocp_reg_write(tp, 0xb87e, 0x0700);
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ocp_reg_write(tp, 0xb87c, 0x8fb9);
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ocp_reg_write(tp, 0xb87e, 0x2801);
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ocp_reg_write(tp, 0xb87c, 0x8fba);
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ocp_reg_write(tp, 0xb87e, 0x0100);
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ocp_reg_write(tp, 0xb87c, 0x8fbc);
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ocp_reg_write(tp, 0xb87e, 0x1900);
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ocp_reg_write(tp, 0xb87c, 0x8fbe);
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ocp_reg_write(tp, 0xb87e, 0xe100);
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ocp_reg_write(tp, 0xb87c, 0x8fc0);
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ocp_reg_write(tp, 0xb87e, 0x0800);
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ocp_reg_write(tp, 0xb87c, 0x8fc2);
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ocp_reg_write(tp, 0xb87e, 0xe500);
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ocp_reg_write(tp, 0xb87c, 0x8fc4);
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ocp_reg_write(tp, 0xb87e, 0x0f00);
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ocp_reg_write(tp, 0xb87c, 0x8fc6);
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ocp_reg_write(tp, 0xb87e, 0xf100);
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ocp_reg_write(tp, 0xb87c, 0x8fc8);
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ocp_reg_write(tp, 0xb87e, 0x0400);
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ocp_reg_write(tp, 0xb87c, 0x8fca);
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ocp_reg_write(tp, 0xb87e, 0xf300);
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ocp_reg_write(tp, 0xb87c, 0x8fcc);
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ocp_reg_write(tp, 0xb87e, 0xfd00);
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ocp_reg_write(tp, 0xb87c, 0x8fce);
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ocp_reg_write(tp, 0xb87e, 0xff00);
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ocp_reg_write(tp, 0xb87c, 0x8fd0);
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ocp_reg_write(tp, 0xb87e, 0xfb00);
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ocp_reg_write(tp, 0xb87c, 0x8fd2);
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ocp_reg_write(tp, 0xb87e, 0x0100);
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ocp_reg_write(tp, 0xb87c, 0x8fd4);
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ocp_reg_write(tp, 0xb87e, 0xf400);
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ocp_reg_write(tp, 0xb87c, 0x8fd6);
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ocp_reg_write(tp, 0xb87e, 0xff00);
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ocp_reg_write(tp, 0xb87c, 0x8fd8);
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ocp_reg_write(tp, 0xb87e, 0xf600);
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sram2_write(tp, 0x8013, 0x0700);
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sram2_write(tp, 0x8fb9, 0x2801);
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sram2_write(tp, 0x8fba, 0x0100);
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sram2_write(tp, 0x8fbc, 0x1900);
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sram2_write(tp, 0x8fbe, 0xe100);
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sram2_write(tp, 0x8fc0, 0x0800);
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sram2_write(tp, 0x8fc2, 0xe500);
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sram2_write(tp, 0x8fc4, 0x0f00);
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sram2_write(tp, 0x8fc6, 0xf100);
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sram2_write(tp, 0x8fc8, 0x0400);
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sram2_write(tp, 0x8fca, 0xf300);
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sram2_write(tp, 0x8fcc, 0xfd00);
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sram2_write(tp, 0x8fce, 0xff00);
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sram2_write(tp, 0x8fd0, 0xfb00);
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sram2_write(tp, 0x8fd2, 0x0100);
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sram2_write(tp, 0x8fd4, 0xf400);
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sram2_write(tp, 0x8fd6, 0xff00);
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sram2_write(tp, 0x8fd8, 0xf600);
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ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_USB_CFG,
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EN_XG_LIP | EN_G_LIP);
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ocp_reg_write(tp, 0xb87c, 0x813d);
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ocp_reg_write(tp, 0xb87e, 0x390e);
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ocp_reg_write(tp, 0xb87c, 0x814f);
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ocp_reg_write(tp, 0xb87e, 0x790e);
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ocp_reg_write(tp, 0xb87c, 0x80b0);
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ocp_reg_write(tp, 0xb87e, 0x0f31);
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sram2_write(tp, 0x813d, 0x390e);
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sram2_write(tp, 0x814f, 0x790e);
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sram2_write(tp, 0x80b0, 0x0f31);
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ocp_reg_set_bits(tp, 0xbf4c, BIT(1));
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ocp_reg_set_bits(tp, 0xbcca, BIT(9) | BIT(8));
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ocp_reg_write(tp, 0xb87c, 0x8141);
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ocp_reg_write(tp, 0xb87e, 0x320e);
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ocp_reg_write(tp, 0xb87c, 0x8153);
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ocp_reg_write(tp, 0xb87e, 0x720e);
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ocp_reg_write(tp, 0xb87c, 0x8529);
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ocp_reg_write(tp, 0xb87e, 0x050e);
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sram2_write(tp, 0x8141, 0x320e);
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sram2_write(tp, 0x8153, 0x720e);
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sram2_write(tp, 0x8529, 0x050e);
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ocp_reg_clr_bits(tp, OCP_EEE_CFG, CTAP_SHORT_EN);
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sram_write(tp, 0x816c, 0xc4a0);
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@ -7489,27 +7474,17 @@ static void r8156b_hw_phy_cfg(struct r8152 *tp)
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sram_write(tp, 0x8ff1, 0x0404);
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ocp_reg_write(tp, 0xbf4a, 0x001b);
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ocp_reg_write(tp, 0xb87c, 0x8033);
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ocp_reg_write(tp, 0xb87e, 0x7c13);
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ocp_reg_write(tp, 0xb87c, 0x8037);
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ocp_reg_write(tp, 0xb87e, 0x7c13);
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ocp_reg_write(tp, 0xb87c, 0x803b);
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ocp_reg_write(tp, 0xb87e, 0xfc32);
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ocp_reg_write(tp, 0xb87c, 0x803f);
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ocp_reg_write(tp, 0xb87e, 0x7c13);
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ocp_reg_write(tp, 0xb87c, 0x8043);
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ocp_reg_write(tp, 0xb87e, 0x7c13);
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ocp_reg_write(tp, 0xb87c, 0x8047);
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ocp_reg_write(tp, 0xb87e, 0x7c13);
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sram2_write(tp, 0x8033, 0x7c13);
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sram2_write(tp, 0x8037, 0x7c13);
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sram2_write(tp, 0x803b, 0xfc32);
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sram2_write(tp, 0x803f, 0x7c13);
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sram2_write(tp, 0x8043, 0x7c13);
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sram2_write(tp, 0x8047, 0x7c13);
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ocp_reg_write(tp, 0xb87c, 0x8145);
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ocp_reg_write(tp, 0xb87e, 0x370e);
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ocp_reg_write(tp, 0xb87c, 0x8157);
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ocp_reg_write(tp, 0xb87e, 0x770e);
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ocp_reg_write(tp, 0xb87c, 0x8169);
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ocp_reg_write(tp, 0xb87e, 0x0d0a);
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ocp_reg_write(tp, 0xb87c, 0x817b);
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ocp_reg_write(tp, 0xb87e, 0x1d0a);
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sram2_write(tp, 0x8145, 0x370e);
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sram2_write(tp, 0x8157, 0x770e);
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sram2_write(tp, 0x8169, 0x0d0a);
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sram2_write(tp, 0x817b, 0x1d0a);
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sram_write_w0w1(tp, 0x8217, 0xff00, 0x5000);
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sram_write_w0w1(tp, 0x821a, 0xff00, 0x5000);
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@ -7574,12 +7549,9 @@ static void r8156b_hw_phy_cfg(struct r8152 *tp)
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fallthrough;
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case RTL_VER_15:
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/* EEE parameter */
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ocp_reg_write(tp, 0xb87c, 0x80f5);
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ocp_reg_write(tp, 0xb87e, 0x760e);
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ocp_reg_write(tp, 0xb87c, 0x8107);
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ocp_reg_write(tp, 0xb87e, 0x360e);
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ocp_reg_write(tp, 0xb87c, 0x8551);
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ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0800);
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sram2_write(tp, 0x80f5, 0x760e);
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sram2_write(tp, 0x8107, 0x360e);
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sram2_write_w0w1(tp, 0x8551, 0xff00, 0x0800);
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/* ADC_PGA parameter */
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ocp_reg_w0w1(tp, 0xbf00, 0xe000, 0xa000);
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