drm/amd/display: Add DCN35 CLK_MGR
[Why & How] Add CLK_MGR handling for DCN35. v2: Drop stale SMU interfaces (Alex) Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>pull/806/head
Qingqing Zhuo
Alex Deucher
parent
6f8b7565cc
commit
8774029f76
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@ -1680,6 +1680,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
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init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
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init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
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init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];
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INIT_LIST_HEAD(&adev->dm.da_list);
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@ -172,4 +172,12 @@ AMD_DAL_CLK_MGR_DCN32 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn32/,$(CLK_MGR_DC
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AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN32)
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###############################################################################
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# DCN35
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###############################################################################
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CLK_MGR_DCN35 = dcn35_smu.o dcn35_clk_mgr.o
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AMD_DAL_CLK_MGR_DCN35 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn35/,$(CLK_MGR_DCN35))
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AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN35)
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endif
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@ -48,6 +48,7 @@
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#include "dcn315/dcn315_clk_mgr.h"
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#include "dcn316/dcn316_clk_mgr.h"
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#include "dcn32/dcn32_clk_mgr.h"
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#include "dcn35/dcn35_clk_mgr.h"
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int clk_mgr_helper_get_active_display_cnt(
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struct dc *dc,
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@ -405,6 +406,10 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
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dcn314_clk_mgr_destroy(clk_mgr);
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break;
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case AMDGPU_FAMILY_GC_11_5_0:
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dcn35_clk_mgr_destroy(clk_mgr);
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break;
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default:
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break;
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}
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,63 @@
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/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DCN35_CLK_MGR_H__
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#define __DCN35_CLK_MGR_H__
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#include "clk_mgr_internal.h"
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#define NUM_CLOCK_SOURCES 5
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struct dcn35_watermarks;
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struct dcn35_smu_watermark_set {
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struct dcn35_watermarks *wm_set;
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union large_integer mc_address;
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};
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struct dcn35_ss_info_table {
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uint32_t ss_divider;
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uint32_t ss_percentage[NUM_CLOCK_SOURCES];
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};
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struct clk_mgr_dcn35 {
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struct clk_mgr_internal base;
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struct dcn35_smu_watermark_set smu_wm_set;
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};
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bool dcn35_are_clock_states_equal(struct dc_clocks *a,
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struct dc_clocks *b);
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void dcn35_init_clocks(struct clk_mgr *clk_mgr);
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void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
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struct dc_state *context,
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bool safe_to_lower);
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void dcn35_clk_mgr_construct(struct dc_context *ctx,
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struct clk_mgr_dcn35 *clk_mgr,
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struct pp_smu_funcs *pp_smu,
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struct dccg *dccg);
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void dcn35_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);
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#endif //__DCN35_CLK_MGR_H__
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@ -0,0 +1,453 @@
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/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "core_types.h"
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#include "clk_mgr_internal.h"
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#include "reg_helper.h"
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#include "dm_helpers.h"
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#include "dcn35_smu.h"
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#include "mp/mp_14_0_0_offset.h"
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#include "mp/mp_14_0_0_sh_mask.h"
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/* TODO: Use the real headers when they're correct */
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#define MP1_BASE__INST0_SEG0 0x00016000
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#define MP1_BASE__INST0_SEG1 0x0243FC00
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#define MP1_BASE__INST0_SEG2 0x00DC0000
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#define MP1_BASE__INST0_SEG3 0x00E00000
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#define MP1_BASE__INST0_SEG4 0x00E40000
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#define MP1_BASE__INST0_SEG5 0
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#ifdef BASE_INNER
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#undef BASE_INNER
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#endif
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#define BASE_INNER(seg) MP1_BASE__INST0_SEG ## seg
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#define BASE(seg) BASE_INNER(seg)
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#define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
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#define FN(reg_name, field) \
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FD(reg_name##__##field)
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#include "logger_types.h"
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#undef DC_LOGGER
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#define DC_LOGGER \
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CTX->logger
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#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
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#define VBIOSSMC_MSG_TestMessage 0x1
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#define VBIOSSMC_MSG_GetSmuVersion 0x2
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#define VBIOSSMC_MSG_PowerUpGfx 0x3
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#define VBIOSSMC_MSG_SetDispclkFreq 0x4
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#define VBIOSSMC_MSG_SetDprefclkFreq 0x5 //Not used. DPRef is constant
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#define VBIOSSMC_MSG_SetDppclkFreq 0x6
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#define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x7
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#define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x8
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#define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0x9 //Keep it in case VMIN dees not support phy clk
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#define VBIOSSMC_MSG_GetFclkFrequency 0xA
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#define VBIOSSMC_MSG_SetDisplayCount 0xB //Not used anymore
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#define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xC //To ask PMFW turn off TMDP 48MHz refclk during display off to save power
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#define VBIOSSMC_MSG_UpdatePmeRestore 0xD
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#define VBIOSSMC_MSG_SetVbiosDramAddrHigh 0xE //Used for WM table txfr
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#define VBIOSSMC_MSG_SetVbiosDramAddrLow 0xF
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#define VBIOSSMC_MSG_TransferTableSmu2Dram 0x10
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#define VBIOSSMC_MSG_TransferTableDram2Smu 0x11
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#define VBIOSSMC_MSG_SetDisplayIdleOptimizations 0x12
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#define VBIOSSMC_MSG_GetDprefclkFreq 0x13
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#define VBIOSSMC_MSG_GetDtbclkFreq 0x14
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#define VBIOSSMC_MSG_AllowZstatesEntry 0x15
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#define VBIOSSMC_MSG_DisallowZstatesEntry 0x16
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#define VBIOSSMC_MSG_SetDtbClk 0x17
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#define VBIOSSMC_MSG_DispPsrEntry 0x18 ///< Display PSR entry, DMU
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#define VBIOSSMC_MSG_DispPsrExit 0x19 ///< Display PSR exit, DMU
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#define VBIOSSMC_Message_Count 0x1A
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#define VBIOSSMC_Status_BUSY 0x0
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#define VBIOSSMC_Result_OK 0x1
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#define VBIOSSMC_Result_Failed 0xFF
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#define VBIOSSMC_Result_UnknownCmd 0xFE
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#define VBIOSSMC_Result_CmdRejectedPrereq 0xFD
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#define VBIOSSMC_Result_CmdRejectedBusy 0xFC
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/*
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* Function to be used instead of REG_WAIT macro because the wait ends when
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* the register is NOT EQUAL to zero, and because `the translation in msg_if.h
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* won't work with REG_WAIT.
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*/
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static uint32_t dcn35_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
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{
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uint32_t res_val = VBIOSSMC_Status_BUSY;
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do {
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res_val = REG_READ(MP1_SMN_C2PMSG_91);
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if (res_val != VBIOSSMC_Status_BUSY)
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break;
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if (delay_us >= 1000)
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msleep(delay_us/1000);
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else if (delay_us > 0)
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udelay(delay_us);
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} while (max_retries--);
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return res_val;
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}
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static int dcn35_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
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unsigned int msg_id,
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unsigned int param)
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{
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uint32_t result;
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result = dcn35_smu_wait_for_response(clk_mgr, 10, 2000000);
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ASSERT(result == VBIOSSMC_Result_OK);
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if (result == VBIOSSMC_Status_BUSY) {
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smu_print("SMU response after wait: %d\n", result);
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return -1;
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}
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/* First clear response register */
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REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
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/* Set the parameter register for the SMU message, unit is Mhz */
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REG_WRITE(MP1_SMN_C2PMSG_83, param);
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/* Trigger the message transaction by writing the message ID */
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REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
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result = dcn35_smu_wait_for_response(clk_mgr, 10, 2000000);
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if (result == VBIOSSMC_Result_Failed) {
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if (msg_id == VBIOSSMC_MSG_TransferTableDram2Smu &&
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param == TABLE_WATERMARKS)
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DC_LOG_WARNING("Watermarks table not configured properly by SMU");
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else
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ASSERT(0);
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REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK);
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smu_print("SMU response after wait: %d\n", result);
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return -1;
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}
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if (IS_SMU_TIMEOUT(result)) {
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ASSERT(0);
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result = dcn35_smu_wait_for_response(clk_mgr, 10, 2000000);
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//dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);
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smu_print("SMU response after wait: %d\n", result);
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}
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return REG_READ(MP1_SMN_C2PMSG_83);
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}
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int dcn35_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
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{
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return dcn35_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_GetSmuVersion,
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0);
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}
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int dcn35_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
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{
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int actual_dispclk_set_mhz = -1;
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if (!clk_mgr->smu_present)
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return requested_dispclk_khz;
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/* Unit of SMU msg parameter is Mhz */
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actual_dispclk_set_mhz = dcn35_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetDispclkFreq,
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khz_to_mhz_ceil(requested_dispclk_khz));
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smu_print("requested_dispclk_khz = %d, actual_dispclk_set_mhz: %d\n", requested_dispclk_khz, actual_dispclk_set_mhz);
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return actual_dispclk_set_mhz * 1000;
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}
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int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
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{
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int actual_dprefclk_set_mhz = -1;
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if (!clk_mgr->smu_present)
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return clk_mgr->base.dprefclk_khz;
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actual_dprefclk_set_mhz = dcn35_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetDprefclkFreq,
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khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz));
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/* TODO: add code for programing DP DTO, currently this is down by command table */
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return actual_dprefclk_set_mhz * 1000;
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}
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int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
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{
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int actual_dcfclk_set_mhz = -1;
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if (!clk_mgr->smu_present)
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return requested_dcfclk_khz;
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actual_dcfclk_set_mhz = dcn35_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
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khz_to_mhz_ceil(requested_dcfclk_khz));
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smu_print("requested_dcfclk_khz = %d, actual_dcfclk_set_mhz: %d\n", requested_dcfclk_khz, actual_dcfclk_set_mhz);
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return actual_dcfclk_set_mhz * 1000;
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}
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int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
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{
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int actual_min_ds_dcfclk_mhz = -1;
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if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
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return -1;
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if (!clk_mgr->smu_present)
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return requested_min_ds_dcfclk_khz;
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actual_min_ds_dcfclk_mhz = dcn35_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetMinDeepSleepDcfclk,
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khz_to_mhz_ceil(requested_min_ds_dcfclk_khz));
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smu_print("requested_min_ds_dcfclk_khz = %d, actual_min_ds_dcfclk_mhz: %d\n", requested_min_ds_dcfclk_khz, actual_min_ds_dcfclk_mhz);
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return actual_min_ds_dcfclk_mhz * 1000;
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}
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int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
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{
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int actual_dppclk_set_mhz = -1;
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if (!clk_mgr->smu_present)
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return requested_dpp_khz;
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actual_dppclk_set_mhz = dcn35_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetDppclkFreq,
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khz_to_mhz_ceil(requested_dpp_khz));
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smu_print("requested_dpp_khz = %d, actual_dppclk_set_mhz: %d\n", requested_dpp_khz, actual_dppclk_set_mhz);
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return actual_dppclk_set_mhz * 1000;
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}
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void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)
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{
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if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
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return;
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if (!clk_mgr->smu_present)
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return;
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//TODO: Work with smu team to define optimization options.
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dcn35_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetDisplayIdleOptimizations,
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idle_info);
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smu_print("VBIOSSMC_MSG_SetDisplayIdleOptimizations idle_info = %d\n", idle_info);
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}
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void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
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{
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union display_idle_optimization_u idle_info = { 0 };
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if (!clk_mgr->smu_present)
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return;
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if (enable) {
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idle_info.idle_info.df_request_disabled = 1;
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idle_info.idle_info.phy_ref_clk_off = 1;
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}
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dcn35_smu_send_msg_with_param(
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clk_mgr,
|
||||
VBIOSSMC_MSG_SetDisplayIdleOptimizations,
|
||||
idle_info.data);
|
||||
smu_print("dcn35_smu_enable_phy_refclk_pwrdwn = %d\n", enable ? 1 : 0);
|
||||
}
|
||||
|
||||
void dcn35_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
|
||||
{
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
dcn35_smu_send_msg_with_param(
|
||||
clk_mgr,
|
||||
VBIOSSMC_MSG_UpdatePmeRestore,
|
||||
0);
|
||||
}
|
||||
|
||||
void dcn35_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
|
||||
{
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
dcn35_smu_send_msg_with_param(clk_mgr,
|
||||
VBIOSSMC_MSG_SetVbiosDramAddrHigh, addr_high);
|
||||
}
|
||||
|
||||
void dcn35_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
|
||||
{
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
dcn35_smu_send_msg_with_param(clk_mgr,
|
||||
VBIOSSMC_MSG_SetVbiosDramAddrLow, addr_low);
|
||||
}
|
||||
|
||||
void dcn35_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)
|
||||
{
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
dcn35_smu_send_msg_with_param(clk_mgr,
|
||||
VBIOSSMC_MSG_TransferTableSmu2Dram, TABLE_DPMCLOCKS);
|
||||
}
|
||||
|
||||
void dcn35_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
|
||||
{
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
dcn35_smu_send_msg_with_param(clk_mgr,
|
||||
VBIOSSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS);
|
||||
}
|
||||
|
||||
void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support)
|
||||
{
|
||||
unsigned int msg_id, param;
|
||||
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
switch (support) {
|
||||
|
||||
case DCN_ZSTATE_SUPPORT_ALLOW:
|
||||
msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
|
||||
param = (1 << 10) | (1 << 9) | (1 << 8);
|
||||
break;
|
||||
|
||||
case DCN_ZSTATE_SUPPORT_DISALLOW:
|
||||
msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
|
||||
param = 0;
|
||||
break;
|
||||
|
||||
|
||||
case DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY:
|
||||
msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
|
||||
param = (1 << 10);
|
||||
break;
|
||||
|
||||
case DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY:
|
||||
msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
|
||||
param = (1 << 10) | (1 << 8);
|
||||
break;
|
||||
|
||||
case DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY:
|
||||
msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
|
||||
param = (1 << 8);
|
||||
break;
|
||||
|
||||
default: //DCN_ZSTATE_SUPPORT_UNKNOWN
|
||||
msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
|
||||
param = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
dcn35_smu_send_msg_with_param(
|
||||
clk_mgr,
|
||||
msg_id,
|
||||
param);
|
||||
smu_print("dcn35_smu_set_zstate_support msg_id = %d, param = %d\n", msg_id, param);
|
||||
}
|
||||
|
||||
int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr)
|
||||
{
|
||||
int dprefclk;
|
||||
|
||||
if (!clk_mgr->smu_present)
|
||||
return 0;
|
||||
|
||||
dprefclk = dcn35_smu_send_msg_with_param(clk_mgr,
|
||||
VBIOSSMC_MSG_GetDprefclkFreq,
|
||||
0);
|
||||
|
||||
smu_print("dcn35_smu_get_DPREF clk = %d mhz\n", dprefclk);
|
||||
return dprefclk * 1000;
|
||||
}
|
||||
|
||||
int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)
|
||||
{
|
||||
int dtbclk;
|
||||
|
||||
if (!clk_mgr->smu_present)
|
||||
return 0;
|
||||
|
||||
dtbclk = dcn35_smu_send_msg_with_param(clk_mgr,
|
||||
VBIOSSMC_MSG_GetDtbclkFreq,
|
||||
0);
|
||||
|
||||
smu_print("dcn35_smu_get_dtbclk = %d mhz\n", dtbclk);
|
||||
return dtbclk * 1000;
|
||||
}
|
||||
/* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */
|
||||
void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
|
||||
{
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
dcn35_smu_send_msg_with_param(
|
||||
clk_mgr,
|
||||
VBIOSSMC_MSG_SetDtbClk,
|
||||
enable);
|
||||
smu_print("dcn35_smu_set_dtbclk = %d \n", enable ? 1 : 0);
|
||||
}
|
||||
|
||||
void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
|
||||
{
|
||||
dcn35_smu_send_msg_with_param(
|
||||
clk_mgr,
|
||||
VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown,
|
||||
enable);
|
||||
}
|
||||
|
||||
void dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)
|
||||
{
|
||||
dcn35_smu_send_msg_with_param(
|
||||
clk_mgr,
|
||||
VBIOSSMC_MSG_DispPsrExit,
|
||||
0);
|
||||
}
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
/*
|
||||
* Copyright 2022 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef DAL_DC_35_SMU_H_
|
||||
#define DAL_DC_35_SMU_H_
|
||||
|
||||
#include "os_types.h"
|
||||
|
||||
#ifndef PMFW_DRIVER_IF_H
|
||||
#define PMFW_DRIVER_IF_H
|
||||
#define PMFW_DRIVER_IF_VERSION 4
|
||||
|
||||
typedef enum {
|
||||
DSPCLK_DCFCLK = 0,
|
||||
DSPCLK_DISPCLK,
|
||||
DSPCLK_PIXCLK,
|
||||
DSPCLK_PHYCLK,
|
||||
DSPCLK_COUNT,
|
||||
} DSPCLK_e;
|
||||
|
||||
typedef struct {
|
||||
uint16_t Freq; // in MHz
|
||||
uint16_t Vid; // min voltage in SVI3 VID
|
||||
} DisplayClockTable_t;
|
||||
|
||||
typedef struct {
|
||||
uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
|
||||
uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
|
||||
uint16_t MinMclk;
|
||||
uint16_t MaxMclk;
|
||||
|
||||
uint8_t WmSetting;
|
||||
uint8_t WmType; // Used for normal pstate change or memory retraining
|
||||
uint8_t Padding[2];
|
||||
} WatermarkRowGeneric_t;
|
||||
|
||||
#define NUM_WM_RANGES 4
|
||||
#define WM_PSTATE_CHG 0
|
||||
#define WM_RETRAINING 1
|
||||
|
||||
typedef enum {
|
||||
WM_SOCCLK = 0,
|
||||
WM_DCFCLK,
|
||||
WM_COUNT,
|
||||
} WM_CLOCK_e;
|
||||
|
||||
typedef struct {
|
||||
// Watermarks
|
||||
WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
|
||||
|
||||
uint32_t MmHubPadding[7]; // SMU internal use
|
||||
} Watermarks_t;
|
||||
|
||||
#define NUM_DCFCLK_DPM_LEVELS 8
|
||||
#define NUM_DISPCLK_DPM_LEVELS 8
|
||||
#define NUM_DPPCLK_DPM_LEVELS 8
|
||||
#define NUM_SOCCLK_DPM_LEVELS 8
|
||||
#define NUM_VCN_DPM_LEVELS 8
|
||||
#define NUM_SOC_VOLTAGE_LEVELS 8
|
||||
#define NUM_DF_PSTATE_LEVELS 4
|
||||
|
||||
typedef enum{
|
||||
WCK_RATIO_1_1 = 0, // DDR5, Wck:ck is always 1:1;
|
||||
WCK_RATIO_1_2,
|
||||
WCK_RATIO_1_4,
|
||||
WCK_RATIO_MAX
|
||||
} WCK_RATIO_e;
|
||||
|
||||
typedef struct {
|
||||
uint32_t FClk;
|
||||
uint32_t MemClk;
|
||||
uint32_t Voltage;
|
||||
uint8_t WckRatio;
|
||||
uint8_t Spare[3];
|
||||
} DfPstateTable_t;
|
||||
|
||||
//Freq in MHz
|
||||
//Voltage in milli volts with 2 fractional bits
|
||||
typedef struct {
|
||||
uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
|
||||
uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
|
||||
uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
|
||||
uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
|
||||
uint32_t VClocks[NUM_VCN_DPM_LEVELS];
|
||||
uint32_t DClocks[NUM_VCN_DPM_LEVELS];
|
||||
uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
|
||||
DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
|
||||
|
||||
uint8_t NumDcfClkLevelsEnabled;
|
||||
uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
|
||||
uint8_t NumSocClkLevelsEnabled;
|
||||
uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk
|
||||
uint8_t NumDfPstatesEnabled;
|
||||
uint8_t spare[3];
|
||||
|
||||
uint32_t MinGfxClk;
|
||||
uint32_t MaxGfxClk;
|
||||
} DpmClocks_t;
|
||||
|
||||
#define TABLE_BIOS_IF 0 // Called by BIOS
|
||||
#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
|
||||
#define TABLE_CUSTOM_DPM 2 // Called by Driver
|
||||
#define TABLE_SPARE1 3
|
||||
#define TABLE_DPMCLOCKS 4 // Called by Driver
|
||||
#define TABLE_MOMENTARY_PM 5 // Called by Tools
|
||||
#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log
|
||||
#define TABLE_SMU_METRICS 7 // Called by Driver
|
||||
#define TABLE_COUNT 8
|
||||
|
||||
#endif
|
||||
|
||||
struct dcn35_watermarks {
|
||||
// Watermarks
|
||||
WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
|
||||
|
||||
uint32_t MmHubPadding[7]; // SMU internal use
|
||||
};
|
||||
|
||||
struct dcn35_smu_dpm_clks {
|
||||
DpmClocks_t *dpm_clks;
|
||||
union large_integer mc_address;
|
||||
};
|
||||
|
||||
/* TODO: taken from vgh, may not be correct */
|
||||
struct display_idle_optimization {
|
||||
unsigned int df_request_disabled : 1;
|
||||
unsigned int phy_ref_clk_off : 1;
|
||||
unsigned int s0i2_rdy : 1;
|
||||
unsigned int reserved : 29;
|
||||
};
|
||||
|
||||
union display_idle_optimization_u {
|
||||
struct display_idle_optimization idle_info;
|
||||
uint32_t data;
|
||||
};
|
||||
|
||||
int dcn35_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
|
||||
int dcn35_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
|
||||
int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
|
||||
int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
|
||||
int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
|
||||
int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
|
||||
void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
|
||||
void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
|
||||
void dcn35_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
|
||||
void dcn35_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
|
||||
void dcn35_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
|
||||
void dcn35_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
|
||||
void dcn35_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
|
||||
|
||||
void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support);
|
||||
void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
|
||||
void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
|
||||
|
||||
void dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr);
|
||||
int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr);
|
||||
int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr);
|
||||
#endif /* DAL_DC_35_SMU_H_ */
|
||||
|
|
@ -868,6 +868,7 @@ static bool dc_construct_ctx(struct dc *dc,
|
|||
dc_ctx->dce_environment = init_params->dce_environment;
|
||||
dc_ctx->dcn_reg_offsets = init_params->dcn_reg_offsets;
|
||||
dc_ctx->nbio_reg_offsets = init_params->nbio_reg_offsets;
|
||||
dc_ctx->clk_reg_offsets = init_params->clk_reg_offsets;
|
||||
|
||||
/* Create logger */
|
||||
|
||||
|
|
@ -1367,6 +1368,7 @@ struct dc *dc_create(const struct dc_init_data *init_params)
|
|||
|
||||
dc->dcn_reg_offsets = init_params->dcn_reg_offsets;
|
||||
dc->nbio_reg_offsets = init_params->nbio_reg_offsets;
|
||||
dc->clk_reg_offsets = init_params->clk_reg_offsets;
|
||||
|
||||
/* Populate versioning information */
|
||||
dc->versions.dc_ver = DC_VER;
|
||||
|
|
|
|||
|
|
@ -1027,6 +1027,7 @@ struct dc {
|
|||
|
||||
uint32_t *dcn_reg_offsets;
|
||||
uint32_t *nbio_reg_offsets;
|
||||
uint32_t *clk_reg_offsets;
|
||||
|
||||
/* Scratch memory */
|
||||
struct {
|
||||
|
|
@ -1086,6 +1087,7 @@ struct dc_init_data {
|
|||
*/
|
||||
uint32_t *dcn_reg_offsets;
|
||||
uint32_t *nbio_reg_offsets;
|
||||
uint32_t *clk_reg_offsets;
|
||||
};
|
||||
|
||||
struct dc_callback_init {
|
||||
|
|
|
|||
|
|
@ -808,6 +808,7 @@ struct dc_context {
|
|||
struct cp_psp cp_psp;
|
||||
uint32_t *dcn_reg_offsets;
|
||||
uint32_t *nbio_reg_offsets;
|
||||
uint32_t *clk_reg_offsets;
|
||||
};
|
||||
|
||||
/* DSC DPCD capabilities */
|
||||
|
|
|
|||
|
|
@ -258,6 +258,7 @@ struct clk_mgr_funcs {
|
|||
int (*get_dtb_ref_clk_frequency)(struct clk_mgr *clk_mgr);
|
||||
|
||||
void (*set_low_power_state)(struct clk_mgr *clk_mgr);
|
||||
void (*exit_low_power_state)(struct clk_mgr *clk_mgr);
|
||||
|
||||
void (*init_clocks)(struct clk_mgr *clk_mgr);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue