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riscv: dts: starfive - Add hwrng node for JH7110 SoC 

Add hardware rng controller node for StarFive JH7110 SoC.

Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
pull/806/head
Jia Jie Ho 2023-08-08 22:15:58 +08:00 committed by Conor Dooley
parent e2c07765e1
commit 87ddf5b109
1 changed files with 10 additions and 0 deletions
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10
arch/riscv/boot/dts/starfive/jh7110.dtsi
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@ -848,6 +848,16 @@
#dma-cells = <2>;
};
rng: rng@1600c000 {
compatible = "starfive,jh7110-trng";
reg = <0x0 0x1600C000 0x0 0x4000>;
clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
<&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
clock-names = "hclk", "ahb";
resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
interrupts = <30>;
};
mmc0: mmc@16010000 {
compatible = "starfive,jh7110-mmc";
reg = <0x0 0x16010000 0x0 0x10000>;