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arm64: dts: imx8mn-tqma8mqnl: fix LDO5 power off 

Fix SD card removal caused by automatic LDO5 power off after boot

To prevent this, add vqmmc regulator for USDHC, using a GPIO-controlled
regulator that is supplied by LDO5. Since this is implemented on SoM but
used on baseboards with SD-card interface, implement the functionality
on SoM part and optionally enable it on baseboards if needed.

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
master
Markus Niebel 2025-12-16 14:39:25 +01:00 committed by Shawn Guo
parent 8b6ffe54fd
commit 8adc841d43
2 changed files with 29 additions and 6 deletions
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13
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts
View File

@ -69,6 +69,10 @@
samsung,esc-clock-frequency = <20000000>;
};
&reg_usdhc2_vqmmc {
status = "okay";
};
&sai3 {
assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
@ -216,8 +220,7 @@
<MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>,
<MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>,
<MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>,
<MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>,
<MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>;
<MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
@ -226,8 +229,7 @@
<MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>,
<MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>,
<MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>,
<MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>,
<MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>;
<MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
@ -236,8 +238,7 @@
<MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>,
<MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>,
<MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>,
<MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>,
<MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>;
<MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>;
};
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {

22
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi
View File

@ -15,6 +15,20 @@
reg = <0x00000000 0x40000000 0 0x40000000>;
};
reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
compatible = "regulator-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>;
regulator-name = "V_SD2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
states = <1800000 0x1>,
<3300000 0x0>;
vin-supply = <&ldo5_reg>;
status = "disabled";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -218,6 +232,10 @@
vddio-supply = <&ldo3_reg>;
};
&usdhc2 {
vqmmc-supply = <&reg_usdhc2_vqmmc>;
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
@ -272,6 +290,10 @@
fsl,pins = <MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>;
};
pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp {
fsl,pins = <MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc0>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>,
<MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,