openrisc: Add jump label support
Supported a complete jump_label implementation based on the ARM64 and RV64 version and add the CONFIG_JUMP_LABEL=y to the defconfig. Testing was conducted using a dedicated test module jump-label-test, provided in the link below. For detailed steps, please refer to the README also at the provided link. Link: https://github.com/ChenMiaoi/GSoC-2025-Final-Report/tree/main/tests/jump-label-test Test Environment: - Hardware: QEMU emulated OR1K - Kernel Version: 6.17.0-rc3-dirty - Configs: CONFIG_MODULES=y,CONFIG_MODULE_UNLOAD=y - Toolchain: or1k-none-linux-musl-gcc 15.1.0 Test Results: $ insmod jump_label_test.ko [ 32.590000] Jump label performance test module loaded [ 35.250000] Normal branch time: 1241327150 ns (124 ns per iteration) [ 35.250000] Jump label (false) time: 706422700 ns (70 ns per iteration) [ 35.250000] Jump label (true) time: 708913450 ns (70 ns per iteration) $ rmmod jump_label_test.ko [ 72.210000] Jump label test module unloaded The results show approximately 43% improvement in branch performance when using jump labels compared to traditional branches. Link: https://lore.kernel.org/openrisc/aLsZ9S3X0OpKy1RM@antec/T/#u Signed-off-by: chenmiao <chenmiao.ku@gmail.com> Signed-off-by: Stafford Horne <shorne@gmail.com>pull/1354/merge
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@ -17,7 +17,7 @@
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| microblaze: | TODO |
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| mips: | ok |
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| nios2: | TODO |
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| openrisc: | TODO |
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| openrisc: | ok |
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| parisc: | ok |
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| powerpc: | ok |
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| riscv: | ok |
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@ -24,6 +24,8 @@ config OPENRISC
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select GENERIC_PCI_IOMAP
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select GENERIC_IOREMAP
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select GENERIC_CPU_DEVICES
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select HAVE_ARCH_JUMP_LABEL
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select HAVE_ARCH_JUMP_LABEL_RELATIVE
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select HAVE_PCI
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select HAVE_UID16
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select HAVE_PAGE_SIZE_8KB
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@ -10,6 +10,7 @@ CONFIG_EXPERT=y
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# CONFIG_KALLSYMS is not set
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CONFIG_BUILTIN_DTB_NAME="or1ksim"
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CONFIG_HZ_100=y
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CONFIG_JUMP_LABEL=y
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CONFIG_MODULES=y
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# CONFIG_BLOCK is not set
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CONFIG_SLUB_TINY=y
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@ -12,6 +12,7 @@ CONFIG_NR_CPUS=8
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CONFIG_SMP=y
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CONFIG_HZ_100=y
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# CONFIG_OPENRISC_NO_SPR_SR_DSX is not set
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CONFIG_JUMP_LABEL=y
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# CONFIG_COMPAT_BRK is not set
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CONFIG_NET=y
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CONFIG_PACKET=y
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@ -9,4 +9,7 @@
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/* or1k instructions are always 32 bits. */
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#define OPENRISC_INSN_SIZE 4
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/* or1k nop instruction code */
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#define OPENRISC_INSN_NOP 0x15000000U
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#endif /* __ASM_OPENRISC_INSN_DEF_H */
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@ -0,0 +1,72 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2025 Chen Miao
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*
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* Based on arch/arm/include/asm/jump_label.h
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*/
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#ifndef __ASM_OPENRISC_JUMP_LABEL_H
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#define __ASM_OPENRISC_JUMP_LABEL_H
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#ifndef __ASSEMBLER__
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#include <linux/types.h>
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#include <asm/insn-def.h>
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#define HAVE_JUMP_LABEL_BATCH
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#define JUMP_LABEL_NOP_SIZE OPENRISC_INSN_SIZE
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/**
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* JUMP_TABLE_ENTRY - Create a jump table entry
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* @key: Jump key identifier (typically a symbol address)
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* @label: Target label address
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*
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* This macro creates a jump table entry in the dedicated kernel section (__jump_table).
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* Each entry contains the following information:
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* Offset from current instruction to jump instruction (1b - .)
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* Offset from current instruction to target label (label - .)
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* Offset from current instruction to key identifier (key - .)
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*/
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#define JUMP_TABLE_ENTRY(key, label) \
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".pushsection __jump_table, \"aw\" \n\t" \
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".align 4 \n\t" \
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".long 1b - ., " label " - . \n\t" \
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".long " key " - . \n\t" \
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".popsection \n\t"
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#define ARCH_STATIC_BRANCH_ASM(key, label) \
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".align 4 \n\t" \
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"1: l.nop \n\t" \
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" l.nop \n\t" \
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JUMP_TABLE_ENTRY(key, label)
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static __always_inline bool arch_static_branch(struct static_key *const key,
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const bool branch)
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{
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asm goto (ARCH_STATIC_BRANCH_ASM("%0", "%l[l_yes]")
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::"i"(&((char *)key)[branch])::l_yes);
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return false;
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l_yes:
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return true;
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}
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#define ARCH_STATIC_BRANCH_JUMP_ASM(key, label) \
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".align 4 \n\t" \
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"1: l.j " label " \n\t" \
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" l.nop \n\t" \
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JUMP_TABLE_ENTRY(key, label)
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static __always_inline bool
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arch_static_branch_jump(struct static_key *const key, const bool branch)
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{
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asm goto (ARCH_STATIC_BRANCH_JUMP_ASM("%0", "%l[l_yes]")
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::"i"(&((char *)key)[branch])::l_yes);
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return false;
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l_yes:
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return true;
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}
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#endif /* __ASSEMBLER__ */
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#endif /* __ASM_OPENRISC_JUMP_LABEL_H */
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@ -9,6 +9,7 @@ obj-y := head.o setup.o or32_ksyms.o process.o dma.o \
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traps.o time.o irq.o entry.o ptrace.o signal.o \
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sys_call_table.o unwinder.o cacheinfo.o
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obj-$(CONFIG_JUMP_LABEL) += jump_label.o
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obj-$(CONFIG_SMP) += smp.o sync-timer.o
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obj-$(CONFIG_STACKTRACE) += stacktrace.o
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obj-$(CONFIG_MODULES) += module.o
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@ -0,0 +1,51 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2025 Chen Miao
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*
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* Based on arch/arm/kernel/jump_label.c
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*/
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#include <linux/jump_label.h>
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#include <linux/kernel.h>
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#include <linux/memory.h>
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#include <asm/bug.h>
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#include <asm/cacheflush.h>
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#include <asm/text-patching.h>
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bool arch_jump_label_transform_queue(struct jump_entry *entry,
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enum jump_label_type type)
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{
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void *addr = (void *)jump_entry_code(entry);
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u32 insn;
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if (type == JUMP_LABEL_JMP) {
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long offset;
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offset = jump_entry_target(entry) - jump_entry_code(entry);
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/*
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* The actual maximum range of the l.j instruction's offset is -134,217,728
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* ~ 134,217,724 (sign 26-bit imm).
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* For the original jump range, we need to right-shift N by 2 to obtain the
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* instruction's offset.
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*/
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WARN_ON_ONCE(offset < -134217728 || offset > 134217724);
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/* 26bit imm mask */
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offset = (offset >> 2) & 0x03ffffff;
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insn = offset;
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} else {
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insn = OPENRISC_INSN_NOP;
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}
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if (early_boot_irqs_disabled)
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copy_to_kernel_nofault(addr, &insn, sizeof(insn));
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else
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patch_insn_write(addr, insn);
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return true;
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}
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void arch_jump_label_transform_apply(void)
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{
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kick_all_cpus_sync();
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}
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@ -249,6 +249,8 @@ void __init setup_arch(char **cmdline_p)
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initrd_below_start_ok = 1;
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}
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#endif
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/* perform jump_table sorting before paging_init locks down read only memory */
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jump_label_init();
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/* paging_init() sets up the MMU and marks all pages as reserved */
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paging_init();
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