Merge branch 'pci/controller/dwc-eswin'
- Add DT binding and driver for ESWIN PCIe Root Complex (Senchuan Zhang) * pci/controller/dwc-eswin: PCI: eswin: Add ESWIN PCIe Root Complex driver dt-bindings: PCI: eswin: Add ESWIN PCIe Root Complex # Conflicts: # drivers/pci/controller/dwc/Kconfig # drivers/pci/controller/dwc/Makefilemaster
Bjorn Helgaas
commit
927e9d9d4e
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|
@ -0,0 +1,166 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/eswin,pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ESWIN PCIe Root Complex
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maintainers:
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- Yu Ning <ningyu@eswincomputing.com>
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- Senchuan Zhang <zhangsenchuan@eswincomputing.com>
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- Yanghui Ou <ouyanghui@eswincomputing.com>
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description:
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ESWIN SoCs PCIe Root Complex is based on the Synopsys DesignWare PCIe IP.
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properties:
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compatible:
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const: eswin,eic7700-pcie
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reg:
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maxItems: 3
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reg-names:
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items:
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- const: dbi
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- const: config
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- const: elbi
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ranges:
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maxItems: 3
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'#interrupt-cells':
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const: 1
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interrupt-names:
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items:
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- const: msi
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- const: inta
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- const: intb
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- const: intc
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- const: intd
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interrupt-map:
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maxItems: 4
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interrupt-map-mask:
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items:
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- const: 0
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- const: 0
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- const: 0
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- const: 7
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clocks:
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maxItems: 4
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clock-names:
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items:
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- const: mstr
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- const: dbi
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- const: phy_reg
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- const: aux
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: dbi
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- const: pwr
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patternProperties:
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"^pcie@":
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type: object
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$ref: /schemas/pci/pci-pci-bridge.yaml#
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properties:
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reg:
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maxItems: 1
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num-lanes:
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maximum: 4
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: perst
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required:
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- reg
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- ranges
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- num-lanes
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- resets
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- reset-names
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- ranges
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- interrupts
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- interrupt-names
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- interrupt-map-mask
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- interrupt-map
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- '#interrupt-cells'
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- clocks
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- clock-names
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- resets
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- reset-names
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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unevaluatedProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@54000000 {
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compatible = "eswin,eic7700-pcie";
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reg = <0x0 0x54000000 0x0 0x4000000>,
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<0x0 0x40000000 0x0 0x800000>,
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<0x0 0x50000000 0x0 0x100000>;
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reg-names = "dbi", "config", "elbi";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x01000000 0x0 0x40800000 0x0 0x40800000 0x0 0x800000>,
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<0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0xf000000>,
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<0x43000000 0x80 0x00000000 0x80 0x00000000 0x2 0x00000000>;
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bus-range = <0x00 0xff>;
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clocks = <&clock 144>,
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<&clock 145>,
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<&clock 146>,
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<&clock 147>;
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clock-names = "mstr", "dbi", "phy_reg", "aux";
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resets = <&reset 97>,
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<&reset 98>;
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reset-names = "dbi", "pwr";
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interrupts = <220>, <179>, <180>, <181>, <182>, <183>, <184>, <185>, <186>;
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interrupt-names = "msi", "inta", "intb", "intc", "intd";
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interrupt-parent = <&plic>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &plic 179>,
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<0x0 0x0 0x0 0x2 &plic 180>,
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<0x0 0x0 0x0 0x3 &plic 181>,
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<0x0 0x0 0x0 0x4 &plic 182>;
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device_type = "pci";
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pcie@0 {
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reg = <0x0 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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device_type = "pci";
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num-lanes = <4>;
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resets = <&reset 99>;
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reset-names = "perst";
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};
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};
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};
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@ -20501,6 +20501,13 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Odd Fixes
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F: drivers/pci/controller/pci-thunder-*
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PCIE DRIVER FOR ESWIN
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M: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
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L: linux-pci@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/eswin,pcie.yaml
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F: drivers/pci/controller/dwc/pcie-eswin.c
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PCIE DRIVER FOR HISILICON
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M: Zhou Wang <wangzhou1@hisilicon.com>
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L: linux-pci@vger.kernel.org
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@ -95,6 +95,16 @@ config PCIE_ARTPEC6_EP
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Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
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endpoint mode. This uses the DesignWare core.
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config PCIE_ESWIN
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tristate "ESWIN PCIe controller"
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depends on ARCH_ESWIN || COMPILE_TEST
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depends on PCI_MSI
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select PCIE_DW_HOST
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help
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Say Y here if you want PCIe controller support for the ESWIN SoCs.
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The PCIe controller in ESWIN SoCs is based on DesignWare hardware, and
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works only in host mode.
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config PCI_IMX6
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bool
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@ -6,6 +6,7 @@ obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
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obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
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obj-$(CONFIG_PCIE_AMD_MDB) += pcie-amd-mdb.o
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obj-$(CONFIG_PCIE_ANDES_QILAI) += pcie-andes-qilai.o
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obj-$(CONFIG_PCIE_ESWIN) += pcie-eswin.o
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obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
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obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
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obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o
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@ -0,0 +1,408 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* ESWIN PCIe Root Complex driver
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*
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* Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd.
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*
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* Authors: Yu Ning <ningyu@eswincomputing.com>
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* Senchuan Zhang <zhangsenchuan@eswincomputing.com>
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* Yanghui Ou <ouyanghui@eswincomputing.com>
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*/
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/resource.h>
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#include <linux/reset.h>
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#include <linux/types.h>
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#include "pcie-designware.h"
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/* ELBI registers */
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#define PCIEELBI_CTRL0_OFFSET 0x0
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#define PCIEELBI_STATUS0_OFFSET 0x100
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/* LTSSM register fields */
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#define PCIEELBI_APP_LTSSM_ENABLE BIT(5)
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/* APP_HOLD_PHY_RST register fields */
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#define PCIEELBI_APP_HOLD_PHY_RST BIT(6)
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/* PM_SEL_AUX_CLK register fields */
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#define PCIEELBI_PM_SEL_AUX_CLK BIT(16)
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/* DEV_TYPE register fields */
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#define PCIEELBI_CTRL0_DEV_TYPE GENMASK(3, 0)
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/* Vendor and device ID value */
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#define PCI_VENDOR_ID_ESWIN 0x1fe1
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#define PCI_DEVICE_ID_ESWIN_EIC7700 0x2030
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#define ESWIN_NUM_RSTS ARRAY_SIZE(eswin_pcie_rsts)
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static const char * const eswin_pcie_rsts[] = {
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"pwr",
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"dbi",
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};
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struct eswin_pcie_data {
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bool skip_l23;
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};
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struct eswin_pcie_port {
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struct list_head list;
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struct reset_control *perst;
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int num_lanes;
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};
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struct eswin_pcie {
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struct dw_pcie pci;
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struct clk_bulk_data *clks;
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struct reset_control_bulk_data resets[ESWIN_NUM_RSTS];
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struct list_head ports;
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const struct eswin_pcie_data *data;
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int num_clks;
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};
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#define to_eswin_pcie(x) dev_get_drvdata((x)->dev)
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static int eswin_pcie_start_link(struct dw_pcie *pci)
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{
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u32 val;
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/* Enable LTSSM */
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val = readl_relaxed(pci->elbi_base + PCIEELBI_CTRL0_OFFSET);
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val |= PCIEELBI_APP_LTSSM_ENABLE;
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writel_relaxed(val, pci->elbi_base + PCIEELBI_CTRL0_OFFSET);
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return 0;
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}
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static bool eswin_pcie_link_up(struct dw_pcie *pci)
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{
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u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
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u16 val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
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return val & PCI_EXP_LNKSTA_DLLLA;
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}
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static int eswin_pcie_perst_reset(struct eswin_pcie_port *port,
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struct eswin_pcie *pcie)
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{
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int ret;
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ret = reset_control_assert(port->perst);
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if (ret) {
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dev_err(pcie->pci.dev, "Failed to assert PERST#\n");
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return ret;
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}
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/* Ensure that PERST# has been asserted for at least 100 ms */
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msleep(PCIE_T_PVPERL_MS);
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ret = reset_control_deassert(port->perst);
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if (ret) {
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dev_err(pcie->pci.dev, "Failed to deassert PERST#\n");
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||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
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}
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|
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static void eswin_pcie_assert(struct eswin_pcie *pcie)
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||||
{
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struct eswin_pcie_port *port;
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|
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list_for_each_entry(port, &pcie->ports, list)
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reset_control_assert(port->perst);
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reset_control_bulk_assert(ESWIN_NUM_RSTS, pcie->resets);
|
||||
}
|
||||
|
||||
static int eswin_pcie_parse_port(struct eswin_pcie *pcie,
|
||||
struct device_node *node)
|
||||
{
|
||||
struct device *dev = pcie->pci.dev;
|
||||
struct eswin_pcie_port *port;
|
||||
|
||||
port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
|
||||
if (!port)
|
||||
return -ENOMEM;
|
||||
|
||||
port->perst = of_reset_control_get_exclusive(node, "perst");
|
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if (IS_ERR(port->perst)) {
|
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dev_err(dev, "Failed to get PERST# reset\n");
|
||||
return PTR_ERR(port->perst);
|
||||
}
|
||||
|
||||
/*
|
||||
* TODO: Since the Root Port node is separated out by pcie devicetree,
|
||||
* the DWC core initialization code can't parse the num-lanes attribute
|
||||
* in the Root Port. Before entering the DWC core initialization code,
|
||||
* the platform driver code parses the Root Port node. The ESWIN only
|
||||
* supports one Root Port node, and the num-lanes attribute is suitable
|
||||
* for the case of one Root Port.
|
||||
*/
|
||||
if (!of_property_read_u32(node, "num-lanes", &port->num_lanes))
|
||||
pcie->pci.num_lanes = port->num_lanes;
|
||||
|
||||
INIT_LIST_HEAD(&port->list);
|
||||
list_add_tail(&port->list, &pcie->ports);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int eswin_pcie_parse_ports(struct eswin_pcie *pcie)
|
||||
{
|
||||
struct eswin_pcie_port *port, *tmp;
|
||||
struct device *dev = pcie->pci.dev;
|
||||
int ret;
|
||||
|
||||
for_each_available_child_of_node_scoped(dev->of_node, of_port) {
|
||||
ret = eswin_pcie_parse_port(pcie, of_port);
|
||||
if (ret)
|
||||
goto err_port;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_port:
|
||||
list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
|
||||
reset_control_put(port->perst);
|
||||
list_del(&port->list);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int eswin_pcie_host_init(struct dw_pcie_rp *pp)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
||||
struct eswin_pcie *pcie = to_eswin_pcie(pci);
|
||||
struct eswin_pcie_port *port, *tmp;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* The PWR and DBI reset signals are respectively used to reset the
|
||||
* PCIe controller and the DBI register.
|
||||
*
|
||||
* The PERST# signal is a reset signal that simultaneously controls the
|
||||
* PCIe controller, PHY, and Endpoint. Before configuring the PHY, the
|
||||
* PERST# signal must first be deasserted.
|
||||
*
|
||||
* The external reference clock is supplied simultaneously to the PHY
|
||||
* and EP. When the PHY is configurable, the entire chip already has
|
||||
* stable power and reference clock. The PHY will be ready within 20ms
|
||||
* after writing app_hold_phy_rst register bit of ELBI register space.
|
||||
*/
|
||||
ret = reset_control_bulk_deassert(ESWIN_NUM_RSTS, pcie->resets);
|
||||
if (ret) {
|
||||
dev_err(pcie->pci.dev, "Failed to deassert resets\n");
|
||||
goto err_deassert;
|
||||
}
|
||||
|
||||
/* Configure Root Port type */
|
||||
val = readl_relaxed(pci->elbi_base + PCIEELBI_CTRL0_OFFSET);
|
||||
val &= ~PCIEELBI_CTRL0_DEV_TYPE;
|
||||
val |= FIELD_PREP(PCIEELBI_CTRL0_DEV_TYPE, PCI_EXP_TYPE_ROOT_PORT);
|
||||
writel_relaxed(val, pci->elbi_base + PCIEELBI_CTRL0_OFFSET);
|
||||
|
||||
list_for_each_entry(port, &pcie->ports, list) {
|
||||
ret = eswin_pcie_perst_reset(port, pcie);
|
||||
if (ret)
|
||||
goto err_perst;
|
||||
}
|
||||
|
||||
/* Configure app_hold_phy_rst */
|
||||
val = readl_relaxed(pci->elbi_base + PCIEELBI_CTRL0_OFFSET);
|
||||
val &= ~PCIEELBI_APP_HOLD_PHY_RST;
|
||||
writel_relaxed(val, pci->elbi_base + PCIEELBI_CTRL0_OFFSET);
|
||||
|
||||
/* The maximum waiting time for the clock switch lock is 20ms */
|
||||
ret = readl_poll_timeout(pci->elbi_base + PCIEELBI_STATUS0_OFFSET, val,
|
||||
!(val & PCIEELBI_PM_SEL_AUX_CLK), 1000,
|
||||
20000);
|
||||
if (ret) {
|
||||
dev_err(pci->dev, "Timeout waiting for PM_SEL_AUX_CLK ready\n");
|
||||
goto err_phy_init;
|
||||
}
|
||||
|
||||
/*
|
||||
* Configure ESWIN VID:DID for Root Port as the default values are
|
||||
* invalid.
|
||||
*/
|
||||
dw_pcie_dbi_ro_wr_en(pci);
|
||||
dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, PCI_VENDOR_ID_ESWIN);
|
||||
dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, PCI_DEVICE_ID_ESWIN_EIC7700);
|
||||
dw_pcie_dbi_ro_wr_dis(pci);
|
||||
|
||||
return 0;
|
||||
|
||||
err_phy_init:
|
||||
list_for_each_entry(port, &pcie->ports, list)
|
||||
reset_control_assert(port->perst);
|
||||
err_perst:
|
||||
reset_control_bulk_assert(ESWIN_NUM_RSTS, pcie->resets);
|
||||
err_deassert:
|
||||
clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
|
||||
list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
|
||||
reset_control_put(port->perst);
|
||||
list_del(&port->list);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void eswin_pcie_host_deinit(struct dw_pcie_rp *pp)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
||||
struct eswin_pcie *pcie = to_eswin_pcie(pci);
|
||||
|
||||
eswin_pcie_assert(pcie);
|
||||
clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
|
||||
}
|
||||
|
||||
static void eswin_pcie_pme_turn_off(struct dw_pcie_rp *pp)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
||||
struct eswin_pcie *pcie = to_eswin_pcie(pci);
|
||||
|
||||
/*
|
||||
* The ESWIN EIC7700 SoC lacks hardware support for the L2/L3 low-power
|
||||
* link states. It cannot enter the L2/L3 Ready state through the
|
||||
* PME_Turn_Off/PME_To_Ack handshake protocol. To avoid this problem,
|
||||
* the skip_l23_ready has been set.
|
||||
*/
|
||||
pp->skip_l23_ready = pcie->data->skip_l23;
|
||||
}
|
||||
|
||||
static const struct dw_pcie_host_ops eswin_pcie_host_ops = {
|
||||
.init = eswin_pcie_host_init,
|
||||
.deinit = eswin_pcie_host_deinit,
|
||||
.pme_turn_off = eswin_pcie_pme_turn_off,
|
||||
};
|
||||
|
||||
static const struct dw_pcie_ops dw_pcie_ops = {
|
||||
.start_link = eswin_pcie_start_link,
|
||||
.link_up = eswin_pcie_link_up,
|
||||
};
|
||||
|
||||
static int eswin_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct eswin_pcie_data *data;
|
||||
struct eswin_pcie_port *port, *tmp;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct eswin_pcie *pcie;
|
||||
struct dw_pcie *pci;
|
||||
int ret, i;
|
||||
|
||||
data = of_device_get_match_data(dev);
|
||||
if (!data)
|
||||
return dev_err_probe(dev, -ENODATA, "No platform data\n");
|
||||
|
||||
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
|
||||
if (!pcie)
|
||||
return -ENOMEM;
|
||||
|
||||
INIT_LIST_HEAD(&pcie->ports);
|
||||
|
||||
pci = &pcie->pci;
|
||||
pci->dev = dev;
|
||||
pci->ops = &dw_pcie_ops;
|
||||
pci->pp.ops = &eswin_pcie_host_ops;
|
||||
pcie->data = data;
|
||||
|
||||
pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks);
|
||||
if (pcie->num_clks < 0)
|
||||
return dev_err_probe(dev, pcie->num_clks,
|
||||
"Failed to get pcie clocks\n");
|
||||
|
||||
for (i = 0; i < ESWIN_NUM_RSTS; i++)
|
||||
pcie->resets[i].id = eswin_pcie_rsts[i];
|
||||
|
||||
ret = devm_reset_control_bulk_get_exclusive(dev, ESWIN_NUM_RSTS,
|
||||
pcie->resets);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "Failed to get resets\n");
|
||||
|
||||
ret = eswin_pcie_parse_ports(pcie);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "Failed to parse Root Port\n");
|
||||
|
||||
platform_set_drvdata(pdev, pcie);
|
||||
|
||||
pm_runtime_no_callbacks(dev);
|
||||
devm_pm_runtime_enable(dev);
|
||||
ret = pm_runtime_get_sync(dev);
|
||||
if (ret < 0)
|
||||
goto err_pm_runtime_put;
|
||||
|
||||
ret = dw_pcie_host_init(&pci->pp);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to init host\n");
|
||||
goto err_init;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_pm_runtime_put:
|
||||
list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
|
||||
reset_control_put(port->perst);
|
||||
list_del(&port->list);
|
||||
}
|
||||
err_init:
|
||||
pm_runtime_put(dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int eswin_pcie_suspend_noirq(struct device *dev)
|
||||
{
|
||||
struct eswin_pcie *pcie = dev_get_drvdata(dev);
|
||||
|
||||
return dw_pcie_suspend_noirq(&pcie->pci);
|
||||
}
|
||||
|
||||
static int eswin_pcie_resume_noirq(struct device *dev)
|
||||
{
|
||||
struct eswin_pcie *pcie = dev_get_drvdata(dev);
|
||||
|
||||
return dw_pcie_resume_noirq(&pcie->pci);
|
||||
}
|
||||
|
||||
static DEFINE_NOIRQ_DEV_PM_OPS(eswin_pcie_pm, eswin_pcie_suspend_noirq,
|
||||
eswin_pcie_resume_noirq);
|
||||
|
||||
static const struct eswin_pcie_data eswin_eic7700_data = {
|
||||
.skip_l23 = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id eswin_pcie_of_match[] = {
|
||||
{ .compatible = "eswin,eic7700-pcie", .data = &eswin_eic7700_data },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver eswin_pcie_driver = {
|
||||
.probe = eswin_pcie_probe,
|
||||
.driver = {
|
||||
.name = "eswin-pcie",
|
||||
.of_match_table = eswin_pcie_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
.pm = &eswin_pcie_pm,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(eswin_pcie_driver);
|
||||
|
||||
MODULE_DESCRIPTION("ESWIN PCIe Root Complex driver");
|
||||
MODULE_AUTHOR("Yu Ning <ningyu@eswincomputing.com>");
|
||||
MODULE_AUTHOR("Senchuan Zhang <zhangsenchuan@eswincomputing.com>");
|
||||
MODULE_AUTHOR("Yanghui Ou <ouyanghui@eswincomputing.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue