dt-bindings: display/msm: expand to support MST
On a vast majority of Qualcomm chipsets DisplayPort controller can support several MST streams (up to 4x). To support MST these chipsets use up to 4 stream pixel clocks for the DisplayPort controller and several extra register regions. Expand corresponding region and clock bindings for these platforms and fix example schema files to follow updated bindings. Note: On chipsets that support MST, the number of streams supported can vary between controllers. For example, SA8775P supports 4 MST streams on mdss_dp0 but only 2 streams on mdss_dp1. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/672585/ Link: https://lore.kernel.org/r/20250903-dp_mst_bindings-v8-7-7526f0311eaa@oss.qualcomm.compull/1354/merge
Abhinav Kumar
Dmitry Baryshkov
parent
0253f5ef8d
commit
9be5c47908
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@ -66,25 +66,37 @@ properties:
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- description: link register block
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- description: p0 register block
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- description: p1 register block
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- description: p2 register block
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- description: p3 register block
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- description: mst2link register block
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- description: mst3link register block
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interrupts:
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maxItems: 1
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clocks:
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minItems: 5
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items:
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- description: AHB clock to enable register access
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- description: Display Port AUX clock
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- description: Display Port Link clock
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- description: Link interface clock between DP and PHY
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- description: Display Port Pixel clock
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- description: Display Port stream 0 Pixel clock
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- description: Display Port stream 1 Pixel clock
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- description: Display Port stream 2 Pixel clock
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- description: Display Port stream 3 Pixel clock
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clock-names:
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minItems: 5
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items:
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- const: core_iface
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- const: core_aux
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- const: ctrl_link
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- const: ctrl_link_iface
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- const: stream_pixel
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- const: stream_1_pixel
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- const: stream_2_pixel
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- const: stream_3_pixel
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phys:
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maxItems: 1
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@ -166,7 +178,6 @@ required:
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allOf:
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# AUX BUS does not exist on DP controllers
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# Audio output also is present only on DP output
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# p1 regions is present on DP, but not on eDP
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- if:
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properties:
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compatible:
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@ -195,11 +206,95 @@ allOf:
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else:
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properties:
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aux-bus: false
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reg:
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minItems: 5
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required:
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- "#sound-dai-cells"
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- if:
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properties:
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compatible:
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contains:
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enum:
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# these platforms support SST only
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- qcom,sc7180-dp
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- qcom,sc7280-dp
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- qcom,sc7280-edp
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- qcom,sc8180x-edp
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- qcom,sc8280xp-edp
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then:
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properties:
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reg:
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minItems: 5
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maxItems: 5
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clocks:
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minItems: 5
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maxItems: 5
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clocks-names:
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minItems: 5
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maxItems: 5
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- if:
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properties:
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compatible:
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contains:
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enum:
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# these platforms support 2 streams MST on some interfaces,
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# others are SST only
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- qcom,sc8280xp-dp
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- qcom,x1e80100-dp
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then:
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properties:
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reg:
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minItems: 5
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maxItems: 5
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clocks:
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minItems: 5
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maxItems: 6
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clocks-names:
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minItems: 5
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maxItems: 6
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- if:
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properties:
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compatible:
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contains:
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# 2 streams MST
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enum:
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- qcom,sc8180x-dp
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- qcom,sdm845-dp
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- qcom,sm8350-dp
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- qcom,sm8650-dp
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then:
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properties:
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reg:
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minItems: 5
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maxItems: 5
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clocks:
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minItems: 6
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maxItems: 6
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clocks-names:
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minItems: 6
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maxItems: 6
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- if:
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properties:
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compatible:
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contains:
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enum:
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# these platforms support 4 stream MST on first DP,
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# 2 streams MST on the second one.
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- qcom,sa8775p-dp
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then:
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properties:
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reg:
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minItems: 9
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maxItems: 9
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clocks:
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minItems: 6
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maxItems: 8
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clocks-names:
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minItems: 6
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maxItems: 8
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additionalProperties: false
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examples:
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@ -375,7 +375,11 @@ examples:
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<0xaf54200 0x0c0>,
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<0xaf55000 0x770>,
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<0xaf56000 0x09c>,
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<0xaf57000 0x09c>;
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<0xaf57000 0x09c>,
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<0xaf58000 0x09c>,
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<0xaf59000 0x09c>,
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<0xaf5a000 0x23c>,
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<0xaf5b000 0x23c>;
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interrupt-parent = <&mdss0>;
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interrupts = <12>;
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@ -384,16 +388,28 @@ examples:
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<&dispcc_dptx0_aux_clk>,
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<&dispcc_dptx0_link_clk>,
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<&dispcc_dptx0_link_intf_clk>,
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<&dispcc_dptx0_pixel0_clk>;
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<&dispcc_dptx0_pixel0_clk>,
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<&dispcc_dptx0_pixel1_clk>,
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<&dispcc_dptx0_pixel2_clk>,
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<&dispcc_dptx0_pixel3_clk>;
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clock-names = "core_iface",
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"core_aux",
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"ctrl_link",
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"ctrl_link_iface",
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"stream_pixel";
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"stream_pixel",
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"stream_1_pixel",
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"stream_2_pixel",
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"stream_3_pixel";
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assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
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<&dispcc_mdss_dptx0_pixel0_clk_src>;
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assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
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<&dispcc_mdss_dptx0_pixel0_clk_src>,
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<&dispcc_mdss_dptx0_pixel1_clk_src>,
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<&dispcc_mdss_dptx0_pixel2_clk_src>,
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<&dispcc_mdss_dptx0_pixel3_clk_src>;
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assigned-clock-parents = <&mdss0_dp0_phy 0>,
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<&mdss0_dp0_phy 1>,
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<&mdss0_dp0_phy 1>,
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<&mdss0_dp0_phy 1>;
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phys = <&mdss0_dp0_phy>;
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phy-names = "dp";
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@ -207,16 +207,20 @@ examples:
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<&dispcc_disp_cc_mdss_dptx0_aux_clk>,
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<&dispcc_disp_cc_mdss_dptx0_link_clk>,
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<&dispcc_disp_cc_mdss_dptx0_link_intf_clk>,
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<&dispcc_disp_cc_mdss_dptx0_pixel0_clk>;
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<&dispcc_disp_cc_mdss_dptx0_pixel0_clk>,
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<&dispcc_disp_cc_mdss_dptx0_pixel1_clk>;
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clock-names = "core_iface",
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"core_aux",
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"ctrl_link",
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"ctrl_link_iface",
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"stream_pixel";
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"stream_pixel",
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"stream_1_pixel";
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assigned-clocks = <&dispcc_disp_cc_mdss_dptx0_link_clk_src>,
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<&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>;
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<&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>,
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<&dispcc_disp_cc_mdss_dptx0_pixel1_clk_src>;
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assigned-clock-parents = <&usb_dp_qmpphy_QMP_USB43DP_DP_LINK_CLK>,
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<&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DIV_CLK>,
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<&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DIV_CLK>;
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phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
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@ -281,7 +281,8 @@ examples:
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reg = <0xaea0000 0x200>,
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<0xaea0200 0x200>,
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<0xaea0400 0xc00>,
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<0xaea1000 0x400>;
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<0xaea1000 0x400>,
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<0xaea1400 0x400>;
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interrupt-parent = <&mdss>;
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interrupts = <14>;
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@ -394,16 +394,20 @@ examples:
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<&dispcc_mdss_dp_aux_clk>,
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<&dispcc_mdss_dp_link_clk>,
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<&dispcc_mdss_dp_link_intf_clk>,
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<&dispcc_mdss_dp_pixel_clk>;
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<&dispcc_mdss_dp_pixel_clk>,
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<&dispcc_mdss_dp_pixel1_clk>;
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clock-names = "core_iface",
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"core_aux",
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"ctrl_link",
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"ctrl_link_iface",
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"stream_pixel";
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"stream_pixel",
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"stream_1_pixel";
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assigned-clocks = <&dispcc_mdss_dp_link_clk_src>,
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<&dispcc_mdss_dp_pixel_clk_src>;
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<&dispcc_mdss_dp_pixel_clk_src>,
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<&dispcc_mdss_dp_pixel1_clk_src>;
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assigned-clock-parents = <&dp_phy 0>,
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<&dp_phy 1>,
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<&dp_phy 1>;
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operating-points-v2 = <&dp_opp_table>;
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@ -401,16 +401,20 @@ examples:
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<&disp_cc_mdss_dptx0_aux_clk>,
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<&disp_cc_mdss_dptx0_link_clk>,
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<&disp_cc_mdss_dptx0_link_intf_clk>,
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<&disp_cc_mdss_dptx0_pixel0_clk>;
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<&disp_cc_mdss_dptx0_pixel0_clk>,
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<&disp_cc_mdss_dptx0_pixel1_clk>;
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clock-names = "core_iface",
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"core_aux",
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"ctrl_link",
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"ctrl_link_iface",
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"stream_pixel";
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"stream_pixel",
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"stream_1_pixel";
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assigned-clocks = <&disp_cc_mdss_dptx0_link_clk_src>,
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<&disp_cc_mdss_dptx0_pixel0_clk_src>;
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<&disp_cc_mdss_dptx0_pixel0_clk_src>,
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<&disp_cc_mdss_dptx0_pixel1_clk_src>;
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assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
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<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
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<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
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operating-points-v2 = <&dp_opp_table>;
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@ -183,15 +183,19 @@ examples:
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<&dispcc_dptx0_aux_clk>,
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<&dispcc_dptx0_link_clk>,
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<&dispcc_dptx0_link_intf_clk>,
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<&dispcc_dptx0_pixel0_clk>;
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<&dispcc_dptx0_pixel0_clk>,
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<&dispcc_dptx0_pixel1_clk>;
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clock-names = "core_iface", "core_aux",
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"ctrl_link",
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"ctrl_link_iface",
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"stream_pixel";
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"stream_pixel",
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"stream_1_pixel";
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assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
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<&dispcc_mdss_dptx0_pixel0_clk_src>;
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<&dispcc_mdss_dptx0_pixel0_clk_src>,
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<&dispcc_mdss_dptx0_pixel1_clk_src>;
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assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
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<&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
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<&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
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operating-points-v2 = <&mdss_dp0_opp_table>;
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