From 9a205e33d0dc81121d1a2417b33b55682b81b84d Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Thu, 5 May 2016 18:02:44 -0700 Subject: [PATCH 01/11] ARM: dts: rockchip: add SPI flash node for rk3288-veyron This is a standard binding for describing SPI flash that can be identified by reading their JEDEC ID. Let's use it. Tested on Veyron Jaq. Signed-off-by: Brian Norris Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index b2557bf5a58f..5e4c690c7d4f 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -383,6 +383,12 @@ status = "okay"; rx-sample-delay-ns = <12>; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; }; &tsadc { From 6c42db30d8c808d1d04a8178a29e085b8b5eb475 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Mon, 9 May 2016 12:46:34 +0200 Subject: [PATCH 02/11] ARM: dts: rockchip: Add shared file for audio on rk3288-veyron boards Set i2s block to "okay", add sound node for max98090 with gpios for HP and Mic detect and pinctrl, and add a max98090 device and ts3a227e to the correct i2c bus. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Heiko Stuebner --- .../boot/dts/rk3288-veyron-analog-audio.dtsi | 101 ++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi diff --git a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi new file mode 100644 index 000000000000..3d57c050f9b6 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi @@ -0,0 +1,101 @@ +/* + * Google Veyron (and derivatives) fragment for the max98090 audio + * codec and analog headphone jack. + * + * Copyright 2016 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + sound { + compatible = "rockchip,rockchip-audio-max98090"; + pinctrl-names = "default"; + pinctrl-0 = <&mic_det>, <&hp_det>; + rockchip,model = "ROCKCHIP-I2S"; + rockchip,i2s-controller = <&i2s>; + rockchip,audio-codec = <&max98090>; + rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; + rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + rockchip,headset-codec = <&headsetcodec>; + }; +}; + +&i2c2 { + max98090: max98090@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpio6>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + clock-names = "mclk"; + clocks = <&cru SCLK_I2S0_OUT>; + pinctrl-names = "default"; + pinctrl-0 = <&int_codec>; + }; +}; + +&i2c4 { + headsetcodec: ts3a227e@3b { + compatible = "ti,ts3a227e"; + reg = <0x3b>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ts3a227e_int_l>; + ti,micbias = <7>; /* MICBIAS = 2.8V */ + }; +}; + +&i2s { + status = "okay"; +}; + +&io_domains { + audio-supply = <&vcc18_codec>; +}; + +&rk808 { + vcc10-supply = <&vcc33_sys>; + + regulators { + vcc18_codec: LDO_REG6 { + regulator-name = "vcc18_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; +}; + +&pinctrl { + codec { + hp_det: hp-det { + rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + /* + * HACK: We're going to _pull down_ this _active low_ interrupt + * so that it never fires. We don't need this interrupt because + * we've got a ts3a227e chip but the driver requires it. + */ + int_codec: int-codec { + rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + mic_det: mic-det { + rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headset { + ts3a227e_int_l: ts3a227e-int-l { + rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; From 7dbc2b97ba8aac7168c39a7f9148110f6eaa5053 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Mon, 9 May 2016 12:46:35 +0200 Subject: [PATCH 03/11] ARM: dts: rockchip: Enable analog audio on rk3288-veyron chromebooks Add analog-audio functionality for Veyron devices. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index 2958c36d12a0..ce1f87980bcb 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -46,6 +46,7 @@ #include #include #include "rk3288-veyron.dtsi" +#include "rk3288-veyron-analog-audio.dtsi" #include "rk3288-veyron-sdmmc.dtsi" / { From 3445b2fae55f1a232e6e4843f4f74de074d8c07f Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 21 May 2016 01:36:17 +0200 Subject: [PATCH 04/11] ARM: dts: rockchip: move rk3288 io-domain nodes to the grf io-voltage control is actually part of the grf, so move the node under the newly available grf simple-mfd. To minimize duplicate code, the core node and compatible property gets placed in the core rk3288.dtsi while the individual boards now only need to enable it and add the necessary supply properties. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-firefly.dtsi | 31 ++++++++++++------------- arch/arm/boot/dts/rk3288-miqi.dts | 26 ++++++++++----------- arch/arm/boot/dts/rk3288-popmetal.dts | 31 ++++++++++++------------- arch/arm/boot/dts/rk3288-rock2-som.dtsi | 31 ++++++++++++------------- arch/arm/boot/dts/rk3288-veyron.dtsi | 25 ++++++++++---------- arch/arm/boot/dts/rk3288.dtsi | 5 ++++ 6 files changed, 75 insertions(+), 74 deletions(-) diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index d6cf9ada13c9..114c90fb65e2 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -64,22 +64,6 @@ clock-output-names = "ext_gmac"; }; - io_domains: io-domains { - compatible = "rockchip,rk3288-io-voltage-domain"; - rockchip,grf = <&grf>; - - audio-supply = <&vcca_33>; - bb-supply = <&vcc_io>; - dvp-supply = <&dovdd_1v8>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vccio_wl>; - }; - ir: ir-receiver { compatible = "gpio-ir-receiver"; pinctrl-names = "default"; @@ -397,6 +381,21 @@ status = "okay"; }; +&io_domains { + status = "okay"; + + audio-supply = <&vcca_33>; + bb-supply = <&vcc_io>; + dvp-supply = <&dovdd_1v8>; + flash0-supply = <&vcc_flash>; + flash1-supply = <&vcc_lan>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vccio_wl>; +}; + &pinctrl { pcfg_output_high: pcfg-output-high { output-high; diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts index 8643103d8cd8..24488421f0f0 100644 --- a/arch/arm/boot/dts/rk3288-miqi.dts +++ b/arch/arm/boot/dts/rk3288-miqi.dts @@ -64,19 +64,6 @@ clock-output-names = "ext_gmac"; }; - io_domains: io-domains { - compatible = "rockchip,rk3288-io-voltage-domain"; - - audio-supply = <&vcca_33>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc_18>; - }; - leds { compatible = "gpio-leds"; @@ -321,6 +308,19 @@ status = "okay"; }; +&io_domains { + status = "okay"; + + audio-supply = <&vcca_33>; + flash0-supply = <&vcc_flash>; + flash1-supply = <&vcc_lan>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_18>; +}; + &pinctrl { pcfg_output_high: pcfg-output-high { output-high; diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index 720717bb3614..dda8d259bb6d 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -77,22 +77,6 @@ }; }; - io_domains: io-domains { - compatible = "rockchip,rk3288-io-voltage-domain"; - rockchip,grf = <&grf>; - - audio-supply = <&vcca_33>; - bb-supply = <&vcc_io>; - dvp-supply = <&vcc18_dvp>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vccio_wl>; - }; - ir: ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; @@ -437,6 +421,21 @@ status = "okay"; }; +&io_domains { + status = "okay"; + + audio-supply = <&vcca_33>; + bb-supply = <&vcc_io>; + dvp-supply = <&vcc18_dvp>; + flash0-supply = <&vcc_flash>; + flash1-supply = <&vcc_lan>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vccio_wl>; +}; + &pinctrl { ak8963 { comp_int: comp-int { diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi index e1ee9f949035..bb1f01e037ba 100644 --- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi +++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi @@ -61,22 +61,6 @@ clock-output-names = "ext_gmac"; }; - io_domains: io-domains { - compatible = "rockchip,rk3288-io-voltage-domain"; - rockchip,grf = <&grf>; - - audio-supply = <&vcc_io>; - bb-supply = <&vcc_io>; - dvp-supply = <&vcc_18>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vccio_pmu>; - gpio30-supply = <&vccio_pmu>; - gpio1830 = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc_18>; - }; - vcc_flash: flash-regulator { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -259,6 +243,21 @@ }; }; +&io_domains { + status = "okay"; + + audio-supply = <&vcc_io>; + bb-supply = <&vcc_io>; + dvp-supply = <&vcc_18>; + flash0-supply = <&vcc_flash>; + flash1-supply = <&vccio_pmu>; + gpio30-supply = <&vccio_pmu>; + gpio1830 = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_18>; +}; + &pinctrl { pcfg_output_high: pcfg-output-high { output-high; diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 5e4c690c7d4f..3dd2cca48c11 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -83,19 +83,6 @@ reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; }; - io_domains: io-domains { - compatible = "rockchip,rk3288-io-voltage-domain"; - rockchip,grf = <&grf>; - - bb-supply = <&vcc33_io>; - dvp-supply = <&vcc_18>; - flash0-supply = <&vcc18_flashio>; - gpio1830-supply = <&vcc33_io>; - gpio30-supply = <&vcc33_io>; - lcdc-supply = <&vcc33_lcd>; - wifi-supply = <&vcc18_wl>; - }; - sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rk808 RK808_CLKOUT1>; @@ -355,6 +342,18 @@ i2c-scl-rising-time-ns = <1000>; }; +&io_domains { + status = "okay"; + + bb-supply = <&vcc33_io>; + dvp-supply = <&vcc_18>; + flash0-supply = <&vcc18_flashio>; + gpio1830-supply = <&vcc33_io>; + gpio30-supply = <&vcc33_io>; + lcdc-supply = <&vcc33_lcd>; + wifi-supply = <&vcc18_wl>; +}; + &pwm1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 3b44ef3cff12..7fa932fcd08e 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -826,6 +826,11 @@ #phy-cells = <0>; status = "disabled"; }; + + io_domains: io-domains { + compatible = "rockchip,rk3288-io-voltage-domain"; + status = "disabled"; + }; }; wdt: watchdog@ff800000 { From 7a25d3965726768b0eba9222138d9d47d050bbe1 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 9 Jun 2016 10:03:36 +0200 Subject: [PATCH 05/11] ARM: dts: rockchip: rename i2s model for Veyron devices Commit 6c42db30d8c8 introduced audio support based on alsa ucm profiles taken from the ChromeOS userspace. Both in the kernel as well as alsa they were named (and matched against) ROCKCHIP-I2S. Audio profiles are very much board-specific and hogging the ROCKCHIP-I2S name would make it harder for future boards and also is misleading. For Veyron boards the audio setup is similar over all variants, so VEYRON-I2S is a more suitable name. This rename also was merged into the alsa ucm profile so both userspace and kernel match and the old naming was never released in any alsa or kernel release. Fixes: 6c42db30d8c8 ("ARM: dts: rockchip: Add shared file for audio on rk3288-veyron boards") Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi index 3d57c050f9b6..6d105914a4f3 100644 --- a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi @@ -14,7 +14,7 @@ compatible = "rockchip,rockchip-audio-max98090"; pinctrl-names = "default"; pinctrl-0 = <&mic_det>, <&hp_det>; - rockchip,model = "ROCKCHIP-I2S"; + rockchip,model = "VEYRON-I2S"; rockchip,i2s-controller = <&i2s>; rockchip,audio-codec = <&max98090>; rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; From 5f6d71044f4d766c3636b9fd2c43e7c9d71d31af Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Tue, 21 Jun 2016 12:53:29 +0800 Subject: [PATCH 06/11] clk: rockchip: add clock-ids for rk3228 audio clocks This patch exports related i2s/spdif clocks for dts reference. Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner --- include/dt-bindings/clock/rk3228-cru.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index 5d43ed9b05ad..c992f3e50e25 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -84,6 +84,10 @@ #define PCLK_HDMI_PHY 365 /* hclk gates */ +#define HCLK_I2S0_8CH 442 +#define HCLK_I2S1_8CH 443 +#define HCLK_I2S2_2CH 444 +#define HCLK_SPDIF_8CH 445 #define HCLK_VOP 452 #define HCLK_NANDC 453 #define HCLK_SDMMC 456 From 9ff59360b863706b50cbcd7ffad9287d67254063 Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Tue, 21 Jun 2016 12:59:47 +0800 Subject: [PATCH 07/11] clk: rockchip: add clock-ids for rk3228 MAC clocks This patch exports related MAC clocks for dts reference. Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner --- include/dt-bindings/clock/rk3228-cru.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index c992f3e50e25..b27e2b1a65e3 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -52,6 +52,15 @@ #define SCLK_EMMC_SAMPLE 121 #define SCLK_VOP 122 #define SCLK_HDMI_HDCP 123 +#define SCLK_MAC_SRC 124 +#define SCLK_MAC_EXTCLK 125 +#define SCLK_MAC 126 +#define SCLK_MAC_REFOUT 127 +#define SCLK_MAC_REF 128 +#define SCLK_MAC_RX 129 +#define SCLK_MAC_TX 130 +#define SCLK_MAC_PHY 131 +#define SCLK_MAC_OUT 132 /* dclk gates */ #define DCLK_VOP 190 @@ -61,6 +70,7 @@ #define ACLK_DMAC 194 #define ACLK_PERI 210 #define ACLK_VOP 211 +#define ACLK_GMAC 212 /* pclk gates */ #define PCLK_GPIO0 320 @@ -82,6 +92,7 @@ #define PCLK_PERI 363 #define PCLK_HDMI_CTRL 364 #define PCLK_HDMI_PHY 365 +#define PCLK_GMAC 367 /* hclk gates */ #define HCLK_I2S0_8CH 442 From 8372d93df7c265a67676dcd329da9588cc769192 Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Wed, 22 Jun 2016 11:16:50 +0800 Subject: [PATCH 08/11] ARM: dts: rockchip: rename rk3228.dtsi to rk322x.dtsi We have the brother chipset that RK3228 and RK3229, they share most of dts configuration, but there are a number of different features. In order to develop the future when they are easy to distinguish, we need them to be independent. Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3228-evb.dts | 2 +- arch/arm/boot/dts/{rk3228.dtsi => rk322x.dtsi} | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) rename arch/arm/boot/dts/{rk3228.dtsi => rk322x.dtsi} (99%) diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts index 5956e8246abe..904668e2e666 100644 --- a/arch/arm/boot/dts/rk3228-evb.dts +++ b/arch/arm/boot/dts/rk3228-evb.dts @@ -40,7 +40,7 @@ /dts-v1/; -#include "rk3228.dtsi" +#include "rk322x.dtsi" / { model = "Rockchip RK3228 Evaluation board"; diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk322x.dtsi similarity index 99% rename from arch/arm/boot/dts/rk3228.dtsi rename to arch/arm/boot/dts/rk322x.dtsi index e23a22e29155..a68fdcaf44ff 100644 --- a/arch/arm/boot/dts/rk3228.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -47,8 +47,6 @@ #include "skeleton.dtsi" / { - compatible = "rockchip,rk3228"; - interrupt-parent = <&gic>; aliases { From ccada2489206b5f1870ac132408bf41ffe51995a Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Wed, 22 Jun 2016 11:16:51 +0800 Subject: [PATCH 09/11] ARM: dts: rockchip: add i2s nodes for RK322x SoCs This patch add the i2s dt nodes for rk322x SoCs. Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 55 +++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index a68fdcaf44ff..26f3becc83c4 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -138,6 +138,47 @@ #clock-cells = <0>; }; + i2s1: i2s1@100b0000 { + compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; + reg = <0x100b0000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; + dmas = <&pdma 14>, <&pdma 15>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + status = "disabled"; + }; + + i2s0: i2s0@100c0000 { + compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; + reg = <0x100c0000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; + dmas = <&pdma 11>, <&pdma 12>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2s2: i2s2@100e0000 { + compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; + reg = <0x100e0000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; + dmas = <&pdma 0>, <&pdma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + grf: syscon@11000000 { compatible = "syscon"; reg = <0x11000000 0x1000>; @@ -507,6 +548,20 @@ }; }; + i2s1 { + i2s1_bus: i2s1-bus { + rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>, + <0 9 RK_FUNC_1 &pcfg_pull_none>, + <0 11 RK_FUNC_1 &pcfg_pull_none>, + <0 12 RK_FUNC_1 &pcfg_pull_none>, + <0 13 RK_FUNC_1 &pcfg_pull_none>, + <0 14 RK_FUNC_1 &pcfg_pull_none>, + <1 2 RK_FUNC_1 &pcfg_pull_none>, + <1 4 RK_FUNC_1 &pcfg_pull_none>, + <1 5 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + pwm0 { pwm0_pin: pwm0-pin { rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; From 5d3d7c72b920f9aa44f9b64cdd8a1c5bf5cbea07 Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Wed, 22 Jun 2016 11:16:52 +0800 Subject: [PATCH 10/11] ARM: dts: rockchip: add GMAC nodes for RK322x SoCs This patch add the GMAC dt nodes for rk322x SoCs. Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 61 +++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 26f3becc83c4..9e6bf0e311bb 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -415,6 +415,25 @@ status = "disabled"; }; + gmac: ethernet@30200000 { + compatible = "rockchip,rk3228-gmac"; + reg = <0x30200000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, + <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, + <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, + <&cru PCLK_GMAC>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "clk_mac_refout", "aclk_mac", + "pclk_mac"; + resets = <&cru SRST_GMAC>; + reset-names = "stmmaceth"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + gic: interrupt-controller@32010000 { compatible = "arm,gic-400"; interrupt-controller; @@ -499,6 +518,10 @@ bias-disable; }; + pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { + drive-strength = <12>; + }; + emmc { emmc_clk: emmc-clk { rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; @@ -520,6 +543,44 @@ }; }; + gmac { + rgmii_pins: rgmii-pins { + rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>, + <2 12 RK_FUNC_1 &pcfg_pull_none>, + <2 25 RK_FUNC_1 &pcfg_pull_none>, + <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 17 RK_FUNC_1 &pcfg_pull_none>, + <2 16 RK_FUNC_1 &pcfg_pull_none>, + <2 21 RK_FUNC_2 &pcfg_pull_none>, + <2 20 RK_FUNC_2 &pcfg_pull_none>, + <2 11 RK_FUNC_1 &pcfg_pull_none>, + <2 8 RK_FUNC_1 &pcfg_pull_none>; + }; + + rmii_pins: rmii-pins { + rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>, + <2 12 RK_FUNC_1 &pcfg_pull_none>, + <2 25 RK_FUNC_1 &pcfg_pull_none>, + <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 17 RK_FUNC_1 &pcfg_pull_none>, + <2 16 RK_FUNC_1 &pcfg_pull_none>, + <2 8 RK_FUNC_1 &pcfg_pull_none>, + <2 15 RK_FUNC_1 &pcfg_pull_none>; + }; + + phy_pins: phy-pins { + rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>, + <2 8 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, From 241eff3c198492b2d63e75723b774f2836fee8a3 Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Wed, 22 Jun 2016 11:16:53 +0800 Subject: [PATCH 11/11] ARM: dts: rockchip: add support rk3229 evb board Initial release for rk3229 evb board, and turn the GMAC on. Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner --- .../devicetree/bindings/arm/rockchip.txt | 3 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rk3229-evb.dts | 90 +++++++++++++++++++ 3 files changed, 94 insertions(+) create mode 100644 arch/arm/boot/dts/rk3229-evb.dts diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 715d960d5eea..666864517069 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -107,6 +107,9 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; +- Rockchip RK3229 Evaluation board: + - compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; + - Rockchip RK3399 evb: Required root node properties: - compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 06b6c2d695bf..5e0833f72ea3 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -602,6 +602,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3066a-rayeager.dtb \ rk3188-radxarock.dtb \ rk3228-evb.dtb \ + rk3229-evb.dtb \ rk3288-evb-act8846.dtb \ rk3288-evb-rk808.dtb \ rk3288-firefly-beta.dtb \ diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts new file mode 100644 index 000000000000..b6a12035a6bb --- /dev/null +++ b/arch/arm/boot/dts/rk3229-evb.dts @@ -0,0 +1,90 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "rk322x.dtsi" + +/ { + model = "Rockchip RK3229 Evaluation board"; + compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + ext_gmac: ext_gmac { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc_phy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>; + clock_in_out = "input"; + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +};