This pull request contains Broadcom ARM64 SoCs Device Tree changes for
6.12, please pull the following: - Andrea adds a minimal Device Tree for the Raspberry Pi 5 (2712) - Stefan adjusts the bcm2837/bcm2712 bcm2836-l1-intc node name to conform to the binding changes -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmbZ5BoACgkQh9CWnEQH BwQYRA//dS3SrugL3dBfEtrGDjn+mCH5Nk/EajkDMoJuY6H9uh1hZPpL1wzhZx00 JNn5AvrOdBxjpd32EyxxbyH+ubaQR/mi88AR7YpUE1xuEaCMrt2KQtL2MP0l6ccb a3QRUMW+pTFzFahU3iO8u8bw/uP8EtxeZgh431IXlvmdxJ0zS+jJ40b9hAK0Vvr8 oPnB1+076rSZRJi/EG8klk4eY5bx6XvGV8vUEn/KY7hqitK43V5UM1kEhuWM8Z6a quGvV7nL5ikVbGtUF/q+UDjpJ7rde80WP/MWtPAn2I9vpkqa0RZgZP9f6A4dfv22 hrDWVOzYu3TiPiTelZxevTlxsvU8TWhsA8BfhcTgS02P++JoYPJx3mVZNbzyThDO Am3PGkQ2k4yiSyju+DoSKEcsBZuCRqNDjSSamKQIq9Z4RnvQ5i0CPWgK/8IbEhBV Qh8eP0+rp0EfDwoMCLTivtj9kD2QH9WtTzhIfAmLI386YOPPUU0x1nrIZmajoRTx MVJ48GOW//uHrGEFWiT8x17RRCzrqJ+uPYaqDdjKOx79dvdE6S5USi+anavUXqvd 52fGe+QYFot96OXBYqkomnzg0ojPb3l2/3M9PGieP3THACTezD52hL3BPQR8LVeg Ij2ccJd0Z2B4WOo2eN4MW3bELbn+qF+c7G6PMkns4+h0azAXtKc= =k60v -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmbhWaMACgkQYKtH/8kJ UicGcxAAm7XTkPudtXfgboLLCOnK2YfY6JpdDwFS4iRp6H+qZD5A2UoDWMZRUKO6 p3u08EEwADeBe3iPyxLFxCoPuoh9VV1qDELojZxa7QxQEZxZB3EXa7LOhEUojAwG LP1W+Aa20NarWbWYg+g1dH4Xpxt5zF2ON2lI5TPElQ2QQ3JgEl9TVDsrLgHHJFPz CQ7MSFhJZTWLxeZAjMH+a9HuNFPgOyvNMjXskBCNLoHsfb3/6BSEzLKvsZURoZxI nMffM7D+n1WvyL5hEMdNr2WduTOrMjnrqSzQw1XxPMXsZQmt+4p19I8NNJXKpL7X jK8rzHEgHZNgNPhjMHWrwasrmrsnUdV+cBiGn+xp9Hhjoyd/EhnZUXr6nyhe4xEO FVV14Xmq3T7xTW30S/rDd6+Bfr5xzB2e5CSBoQXaPo1nGnEWDWDQxAIyRT7qnSQw A9/Dyrv/1bME5FNdX1tpP8rBALP7wD/kC4FIaHPwBcptDqZTWhzIrgO3zTEt8eaW DijYnIfisunW54HS6+ad+lAL9zYKEIHuXPALN5jY7BjAUG0nnrVxwYLTAEHmdXlw 1aOPCjI2R8tk3lcFsnVKS4HcQKxxElYoNHD8Orf751KBMsGMlgAkcCLU4grKt0NY hRQi5+Zx003hhhLHWSep2CK/lAa0qHlvkucewM+sOqoKvKFSSNM= =y4Wd -----END PGP SIGNATURE----- Merge tag 'arm-soc/for-6.12/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt This pull request contains Broadcom ARM64 SoCs Device Tree changes for 6.12, please pull the following: - Andrea adds a minimal Device Tree for the Raspberry Pi 5 (2712) - Stefan adjusts the bcm2837/bcm2712 bcm2836-l1-intc node name to conform to the binding changes * tag 'arm-soc/for-6.12/devicetree-arm64' of https://github.com/Broadcom/stblinux: ARM: dts: bcm2837/bcm2712: adjust local intc node names arm64: dts: broadcom: Add minimal support for Raspberry Pi 5 Link: https://lore.kernel.org/r/20240906180643.2275460-2-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>pull/958/head
Arnd Bergmann
commit
af0103eccc
|
|
@ -9,7 +9,7 @@
|
|||
<0x40000000 0x40000000 0x00001000>;
|
||||
dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
|
||||
|
||||
local_intc: local_intc@40000000 {
|
||||
local_intc: interrupt-controller@40000000 {
|
||||
compatible = "brcm,bcm2836-l1-intc";
|
||||
reg = <0x40000000 0x100>;
|
||||
interrupt-controller;
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@ DTC_FLAGS := -@
|
|||
dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \
|
||||
bcm2711-rpi-4-b.dtb \
|
||||
bcm2711-rpi-cm4-io.dtb \
|
||||
bcm2712-rpi-5-b.dtb \
|
||||
bcm2837-rpi-3-a-plus.dtb \
|
||||
bcm2837-rpi-3-b.dtb \
|
||||
bcm2837-rpi-3-b-plus.dtb \
|
||||
|
|
|
|||
|
|
@ -0,0 +1,64 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "bcm2712.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "raspberrypi,5-model-b", "brcm,bcm2712";
|
||||
model = "Raspberry Pi 5";
|
||||
|
||||
aliases {
|
||||
serial10 = &uart10;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial10:115200n8";
|
||||
};
|
||||
|
||||
/* Will be filled by the bootloader */
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0 0 0x28000000>;
|
||||
};
|
||||
|
||||
sd_io_1v8_reg: sd-io-1v8-reg {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "vdd-sd-io";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-settling-time-us = <5000>;
|
||||
gpios = <&gio_aon 3 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 1>,
|
||||
<3300000 0>;
|
||||
};
|
||||
|
||||
sd_vcc_reg: sd-vcc-reg {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc-sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
/* The Debug UART, on Rpi5 it's on JST-SH 1.0mm 3-pin connector
|
||||
* labeled "UART", i.e. the interface with the system console.
|
||||
*/
|
||||
&uart10 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SDIO1 is used to drive the SD card */
|
||||
&sdio1 {
|
||||
vqmmc-supply = <&sd_io_1v8_reg>;
|
||||
vmmc-supply = <&sd_vcc_reg>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-ddr50;
|
||||
sd-uhs-sdr104;
|
||||
};
|
||||
|
|
@ -0,0 +1,283 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm2712";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
interrupt-parent = <&gicv2>;
|
||||
|
||||
clocks {
|
||||
/* The oscillator is the root of the clock tree. */
|
||||
clk_osc: clk-osc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "osc";
|
||||
clock-frequency = <54000000>;
|
||||
};
|
||||
|
||||
clk_vpu: clk-vpu {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <750000000>;
|
||||
clock-output-names = "vpu-clock";
|
||||
};
|
||||
|
||||
clk_uart: clk-uart {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <9216000>;
|
||||
clock-output-names = "uart-clock";
|
||||
};
|
||||
|
||||
clk_emmc2: clk-emmc2 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
clock-output-names = "emmc2-clock";
|
||||
};
|
||||
};
|
||||
|
||||
cpus: cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Source for L1 d/i cache-line-size, cache-sets, cache-size
|
||||
* https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?lang=en
|
||||
* Source for L2 cache-line-size and cache-sets:
|
||||
* https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?lang=en
|
||||
* and for cache-size:
|
||||
* https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
|
||||
*/
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a76";
|
||||
reg = <0x000>;
|
||||
enable-method = "psci";
|
||||
d-cache-size = <0x10000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
|
||||
i-cache-size = <0x10000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
|
||||
next-level-cache = <&l2_cache_l0>;
|
||||
|
||||
l2_cache_l0: l2-cache-l0 {
|
||||
compatible = "cache";
|
||||
cache-size = <0x80000>;
|
||||
cache-line-size = <128>;
|
||||
cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&l3_cache>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a76";
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
d-cache-size = <0x10000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
|
||||
i-cache-size = <0x10000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
|
||||
next-level-cache = <&l2_cache_l1>;
|
||||
|
||||
l2_cache_l1: l2-cache-l1 {
|
||||
compatible = "cache";
|
||||
cache-size = <0x80000>;
|
||||
cache-line-size = <128>;
|
||||
cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&l3_cache>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a76";
|
||||
reg = <0x200>;
|
||||
enable-method = "psci";
|
||||
d-cache-size = <0x10000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
|
||||
i-cache-size = <0x10000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
|
||||
next-level-cache = <&l2_cache_l2>;
|
||||
|
||||
l2_cache_l2: l2-cache-l2 {
|
||||
compatible = "cache";
|
||||
cache-size = <0x80000>;
|
||||
cache-line-size = <128>;
|
||||
cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&l3_cache>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a76";
|
||||
reg = <0x300>;
|
||||
enable-method = "psci";
|
||||
d-cache-size = <0x10000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
|
||||
i-cache-size = <0x10000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
|
||||
next-level-cache = <&l2_cache_l3>;
|
||||
|
||||
l2_cache_l3: l2-cache-l3 {
|
||||
compatible = "cache";
|
||||
cache-size = <0x80000>;
|
||||
cache-line-size = <128>;
|
||||
cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&l3_cache>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Source for cache-line-size and cache-sets:
|
||||
* https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en
|
||||
* Source for cache-size:
|
||||
* https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
|
||||
*/
|
||||
l3_cache: l3-cache {
|
||||
compatible = "cache";
|
||||
cache-size = <0x200000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set
|
||||
cache-level = <3>;
|
||||
cache-unified;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
method = "smc";
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
};
|
||||
|
||||
rmem: reserved-memory {
|
||||
ranges;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
atf@0 {
|
||||
reg = <0x0 0x0 0x0 0x80000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
cma: linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0x0 0x4000000>; /* 64MB */
|
||||
reusable;
|
||||
linux,cma-default;
|
||||
alloc-ranges = <0x0 0x00000000 0x0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@107c000000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00000000 0x10 0x00000000 0x80000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sdio1: mmc@fff000 {
|
||||
compatible = "brcm,bcm2712-sdhci",
|
||||
"brcm,sdhci-brcmstb";
|
||||
reg = <0x00fff000 0x260>,
|
||||
<0x00fff400 0x200>;
|
||||
reg-names = "host", "cfg";
|
||||
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_emmc2>;
|
||||
clock-names = "sw_sdio";
|
||||
mmc-ddr-3_3v;
|
||||
};
|
||||
|
||||
system_timer: timer@7c003000 {
|
||||
compatible = "brcm,bcm2835-system-timer";
|
||||
reg = <0x7c003000 0x1000>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
|
||||
mailbox: mailbox@7c013880 {
|
||||
compatible = "brcm,bcm2835-mbox";
|
||||
reg = <0x7c013880 0x40>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <0>;
|
||||
};
|
||||
|
||||
local_intc: interrupt-controller@7cd00000 {
|
||||
compatible = "brcm,bcm2836-l1-intc";
|
||||
reg = <0x7cd00000 0x100>;
|
||||
};
|
||||
|
||||
uart10: serial@7d001000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x7d001000 0x200>;
|
||||
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_uart>, <&clk_vpu>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
arm,primecell-periphid = <0x00241011>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
interrupt-controller@7d517000 {
|
||||
compatible = "brcm,bcm7271-l2-intc";
|
||||
reg = <0x7d517000 0x10>;
|
||||
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gio_aon: gpio@7d517c00 {
|
||||
compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
|
||||
reg = <0x7d517c00 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
brcm,gpio-bank-widths = <17 6>;
|
||||
/* The lack of 'interrupt-controller' property here is intended:
|
||||
* don't use GIO_AON as an interrupt controller because it will
|
||||
* clash with the firmware monitoring the PMIC interrupt via the VPU.
|
||||
*/
|
||||
};
|
||||
|
||||
gicv2: interrupt-controller@7fff9000 {
|
||||
compatible = "arm,gic-400";
|
||||
reg = <0x7fff9000 0x1000>,
|
||||
<0x7fffa000 0x2000>,
|
||||
<0x7fffc000 0x2000>,
|
||||
<0x7fffe000 0x2000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) |
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue