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Merge tag 'br-v6.2d' of git://linuxtv.org/hverkuil/media_tree into media_stage

Tag branch

* tag 'br-v6.2d' of git://linuxtv.org/hverkuil/media_tree: (35 commits)
  media: saa7164: remove variable cnt
  atomisp: fix potential NULL pointer dereferences
  radio-terratec: Remove variable p
  media: platform: s5p-mfc: Fix spelling mistake "mmaping" -> "mmapping"
  media: platform: mtk-mdp3: remove unused VIDEO_MEDIATEK_VPU config
  media: vivid: remove redundant assignment to variable checksum
  media: cedrus: h264: Optimize mv col buffer allocation
  media: cedrus: h265: Associate mv col buffers with buffer
  media: mediatek: vcodec: fix h264 cavlc bitstream fail
  media: cedrus: hevc: Fix offset adjustments
  media: imx-jpeg: Fix Coverity issue in probe
  media: v4l2-ioctl.c: Unify YCbCr/YUV terms in format descriptions
  media: atomisp: Fix spelling mistake "mis-match" -> "mismatch"
  media: c8sectpfe: Add missed header(s)
  media: adv748x: afe: Select input port when initializing AFE
  media: vimc: Update device configuration in the documentation
  media: adv748x: Remove dead function declaration
  media: mxl5005s: Make array RegAddr static const
  media: atomisp: Fix spelling mistake "modee" -> "mode"
  media: meson/vdec: always init coef_node_start
  ...
pull/520/merge
Mauro Carvalho Chehab 2022-11-15 12:11:46 +00:00
parent a7bab6f8b7 16f3211110
commit b9fbe29c59
35 changed files with 247 additions and 192 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/media/dvb-frontends/cxd2820r_priv.h
View File

@ -52,8 +52,6 @@ struct cxd2820r_priv {
/* cxd2820r_core.c */
extern int cxd2820r_debug;
int cxd2820r_gpio(struct dvb_frontend *fe, u8 *gpio);
int cxd2820r_wr_reg_val_mask_tab(struct cxd2820r_priv *priv,

2
drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h
View File

@ -234,8 +234,6 @@
/*-------- Public API functions ----------------------------------------------*/
extern struct drx_access_func drx_dap_fasi_funct_g;
#define DRXDAP_FASI_RMW 0x10000000
#define DRXDAP_FASI_BROADCAST 0x20000000
#define DRXDAP_FASI_CLEARCRC 0x80000000

4
drivers/media/i2c/adv748x/adv748x-afe.c
View File

@ -521,6 +521,10 @@ int adv748x_afe_init(struct adv748x_afe *afe)
}
}
adv748x_afe_s_input(afe, afe->input);
adv_dbg(state, "AFE Default input set to %d\n", afe->input);
/* Entity pads and sinks are 0-indexed to match the pads */
for (i = ADV748X_AFE_SINK_AIN0; i <= ADV748X_AFE_SINK_AIN7; i++)
afe->pads[i].flags = MEDIA_PAD_FL_SINK;

3
drivers/media/i2c/adv748x/adv748x.h
View File

@ -428,9 +428,6 @@ void adv748x_subdev_init(struct v4l2_subdev *sd, struct adv748x_state *state,
const struct v4l2_subdev_ops *ops, u32 function,
const char *ident);
int adv748x_register_subdevs(struct adv748x_state *state,
struct v4l2_device *v4l2_dev);
int adv748x_tx_power(struct adv748x_csi2 *tx, bool on);
int adv748x_afe_init(struct adv748x_afe *afe);

1
drivers/media/pci/bt8xx/bttv.h
View File

@ -289,7 +289,6 @@ extern void bttv_init_card2(struct bttv *btv);
extern void bttv_init_tuner(struct bttv *btv);
/* card-specific functions */
extern void tea5757_set_freq(struct bttv *btv, unsigned short freq);
extern u32 bttv_tda9880_setnorm(struct bttv *btv, u32 gpiobits);
/* extra tweaks for some chipsets */

3
drivers/media/pci/cx25821/cx25821-video.h
View File

@ -36,9 +36,6 @@ do { \
} while (0)
#define FORMAT_FLAGS_PACKED 0x01
extern void cx25821_video_wakeup(struct cx25821_dev *dev,
struct cx25821_dmaqueue *q, u32 count);
extern int cx25821_start_video_dma(struct cx25821_dev *dev,
struct cx25821_dmaqueue *q,
struct cx25821_buffer *buf,

4
drivers/media/pci/saa7134/saa7134.h
View File

@ -866,7 +866,6 @@ int saa7134_ts_stop(struct saa7134_dev *dev);
/* saa7134-vbi.c */
extern const struct vb2_ops saa7134_vbi_qops;
extern struct video_device saa7134_vbi_template;
int saa7134_vbi_init1(struct saa7134_dev *dev);
int saa7134_vbi_fini(struct saa7134_dev *dev);
@ -897,9 +896,6 @@ void saa7134_enable_i2s(struct saa7134_dev *dev);
/* ----------------------------------------------------------- */
/* saa7134-oss.c */
extern const struct file_operations saa7134_dsp_fops;
extern const struct file_operations saa7134_mixer_fops;
int saa7134_oss_init1(struct saa7134_dev *dev);
int saa7134_oss_fini(struct saa7134_dev *dev);
void saa7134_irq_oss_done(struct saa7134_dev *dev, unsigned long status);

6
drivers/media/pci/saa7164/saa7164-core.c
View File

@ -352,7 +352,7 @@ static void saa7164_work_enchandler(struct work_struct *w)
container_of(w, struct saa7164_port, workenc);
struct saa7164_dev *dev = port->dev;
u32 wp, mcb, rp, cnt = 0;
u32 wp, mcb, rp;
port->last_svc_msecs_diff = port->last_svc_msecs;
port->last_svc_msecs = jiffies_to_msecs(jiffies);
@ -405,7 +405,6 @@ static void saa7164_work_enchandler(struct work_struct *w)
saa7164_work_enchandler_helper(port, rp);
port->last_svc_rp = rp;
cnt++;
if (rp == mcb)
break;
@ -429,7 +428,7 @@ static void saa7164_work_vbihandler(struct work_struct *w)
container_of(w, struct saa7164_port, workenc);
struct saa7164_dev *dev = port->dev;
u32 wp, mcb, rp, cnt = 0;
u32 wp, mcb, rp;
port->last_svc_msecs_diff = port->last_svc_msecs;
port->last_svc_msecs = jiffies_to_msecs(jiffies);
@ -481,7 +480,6 @@ static void saa7164_work_vbihandler(struct work_struct *w)
saa7164_work_enchandler_helper(port, rp);
port->last_svc_rp = rp;
cnt++;
if (rp == mcb)
break;

2
drivers/media/pci/saa7164/saa7164.h
View File

@ -493,8 +493,6 @@ int saa7164_downloadfirmware(struct saa7164_dev *dev);
/* saa7164-i2c.c */
extern int saa7164_i2c_register(struct saa7164_i2c *bus);
extern int saa7164_i2c_unregister(struct saa7164_i2c *bus);
extern void saa7164_call_i2c_clients(struct saa7164_i2c *bus,
unsigned int cmd, void *arg);
/* ----------------------------------------------------------- */
/* saa7164-bus.c */

2
drivers/media/pci/zoran/zoran_device.h
View File

@ -47,8 +47,6 @@ void zr36057_restart(struct zoran *zr);
extern const struct zoran_format zoran_formats[];
extern int v4l_bufsize;
extern int jpg_bufsize;
extern int pass_through;
/* i2c */

13
drivers/media/platform/amphion/vdec.c
View File

@ -753,6 +753,9 @@ static bool vdec_check_source_change(struct vpu_inst *inst)
if (!inst->fh.m2m_ctx)
return false;
if (vdec->reset_codec)
return false;
if (!vb2_is_streaming(v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx)))
return true;
fmt = vpu_helper_find_format(inst, inst->cap_format.type, vdec->codec_info.pixfmt);
@ -1088,7 +1091,8 @@ static void vdec_event_seq_hdr(struct vpu_inst *inst, struct vpu_dec_codec_info
vdec->seq_tag = vdec->codec_info.tag;
if (vdec->is_source_changed) {
vdec_update_state(inst, VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE, 0);
vpu_notify_source_change(inst);
vdec->source_change++;
vdec_handle_resolution_change(inst);
vdec->is_source_changed = false;
}
}
@ -1335,6 +1339,8 @@ static void vdec_abort(struct vpu_inst *inst)
vdec->decoded_frame_count,
vdec->display_frame_count,
vdec->sequence);
if (!vdec->seq_hdr_found)
vdec->reset_codec = true;
vdec->params.end_flag = 0;
vdec->drain = 0;
vdec->params.frame_count = 0;
@ -1342,6 +1348,7 @@ static void vdec_abort(struct vpu_inst *inst)
vdec->display_frame_count = 0;
vdec->sequence = 0;
vdec->aborting = false;
inst->extra_size = 0;
}
static void vdec_stop(struct vpu_inst *inst, bool free)
@ -1464,8 +1471,7 @@ static int vdec_start_session(struct vpu_inst *inst, u32 type)
}
if (V4L2_TYPE_IS_OUTPUT(type)) {
if (inst->state == VPU_CODEC_STATE_SEEK)
vdec_update_state(inst, vdec->state, 1);
vdec_update_state(inst, vdec->state, 1);
vdec->eos_received = 0;
vpu_process_output_buffer(inst);
} else {
@ -1629,6 +1635,7 @@ static int vdec_open(struct file *file)
return ret;
vdec->fixed_fmt = false;
vdec->state = VPU_CODEC_STATE_ACTIVE;
inst->min_buffer_cap = VDEC_MIN_BUFFER_CAP;
inst->min_buffer_out = VDEC_MIN_BUFFER_OUT;
vdec_init(file);

16
drivers/media/platform/aspeed/aspeed-video.c
View File

@ -1961,19 +1961,7 @@ static int aspeed_video_debugfs_show(struct seq_file *s, void *data)
return 0;
}
static int aspeed_video_proc_open(struct inode *inode, struct file *file)
{
return single_open(file, aspeed_video_debugfs_show, inode->i_private);
}
static const struct file_operations aspeed_video_debugfs_ops = {
.owner = THIS_MODULE,
.open = aspeed_video_proc_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
DEFINE_SHOW_ATTRIBUTE(aspeed_video_debugfs);
static struct dentry *debugfs_entry;
@ -1987,7 +1975,7 @@ static int aspeed_video_debugfs_create(struct aspeed_video *video)
{
debugfs_entry = debugfs_create_file(DEVICE_NAME, 0444, NULL,
video,
&aspeed_video_debugfs_ops);
&aspeed_video_debugfs_fops);
if (!debugfs_entry)
aspeed_video_debugfs_remove(video);

10
drivers/media/platform/chips-media/coda-jpeg.c
View File

@ -1052,10 +1052,16 @@ static int coda9_jpeg_start_encoding(struct coda_ctx *ctx)
v4l2_err(&dev->v4l2_dev, "error loading Huffman tables\n");
return ret;
}
if (!ctx->params.jpeg_qmat_tab[0])
if (!ctx->params.jpeg_qmat_tab[0]) {
ctx->params.jpeg_qmat_tab[0] = kmalloc(64, GFP_KERNEL);
if (!ctx->params.jpeg_qmat_tab[1])
if (!ctx->params.jpeg_qmat_tab[0])
return -ENOMEM;
}
if (!ctx->params.jpeg_qmat_tab[1]) {
ctx->params.jpeg_qmat_tab[1] = kmalloc(64, GFP_KERNEL);
if (!ctx->params.jpeg_qmat_tab[1])
return -ENOMEM;
}
coda_set_jpeg_compression_quality(ctx, ctx->params.jpeg_quality);
return 0;

1
drivers/media/platform/mediatek/mdp3/Kconfig
View File

@ -9,7 +9,6 @@ config VIDEO_MEDIATEK_MDP3
select VIDEOBUF2_DMA_CONTIG
select V4L2_MEM2MEM_DEV
select MTK_MMSYS
select VIDEO_MEDIATEK_VPU
select MTK_CMDQ
select MTK_SCP
default n

5
drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.c
View File

@ -1397,7 +1397,10 @@ int mtk_vcodec_enc_ctrls_setup(struct mtk_vcodec_ctx *ctx)
0, V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE);
v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_MPEG_VIDEO_H264_PROFILE,
V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
0, V4L2_MPEG_VIDEO_H264_PROFILE_HIGH);
~((1 << V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
(1 << V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
(1 << V4L2_MPEG_VIDEO_H264_PROFILE_HIGH)),
V4L2_MPEG_VIDEO_H264_PROFILE_HIGH);
v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_MPEG_VIDEO_H264_LEVEL,
h264_max_level,
0, V4L2_MPEG_VIDEO_H264_LEVEL_4_0);

32
drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_multi_if.c
View File

@ -539,6 +539,29 @@ vdec_dec_end:
return 0;
}
static void vdec_h264_insert_startcode(struct mtk_vcodec_dev *vcodec_dev, unsigned char *buf,
size_t *bs_size, struct mtk_h264_pps_param *pps)
{
struct device *dev = &vcodec_dev->plat_dev->dev;
/* Need to add pending data at the end of bitstream when bs_sz is small than
* 20 bytes for cavlc bitstream, or lat will decode fail. This pending data is
* useful for mt8192 and mt8195 platform.
*
* cavlc bitstream when entropy_coding_mode_flag is false.
*/
if (pps->entropy_coding_mode_flag || *bs_size > 20 ||
!(of_device_is_compatible(dev->of_node, "mediatek,mt8192-vcodec-dec") ||
of_device_is_compatible(dev->of_node, "mediatek,mt8195-vcodec-dec")))
return;
buf[*bs_size] = 0;
buf[*bs_size + 1] = 0;
buf[*bs_size + 2] = 1;
buf[*bs_size + 3] = 0xff;
(*bs_size) += 4;
}
static int vdec_h264_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem *bs,
struct vdec_fb *fb, bool *res_chg)
{
@ -582,9 +605,6 @@ static int vdec_h264_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem *bs,
}
inst->vsi->dec.nal_info = buf[nal_start_idx];
inst->vsi->dec.bs_buf_addr = (u64)bs->dma_addr;
inst->vsi->dec.bs_buf_size = bs->size;
lat_buf->src_buf_req = src_buf_info->m2m_buf.vb.vb2_buf.req_obj.req;
v4l2_m2m_buf_copy_metadata(&src_buf_info->m2m_buf.vb, &lat_buf->ts_info, true);
@ -592,6 +612,12 @@ static int vdec_h264_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem *bs,
if (err)
goto err_free_fb_out;
vdec_h264_insert_startcode(inst->ctx->dev, buf, &bs->size,
&share_info->h264_slice_params.pps);
inst->vsi->dec.bs_buf_addr = (uint64_t)bs->dma_addr;
inst->vsi->dec.bs_buf_size = bs->size;
*res_chg = inst->resolution_changed;
if (inst->resolution_changed) {
mtk_vcodec_debug(inst, "- resolution changed -");

2
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c
View File

@ -2431,6 +2431,8 @@ static int mxc_jpeg_probe(struct platform_device *pdev)
unsigned int slot;
of_id = of_match_node(mxc_jpeg_match, dev->of_node);
if (!of_id)
return -ENODEV;
mode = *(const int *)of_id->data;
jpeg = devm_kzalloc(dev, sizeof(struct mxc_jpeg_dev), GFP_KERNEL);

4
drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c
View File

@ -1047,10 +1047,10 @@ static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
int ret;
if (offset < DST_QUEUE_OFF_BASE) {
mfc_debug(2, "mmaping source\n");
mfc_debug(2, "mmapping source\n");
ret = vb2_mmap(&ctx->vq_src, vma);
} else { /* capture */
mfc_debug(2, "mmaping destination\n");
mfc_debug(2, "mmapping destination\n");
vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
ret = vb2_mmap(&ctx->vq_dst, vma);
}

8
drivers/media/platform/st/sti/c8sectpfe/c8sectpfe-core.c
View File

@ -24,16 +24,18 @@
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include <linux/usb.h>
#include <linux/slab.h>
#include <linux/time.h>
#include <linux/usb.h>
#include <linux/wait.h>
#include <linux/pinctrl/pinctrl.h>
#include "c8sectpfe-core.h"
#include "c8sectpfe-common.h"
#include "c8sectpfe-core.h"
#include "c8sectpfe-debugfs.h"
#include <media/dmxdev.h>
#include <media/dvb_demux.h>
#include <media/dvb_frontend.h>

4
drivers/media/platform/st/stm32/stm32-dcmi.c
View File

@ -1997,10 +1997,8 @@ static int dcmi_probe(struct platform_device *pdev)
}
dcmi->regs = devm_ioremap_resource(&pdev->dev, dcmi->res);
if (IS_ERR(dcmi->regs)) {
dev_err(&pdev->dev, "Could not map registers\n");
if (IS_ERR(dcmi->regs))
return PTR_ERR(dcmi->regs);
}
mclk = devm_clk_get(&pdev->dev, "mclk");
if (IS_ERR(mclk)) {

3
drivers/media/radio/radio-terratec.c
View File

@ -82,7 +82,6 @@ static int terratec_s_mute_volume(struct radio_isa_card *isa, bool mute, int vol
static int terratec_s_frequency(struct radio_isa_card *isa, u32 freq)
{
int i;
int p;
int temp;
long rest;
unsigned char buffer[25]; /* we have to bit shift 25 registers */
@ -93,7 +92,6 @@ static int terratec_s_frequency(struct radio_isa_card *isa, u32 freq)
rest = freq * 10 + 10700; /* I once had understood what is going on here */
/* maybe some wise guy (friedhelm?) can comment this stuff */
i = 13;
p = 10;
temp = 102400;
while (rest != 0) {
if (rest % temp == rest)
@ -103,7 +101,6 @@ static int terratec_s_frequency(struct radio_isa_card *isa, u32 freq)
rest = rest - temp;
}
i--;
p--;
temp = temp / 2;
}

28
drivers/media/test-drivers/vivid/vivid-ctrls.c
View File

@ -36,6 +36,8 @@
#define VIVID_CID_RO_INTEGER (VIVID_CID_CUSTOM_BASE + 12)
#define VIVID_CID_U32_DYN_ARRAY (VIVID_CID_CUSTOM_BASE + 13)
#define VIVID_CID_U8_PIXEL_ARRAY (VIVID_CID_CUSTOM_BASE + 14)
#define VIVID_CID_S32_ARRAY (VIVID_CID_CUSTOM_BASE + 15)
#define VIVID_CID_S64_ARRAY (VIVID_CID_CUSTOM_BASE + 16)
#define VIVID_CID_VIVID_BASE (0x00f00000 | 0xf000)
#define VIVID_CID_VIVID_CLASS (0x00f00000 | 1)
@ -241,6 +243,30 @@ static const struct v4l2_ctrl_config vivid_ctrl_u8_pixel_array = {
.dims = { 640 / PIXEL_ARRAY_DIV, 360 / PIXEL_ARRAY_DIV },
};
static const struct v4l2_ctrl_config vivid_ctrl_s32_array = {
.ops = &vivid_user_gen_ctrl_ops,
.id = VIVID_CID_S32_ARRAY,
.name = "S32 2 Element Array",
.type = V4L2_CTRL_TYPE_INTEGER,
.def = 2,
.min = -10,
.max = 10,
.step = 1,
.dims = { 2 },
};
static const struct v4l2_ctrl_config vivid_ctrl_s64_array = {
.ops = &vivid_user_gen_ctrl_ops,
.id = VIVID_CID_S64_ARRAY,
.name = "S64 5 Element Array",
.type = V4L2_CTRL_TYPE_INTEGER64,
.def = 4,
.min = -10,
.max = 10,
.step = 1,
.dims = { 5 },
};
static const char * const vivid_ctrl_menu_strings[] = {
"Menu Item 0 (Skipped)",
"Menu Item 1",
@ -1656,6 +1682,8 @@ int vivid_create_controls(struct vivid_dev *dev, bool show_ccs_cap,
v4l2_ctrl_new_custom(hdl_user_gen, &vivid_ctrl_u16_matrix, NULL);
v4l2_ctrl_new_custom(hdl_user_gen, &vivid_ctrl_u8_4d_array, NULL);
dev->pixel_array = v4l2_ctrl_new_custom(hdl_user_gen, &vivid_ctrl_u8_pixel_array, NULL);
v4l2_ctrl_new_custom(hdl_user_gen, &vivid_ctrl_s32_array, NULL);
v4l2_ctrl_new_custom(hdl_user_gen, &vivid_ctrl_s64_array, NULL);
if (dev->has_vid_cap) {
/* Image Processing Controls */

1
drivers/media/test-drivers/vivid/vivid-vbi-gen.c
View File

@ -194,7 +194,6 @@ static void vivid_vbi_gen_set_time_of_day(u8 *packet)
for (checksum = i = 0; i <= 8; i++)
checksum += packet[i] & 0x7f;
packet[9] = calc_parity(0x100 - checksum);
checksum = 0;
packet[10] = calc_parity(0x07);
packet[11] = calc_parity(0x04);
if (sys_tz.tz_minuteswest >= 0)

2
drivers/media/tuners/mxl5005s.c
View File

@ -3637,7 +3637,7 @@ static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
u16 status = 0;
int i;
u8 RegAddr[] = {43, 136};
static const u8 RegAddr[] = {43, 136};
*count = ARRAY_SIZE(RegAddr);

2
drivers/media/v4l2-core/v4l2-ctrls-core.c
View File

@ -1827,7 +1827,7 @@ struct v4l2_ctrl *v4l2_ctrl_new_std_menu(struct v4l2_ctrl_handler *hdl,
else if (type == V4L2_CTRL_TYPE_INTEGER_MENU)
qmenu_int = v4l2_ctrl_get_int_menu(id, &qmenu_int_len);
if ((!qmenu && !qmenu_int) || (qmenu_int && max > qmenu_int_len)) {
if ((!qmenu && !qmenu_int) || (qmenu_int && max >= qmenu_int_len)) {
handler_set_err(hdl, -EINVAL);
return NULL;
}

34
drivers/media/v4l2-core/v4l2-ioctl.c
View File

@ -1347,23 +1347,23 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
case V4L2_PIX_FMT_YUV420: descr = "Planar YUV 4:2:0"; break;
case V4L2_PIX_FMT_HI240: descr = "8-bit Dithered RGB (BTTV)"; break;
case V4L2_PIX_FMT_M420: descr = "YUV 4:2:0 (M420)"; break;
case V4L2_PIX_FMT_NV12: descr = "Y/CbCr 4:2:0"; break;
case V4L2_PIX_FMT_NV21: descr = "Y/CrCb 4:2:0"; break;
case V4L2_PIX_FMT_NV16: descr = "Y/CbCr 4:2:2"; break;
case V4L2_PIX_FMT_NV61: descr = "Y/CrCb 4:2:2"; break;
case V4L2_PIX_FMT_NV24: descr = "Y/CbCr 4:4:4"; break;
case V4L2_PIX_FMT_NV42: descr = "Y/CrCb 4:4:4"; break;
case V4L2_PIX_FMT_P010: descr = "10-bit Y/CbCr 4:2:0"; break;
case V4L2_PIX_FMT_NV12_4L4: descr = "Y/CbCr 4:2:0 (4x4 Linear)"; break;
case V4L2_PIX_FMT_NV12_16L16: descr = "Y/CbCr 4:2:0 (16x16 Linear)"; break;
case V4L2_PIX_FMT_NV12_32L32: descr = "Y/CbCr 4:2:0 (32x32 Linear)"; break;
case V4L2_PIX_FMT_P010_4L4: descr = "10-bit Y/CbCr 4:2:0 (4x4 Linear)"; break;
case V4L2_PIX_FMT_NV12M: descr = "Y/CbCr 4:2:0 (N-C)"; break;
case V4L2_PIX_FMT_NV21M: descr = "Y/CrCb 4:2:0 (N-C)"; break;
case V4L2_PIX_FMT_NV16M: descr = "Y/CbCr 4:2:2 (N-C)"; break;
case V4L2_PIX_FMT_NV61M: descr = "Y/CrCb 4:2:2 (N-C)"; break;
case V4L2_PIX_FMT_NV12MT: descr = "Y/CbCr 4:2:0 (64x32 MB, N-C)"; break;
case V4L2_PIX_FMT_NV12MT_16X16: descr = "Y/CbCr 4:2:0 (16x16 MB, N-C)"; break;
case V4L2_PIX_FMT_NV12: descr = "Y/UV 4:2:0"; break;
case V4L2_PIX_FMT_NV21: descr = "Y/VU 4:2:0"; break;
case V4L2_PIX_FMT_NV16: descr = "Y/UV 4:2:2"; break;
case V4L2_PIX_FMT_NV61: descr = "Y/VU 4:2:2"; break;
case V4L2_PIX_FMT_NV24: descr = "Y/UV 4:4:4"; break;
case V4L2_PIX_FMT_NV42: descr = "Y/VU 4:4:4"; break;
case V4L2_PIX_FMT_P010: descr = "10-bit Y/UV 4:2:0"; break;
case V4L2_PIX_FMT_NV12_4L4: descr = "Y/UV 4:2:0 (4x4 Linear)"; break;
case V4L2_PIX_FMT_NV12_16L16: descr = "Y/UV 4:2:0 (16x16 Linear)"; break;
case V4L2_PIX_FMT_NV12_32L32: descr = "Y/UV 4:2:0 (32x32 Linear)"; break;
case V4L2_PIX_FMT_P010_4L4: descr = "10-bit Y/UV 4:2:0 (4x4 Linear)"; break;
case V4L2_PIX_FMT_NV12M: descr = "Y/UV 4:2:0 (N-C)"; break;
case V4L2_PIX_FMT_NV21M: descr = "Y/VU 4:2:0 (N-C)"; break;
case V4L2_PIX_FMT_NV16M: descr = "Y/UV 4:2:2 (N-C)"; break;
case V4L2_PIX_FMT_NV61M: descr = "Y/VU 4:2:2 (N-C)"; break;
case V4L2_PIX_FMT_NV12MT: descr = "Y/UV 4:2:0 (64x32 MB, N-C)"; break;
case V4L2_PIX_FMT_NV12MT_16X16: descr = "Y/UV 4:2:0 (16x16 MB, N-C)"; break;
case V4L2_PIX_FMT_YUV420M: descr = "Planar YUV 4:2:0 (N-C)"; break;
case V4L2_PIX_FMT_YVU420M: descr = "Planar YVU 4:2:0 (N-C)"; break;
case V4L2_PIX_FMT_YUV422M: descr = "Planar YUV 4:2:2 (N-C)"; break;

12
drivers/staging/media/atomisp/pci/atomisp_cmd.c
View File

@ -3288,7 +3288,7 @@ int atomisp_css_cp_dvs2_coefs(struct atomisp_sub_device *asd,
if (!IS_ISP2401) {
if (sizeof(*cur) != sizeof(coefs->grid) ||
memcmp(&coefs->grid, cur, sizeof(coefs->grid))) {
dev_err(asd->isp->dev, "dvs grid mis-match!\n");
dev_err(asd->isp->dev, "dvs grid mismatch!\n");
/* If the grid info in the argument differs from the current
grid info, we tell the caller to reset the grid size and
try again. */
@ -3344,7 +3344,7 @@ int atomisp_css_cp_dvs2_coefs(struct atomisp_sub_device *asd,
if (sizeof(*cur) != sizeof(dvs2_coefs.grid) ||
memcmp(&dvs2_coefs.grid, cur, sizeof(dvs2_coefs.grid))) {
dev_err(asd->isp->dev, "dvs grid mis-match!\n");
dev_err(asd->isp->dev, "dvs grid mismatch!\n");
/* If the grid info in the argument differs from the current
grid info, we tell the caller to reset the grid size and
try again. */
@ -3692,14 +3692,14 @@ void atomisp_handle_parameter_and_buffer(struct atomisp_video_pipe *pipe)
unsigned long irqflags;
bool need_to_enqueue_buffer = false;
lockdep_assert_held(&asd->isp->mutex);
if (!asd) {
dev_err(pipe->isp->dev, "%s(): asd is NULL, device is %s\n",
__func__, pipe->vdev.name);
return;
}
lockdep_assert_held(&asd->isp->mutex);
if (atomisp_is_vf_pipe(pipe))
return;
@ -3774,14 +3774,14 @@ int atomisp_set_parameters(struct video_device *vdev,
struct atomisp_css_params *css_param = &asd->params.css_param;
int ret;
lockdep_assert_held(&asd->isp->mutex);
if (!asd) {
dev_err(pipe->isp->dev, "%s(): asd is NULL, device is %s\n",
__func__, vdev->name);
return -EINVAL;
}
lockdep_assert_held(&asd->isp->mutex);
if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) {
dev_err(asd->isp->dev, "%s: internal error!\n", __func__);
return -EINVAL;

2
drivers/staging/media/atomisp/pci/atomisp_compat_css20.c
View File

@ -3180,7 +3180,7 @@ static int atomisp_compare_dvs_grid(struct atomisp_sub_device *asd,
}
if (sizeof(*cur) != sizeof(*atomgrid)) {
dev_err(asd->isp->dev, "dvs grid mis-match!\n");
dev_err(asd->isp->dev, "dvs grid mismatch!\n");
return -EINVAL;
}

2
drivers/staging/media/atomisp/pci/css_2401_system/host/pixelgen_private.h
View File

@ -161,7 +161,7 @@ STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_dump_state(
state->syng_stat_fcnt);
ia_css_print("Pixel Generator ID %d syng stat done 0x%x\n", ID,
state->syng_stat_done);
ia_css_print("Pixel Generator ID %d tpg modee 0x%x\n", ID, state->tpg_mode);
ia_css_print("Pixel Generator ID %d tpg mode 0x%x\n", ID, state->tpg_mode);
ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x\n", ID,
state->tpg_hcnt_mask);
ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x\n", ID,

3
drivers/staging/media/meson/vdec/codec_vp9.c
View File

@ -1649,8 +1649,7 @@ static void adapt_coef_probs(int prev_kf, int cur_kf, int pre_fc,
else if (coef_count_node_start ==
VP9_MV_BITS_1_COUNT_START)
coef_node_start = VP9_MV_BITS_1_START;
else if (coef_count_node_start ==
VP9_MV_CLASS0_HP_0_COUNT_START)
else /* node_start == VP9_MV_CLASS0_HP_0_COUNT_START */
coef_node_start = VP9_MV_CLASS0_HP_0_START;
den = count[coef_count_node_start] +

16
drivers/staging/media/sunxi/cedrus/cedrus.h
View File

@ -100,7 +100,15 @@ struct cedrus_buffer {
struct {
unsigned int position;
enum cedrus_h264_pic_type pic_type;
void *mv_col_buf;
dma_addr_t mv_col_buf_dma;
ssize_t mv_col_buf_size;
} h264;
struct {
void *mv_col_buf;
dma_addr_t mv_col_buf_dma;
ssize_t mv_col_buf_size;
} h265;
} codec;
};
@ -117,10 +125,6 @@ struct cedrus_ctx {
union {
struct {
void *mv_col_buf;
dma_addr_t mv_col_buf_dma;
ssize_t mv_col_buf_field_size;
ssize_t mv_col_buf_size;
void *pic_info_buf;
dma_addr_t pic_info_buf_dma;
ssize_t pic_info_buf_size;
@ -134,10 +138,6 @@ struct cedrus_ctx {
ssize_t intra_pred_buf_size;
} h264;
struct {
void *mv_col_buf;
dma_addr_t mv_col_buf_addr;
ssize_t mv_col_buf_size;
ssize_t mv_col_buf_unit_size;
void *neighbor_info_buf;
dma_addr_t neighbor_info_buf_addr;
void *entry_points_buf;

118
drivers/staging/media/sunxi/cedrus/cedrus_h264.c
View File

@ -54,17 +54,13 @@ static void cedrus_h264_write_sram(struct cedrus_dev *dev,
cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, *buffer++);
}
static dma_addr_t cedrus_h264_mv_col_buf_addr(struct cedrus_ctx *ctx,
unsigned int position,
static dma_addr_t cedrus_h264_mv_col_buf_addr(struct cedrus_buffer *buf,
unsigned int field)
{
dma_addr_t addr = ctx->codec.h264.mv_col_buf_dma;
/* Adjust for the position */
addr += position * ctx->codec.h264.mv_col_buf_field_size * 2;
dma_addr_t addr = buf->codec.h264.mv_col_buf_dma;
/* Adjust for the field */
addr += field * ctx->codec.h264.mv_col_buf_field_size;
addr += field * buf->codec.h264.mv_col_buf_size / 2;
return addr;
}
@ -76,7 +72,6 @@ static void cedrus_fill_ref_pic(struct cedrus_ctx *ctx,
struct cedrus_h264_sram_ref_pic *pic)
{
struct vb2_buffer *vbuf = &buf->m2m_buf.vb.vb2_buf;
unsigned int position = buf->codec.h264.position;
pic->top_field_order_cnt = cpu_to_le32(top_field_order_cnt);
pic->bottom_field_order_cnt = cpu_to_le32(bottom_field_order_cnt);
@ -84,14 +79,12 @@ static void cedrus_fill_ref_pic(struct cedrus_ctx *ctx,
pic->luma_ptr = cpu_to_le32(cedrus_buf_addr(vbuf, &ctx->dst_fmt, 0));
pic->chroma_ptr = cpu_to_le32(cedrus_buf_addr(vbuf, &ctx->dst_fmt, 1));
pic->mv_col_top_ptr =
cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, position, 0));
pic->mv_col_bot_ptr =
cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, position, 1));
pic->mv_col_top_ptr = cpu_to_le32(cedrus_h264_mv_col_buf_addr(buf, 0));
pic->mv_col_bot_ptr = cpu_to_le32(cedrus_h264_mv_col_buf_addr(buf, 1));
}
static void cedrus_write_frame_list(struct cedrus_ctx *ctx,
struct cedrus_run *run)
static int cedrus_write_frame_list(struct cedrus_ctx *ctx,
struct cedrus_run *run)
{
struct cedrus_h264_sram_ref_pic pic_list[CEDRUS_H264_FRAME_NUM];
const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params;
@ -146,6 +139,31 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx,
output_buf = vb2_to_cedrus_buffer(&run->dst->vb2_buf);
output_buf->codec.h264.position = position;
if (!output_buf->codec.h264.mv_col_buf_size) {
const struct v4l2_ctrl_h264_sps *sps = run->h264.sps;
unsigned int field_size;
field_size = DIV_ROUND_UP(ctx->src_fmt.width, 16) *
DIV_ROUND_UP(ctx->src_fmt.height, 16) * 16;
if (!(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE))
field_size = field_size * 2;
if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY))
field_size = field_size * 2;
output_buf->codec.h264.mv_col_buf_size = field_size * 2;
/* Buffer is never accessed by CPU, so we can skip kernel mapping. */
output_buf->codec.h264.mv_col_buf =
dma_alloc_attrs(dev->dev,
output_buf->codec.h264.mv_col_buf_size,
&output_buf->codec.h264.mv_col_buf_dma,
GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING);
if (!output_buf->codec.h264.mv_col_buf) {
output_buf->codec.h264.mv_col_buf_size = 0;
return -ENOMEM;
}
}
if (decode->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC)
output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FIELD;
else if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)
@ -162,6 +180,8 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx,
pic_list, sizeof(pic_list));
cedrus_write(dev, VE_H264_OUTPUT_FRAME_IDX, position);
return 0;
}
#define CEDRUS_MAX_REF_IDX 32
@ -496,6 +516,7 @@ static void cedrus_h264_irq_disable(struct cedrus_ctx *ctx)
static int cedrus_h264_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
{
struct cedrus_dev *dev = ctx->dev;
int ret;
cedrus_engine_enable(ctx);
@ -506,7 +527,9 @@ static int cedrus_h264_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
ctx->codec.h264.neighbor_info_buf_dma);
cedrus_write_scaling_lists(ctx, run);
cedrus_write_frame_list(ctx, run);
ret = cedrus_write_frame_list(ctx, run);
if (ret)
return ret;
cedrus_set_params(ctx, run);
@ -517,8 +540,6 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
unsigned int pic_info_size;
unsigned int field_size;
unsigned int mv_col_size;
int ret;
/*
@ -566,38 +587,6 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx)
goto err_pic_buf;
}
field_size = DIV_ROUND_UP(ctx->src_fmt.width, 16) *
DIV_ROUND_UP(ctx->src_fmt.height, 16) * 16;
/*
* FIXME: This is actually conditional to
* V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE not being set, we
* might have to rework this if memory efficiency ever is
* something we need to work on.
*/
field_size = field_size * 2;
/*
* FIXME: This is actually conditional to
* V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY not being set, we might
* have to rework this if memory efficiency ever is something
* we need to work on.
*/
field_size = field_size * 2;
ctx->codec.h264.mv_col_buf_field_size = field_size;
mv_col_size = field_size * 2 * CEDRUS_H264_FRAME_NUM;
ctx->codec.h264.mv_col_buf_size = mv_col_size;
ctx->codec.h264.mv_col_buf =
dma_alloc_attrs(dev->dev,
ctx->codec.h264.mv_col_buf_size,
&ctx->codec.h264.mv_col_buf_dma,
GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING);
if (!ctx->codec.h264.mv_col_buf) {
ret = -ENOMEM;
goto err_neighbor_buf;
}
if (ctx->src_fmt.width > 2048) {
/*
* Formulas for deblock and intra prediction buffer sizes
@ -613,7 +602,7 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx)
GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING);
if (!ctx->codec.h264.deblk_buf) {
ret = -ENOMEM;
goto err_mv_col_buf;
goto err_neighbor_buf;
}
/*
@ -641,12 +630,6 @@ err_deblk_buf:
ctx->codec.h264.deblk_buf_dma,
DMA_ATTR_NO_KERNEL_MAPPING);
err_mv_col_buf:
dma_free_attrs(dev->dev, ctx->codec.h264.mv_col_buf_size,
ctx->codec.h264.mv_col_buf,
ctx->codec.h264.mv_col_buf_dma,
DMA_ATTR_NO_KERNEL_MAPPING);
err_neighbor_buf:
dma_free_attrs(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE,
ctx->codec.h264.neighbor_info_buf,
@ -664,11 +647,26 @@ err_pic_buf:
static void cedrus_h264_stop(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
struct cedrus_buffer *buf;
struct vb2_queue *vq;
unsigned int i;
vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
for (i = 0; i < vq->num_buffers; i++) {
buf = vb2_to_cedrus_buffer(vb2_get_buffer(vq, i));
if (buf->codec.h264.mv_col_buf_size > 0) {
dma_free_attrs(dev->dev,
buf->codec.h264.mv_col_buf_size,
buf->codec.h264.mv_col_buf,
buf->codec.h264.mv_col_buf_dma,
DMA_ATTR_NO_KERNEL_MAPPING);
buf->codec.h264.mv_col_buf_size = 0;
}
}
dma_free_attrs(dev->dev, ctx->codec.h264.mv_col_buf_size,
ctx->codec.h264.mv_col_buf,
ctx->codec.h264.mv_col_buf_dma,
DMA_ATTR_NO_KERNEL_MAPPING);
dma_free_attrs(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE,
ctx->codec.h264.neighbor_info_buf,
ctx->codec.h264.neighbor_info_buf_dma,

88
drivers/staging/media/sunxi/cedrus/cedrus_h265.c
View File

@ -90,12 +90,13 @@ static void cedrus_h265_sram_write_data(struct cedrus_dev *dev, void *data,
}
static inline dma_addr_t
cedrus_h265_frame_info_mv_col_buf_addr(struct cedrus_ctx *ctx,
unsigned int index, unsigned int field)
cedrus_h265_frame_info_mv_col_buf_addr(struct vb2_buffer *buf,
unsigned int field)
{
return ctx->codec.h265.mv_col_buf_addr + index *
ctx->codec.h265.mv_col_buf_unit_size +
field * ctx->codec.h265.mv_col_buf_unit_size / 2;
struct cedrus_buffer *cedrus_buf = vb2_to_cedrus_buffer(buf);
return cedrus_buf->codec.h265.mv_col_buf_dma +
field * cedrus_buf->codec.h265.mv_col_buf_size / 2;
}
static void cedrus_h265_frame_info_write_single(struct cedrus_ctx *ctx,
@ -108,9 +109,8 @@ static void cedrus_h265_frame_info_write_single(struct cedrus_ctx *ctx,
dma_addr_t dst_luma_addr = cedrus_dst_buf_addr(ctx, buf, 0);
dma_addr_t dst_chroma_addr = cedrus_dst_buf_addr(ctx, buf, 1);
dma_addr_t mv_col_buf_addr[2] = {
cedrus_h265_frame_info_mv_col_buf_addr(ctx, buf->index, 0),
cedrus_h265_frame_info_mv_col_buf_addr(ctx, buf->index,
field_pic ? 1 : 0)
cedrus_h265_frame_info_mv_col_buf_addr(buf, 0),
cedrus_h265_frame_info_mv_col_buf_addr(buf, field_pic ? 1 : 0)
};
u32 offset = VE_DEC_H265_SRAM_OFFSET_FRAME_INFO +
VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT * index;
@ -242,6 +242,18 @@ static void cedrus_h265_skip_bits(struct cedrus_dev *dev, int num)
}
}
static u32 cedrus_h265_show_bits(struct cedrus_dev *dev, int num)
{
cedrus_write(dev, VE_DEC_H265_TRIGGER,
VE_DEC_H265_TRIGGER_SHOW_BITS |
VE_DEC_H265_TRIGGER_TYPE_N_BITS(num));
cedrus_wait_for(dev, VE_DEC_H265_STATUS,
VE_DEC_H265_STATUS_VLD_BUSY);
return cedrus_read(dev, VE_DEC_H265_BITS_READ);
}
static void cedrus_h265_write_scaling_list(struct cedrus_ctx *ctx,
struct cedrus_run *run)
{
@ -400,13 +412,14 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
unsigned int width_in_ctb_luma, ctb_size_luma;
unsigned int log2_max_luma_coding_block_size;
unsigned int ctb_addr_x, ctb_addr_y;
struct cedrus_buffer *cedrus_buf;
dma_addr_t src_buf_addr;
dma_addr_t src_buf_end_addr;
u32 chroma_log2_weight_denom;
u32 num_entry_point_offsets;
u32 output_pic_list_index;
u32 pic_order_cnt[2];
u8 *padding;
u8 padding;
int count;
u32 reg;
@ -416,6 +429,7 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
decode_params = run->h265.decode_params;
pred_weight_table = &slice_params->pred_weight_table;
num_entry_point_offsets = slice_params->num_entry_point_offsets;
cedrus_buf = vb2_to_cedrus_buffer(&run->dst->vb2_buf);
/*
* If entry points offsets are present, we should get them
@ -433,31 +447,25 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
DIV_ROUND_UP(sps->pic_width_in_luma_samples, ctb_size_luma);
/* MV column buffer size and allocation. */
if (!ctx->codec.h265.mv_col_buf_size) {
unsigned int num_buffers =
run->dst->vb2_buf.vb2_queue->num_buffers;
if (!cedrus_buf->codec.h265.mv_col_buf_size) {
/*
* Each CTB requires a MV col buffer with a specific unit size.
* Since the address is given with missing lsb bits, 1 KiB is
* added to each buffer to ensure proper alignment.
*/
ctx->codec.h265.mv_col_buf_unit_size =
cedrus_buf->codec.h265.mv_col_buf_size =
DIV_ROUND_UP(ctx->src_fmt.width, ctb_size_luma) *
DIV_ROUND_UP(ctx->src_fmt.height, ctb_size_luma) *
CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE + SZ_1K;
ctx->codec.h265.mv_col_buf_size = num_buffers *
ctx->codec.h265.mv_col_buf_unit_size;
/* Buffer is never accessed by CPU, so we can skip kernel mapping. */
ctx->codec.h265.mv_col_buf =
cedrus_buf->codec.h265.mv_col_buf =
dma_alloc_attrs(dev->dev,
ctx->codec.h265.mv_col_buf_size,
&ctx->codec.h265.mv_col_buf_addr,
cedrus_buf->codec.h265.mv_col_buf_size,
&cedrus_buf->codec.h265.mv_col_buf_dma,
GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING);
if (!ctx->codec.h265.mv_col_buf) {
ctx->codec.h265.mv_col_buf_size = 0;
if (!cedrus_buf->codec.h265.mv_col_buf) {
cedrus_buf->codec.h265.mv_col_buf_size = 0;
return -ENOMEM;
}
}
@ -520,21 +528,22 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
if (slice_params->data_byte_offset == 0)
return -EOPNOTSUPP;
padding = (u8 *)vb2_plane_vaddr(&run->src->vb2_buf, 0) +
slice_params->data_byte_offset - 1;
cedrus_h265_skip_bits(dev, (slice_params->data_byte_offset - 1) * 8);
padding = cedrus_h265_show_bits(dev, 8);
/* at least one bit must be set in that byte */
if (*padding == 0)
if (padding == 0)
return -EINVAL;
for (count = 0; count < 8; count++)
if (*padding & (1 << count))
if (padding & (1 << count))
break;
/* Include the one bit. */
count++;
cedrus_h265_skip_bits(dev, slice_params->data_byte_offset * 8 - count);
cedrus_h265_skip_bits(dev, 8 - count);
/* Bitstream parameters. */
@ -803,9 +812,6 @@ static int cedrus_h265_start(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
/* The buffer size is calculated at setup time. */
ctx->codec.h265.mv_col_buf_size = 0;
/* Buffer is never accessed by CPU, so we can skip kernel mapping. */
ctx->codec.h265.neighbor_info_buf =
dma_alloc_attrs(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE,
@ -832,14 +838,24 @@ static int cedrus_h265_start(struct cedrus_ctx *ctx)
static void cedrus_h265_stop(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
struct cedrus_buffer *buf;
struct vb2_queue *vq;
unsigned int i;
if (ctx->codec.h265.mv_col_buf_size > 0) {
dma_free_attrs(dev->dev, ctx->codec.h265.mv_col_buf_size,
ctx->codec.h265.mv_col_buf,
ctx->codec.h265.mv_col_buf_addr,
DMA_ATTR_NO_KERNEL_MAPPING);
vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
ctx->codec.h265.mv_col_buf_size = 0;
for (i = 0; i < vq->num_buffers; i++) {
buf = vb2_to_cedrus_buffer(vb2_get_buffer(vq, i));
if (buf->codec.h265.mv_col_buf_size > 0) {
dma_free_attrs(dev->dev,
buf->codec.h265.mv_col_buf_size,
buf->codec.h265.mv_col_buf,
buf->codec.h265.mv_col_buf_dma,
DMA_ATTR_NO_KERNEL_MAPPING);
buf->codec.h265.mv_col_buf_size = 0;
}
}
dma_free_attrs(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE,

2
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
View File

@ -505,6 +505,8 @@
#define VE_DEC_H265_LOW_ADDR_ENTRY_POINTS_BUF(a) \
SHIFT_AND_MASK_BITS(a, 7, 0)
#define VE_DEC_H265_BITS_READ (VE_ENGINE_DEC_H265 + 0xdc)
#define VE_DEC_H265_SRAM_OFFSET (VE_ENGINE_DEC_H265 + 0xe0)
#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0 0x00

2
include/uapi/linux/videodev2.h
View File

@ -1781,6 +1781,8 @@ struct v4l2_ext_control {
__u8 __user *p_u8;
__u16 __user *p_u16;
__u32 __user *p_u32;
__u32 __user *p_s32;
__u32 __user *p_s64;
struct v4l2_area __user *p_area;
struct v4l2_ctrl_h264_sps __user *p_h264_sps;
struct v4l2_ctrl_h264_pps *p_h264_pps;