phy: rockchip: naneng-combphy: Add RK3528 support
Rockchip RK3528 integrates one naneng-combphy that is able to operate in PCIe and USB3 mode. The control logic is similar to previous variants of naneng-combphy but the register layout is apparently different from the RK3568 one. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250728102947.38984-7-ziyao@disroot.org Signed-off-by: Vinod Koul <vkoul@kernel.org>pull/1354/merge
Yao Zi
Vinod Koul
parent
b3bbc6afcf
commit
bbcca4fac8
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@ -20,7 +20,46 @@
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#define REF_CLOCK_25MHz (25 * HZ_PER_MHZ)
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#define REF_CLOCK_100MHz (100 * HZ_PER_MHZ)
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/* COMBO PHY REG */
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/* RK3528 COMBO PHY REG */
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#define RK3528_PHYREG6 0x18
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#define RK3528_PHYREG6_PLL_KVCO GENMASK(12, 10)
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#define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2
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#define RK3528_PHYREG6_SSC_DIR GENMASK(5, 4)
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#define RK3528_PHYREG6_SSC_UPWARD 0
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#define RK3528_PHYREG6_SSC_DOWNWARD 1
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#define RK3528_PHYREG40 0x100
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#define RK3528_PHYREG40_SSC_EN BIT(20)
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#define RK3528_PHYREG40_SSC_CNT GENMASK(10, 0)
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#define RK3528_PHYREG40_SSC_CNT_VALUE 0x17d
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#define RK3528_PHYREG42 0x108
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#define RK3528_PHYREG42_CKDRV_CLK_SEL BIT(29)
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#define RK3528_PHYREG42_CKDRV_CLK_PLL 0
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#define RK3528_PHYREG42_CKDRV_CLK_CKRCV 1
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#define RK3528_PHYREG42_PLL_LPF_R1_ADJ GENMASK(10, 7)
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#define RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE 0x9
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#define RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ GENMASK(6, 4)
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#define RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE 0x7
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#define RK3528_PHYREG42_PLL_KVCO_ADJ GENMASK(2, 0)
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#define RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE 0x0
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#define RK3528_PHYREG80 0x200
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#define RK3528_PHYREG80_CTLE_EN BIT(17)
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#define RK3528_PHYREG81 0x204
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#define RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X BIT(5)
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#define RK3528_PHYREG81_SLEW_RATE_CTRL GENMASK(2, 0)
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#define RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW 0x7
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#define RK3528_PHYREG83 0x20c
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#define RK3528_PHYREG83_RX_SQUELCH GENMASK(2, 0)
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#define RK3528_PHYREG83_RX_SQUELCH_VALUE 0x6
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#define RK3528_PHYREG86 0x218
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#define RK3528_PHYREG86_RTERM_DET_CLK_EN BIT(14)
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/* RK3568 COMBO PHY REG */
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#define RK3568_PHYREG6 0x14
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#define RK3568_PHYREG6_PLL_DIV_MASK GENMASK(7, 6)
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#define RK3568_PHYREG6_PLL_DIV_SHIFT 6
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@ -400,6 +439,150 @@ static int rockchip_combphy_probe(struct platform_device *pdev)
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
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{
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const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
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unsigned long rate;
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u32 val;
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/* Set SSC downward spread spectrum */
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val = FIELD_PREP(RK3528_PHYREG6_SSC_DIR, RK3528_PHYREG6_SSC_DOWNWARD);
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rockchip_combphy_updatel(priv, RK3528_PHYREG6_SSC_DIR, val, RK3528_PHYREG6);
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switch (priv->type) {
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case PHY_TYPE_PCIE:
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rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
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break;
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case PHY_TYPE_USB3:
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/* Enable adaptive CTLE for USB3.0 Rx */
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rockchip_combphy_updatel(priv, RK3528_PHYREG80_CTLE_EN, RK3528_PHYREG80_CTLE_EN,
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RK3528_PHYREG80);
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/* Set slow slew rate control for PI */
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val = FIELD_PREP(RK3528_PHYREG81_SLEW_RATE_CTRL,
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RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW);
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rockchip_combphy_updatel(priv, RK3528_PHYREG81_SLEW_RATE_CTRL, val,
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RK3528_PHYREG81);
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/* Set CDR phase path with 2x gain */
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rockchip_combphy_updatel(priv, RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X,
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RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X, RK3528_PHYREG81);
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/* Set Rx squelch input filler bandwidth */
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val = FIELD_PREP(RK3528_PHYREG83_RX_SQUELCH, RK3528_PHYREG83_RX_SQUELCH_VALUE);
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rockchip_combphy_updatel(priv, RK3528_PHYREG83_RX_SQUELCH, val, RK3528_PHYREG83);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
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rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true);
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break;
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default:
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dev_err(priv->dev, "incompatible PHY type\n");
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return -EINVAL;
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}
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rate = clk_get_rate(priv->refclk);
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switch (rate) {
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case REF_CLOCK_24MHz:
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rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
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if (priv->type == PHY_TYPE_USB3) {
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/* Set ssc_cnt[10:0]=00101111101 & 31.5KHz */
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val = FIELD_PREP(RK3528_PHYREG40_SSC_CNT, RK3528_PHYREG40_SSC_CNT_VALUE);
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rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_CNT, val,
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RK3528_PHYREG40);
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} else if (priv->type == PHY_TYPE_PCIE) {
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/* tx_trim[14]=1, Enable the counting clock of the rterm detect */
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rockchip_combphy_updatel(priv, RK3528_PHYREG86_RTERM_DET_CLK_EN,
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RK3528_PHYREG86_RTERM_DET_CLK_EN, RK3528_PHYREG86);
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}
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break;
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case REF_CLOCK_100MHz:
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rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
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if (priv->type == PHY_TYPE_PCIE) {
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/* PLL KVCO tuning fine */
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val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE);
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rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val,
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RK3528_PHYREG6);
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/* su_trim[6:4]=111, [10:7]=1001, [2:0]=000, swing 650mv */
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writel(0x570804f0, priv->mmio + RK3528_PHYREG42);
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}
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break;
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default:
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dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
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return -EINVAL;
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}
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if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
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rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
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if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
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val = FIELD_PREP(RK3528_PHYREG42_CKDRV_CLK_SEL,
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RK3528_PHYREG42_CKDRV_CLK_CKRCV);
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val |= FIELD_PREP(RK3528_PHYREG42_PLL_LPF_R1_ADJ,
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RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE);
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val |= FIELD_PREP(RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ,
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RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE);
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val |= FIELD_PREP(RK3528_PHYREG42_PLL_KVCO_ADJ,
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RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE);
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rockchip_combphy_updatel(priv,
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RK3528_PHYREG42_CKDRV_CLK_SEL |
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RK3528_PHYREG42_PLL_LPF_R1_ADJ |
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RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ |
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RK3528_PHYREG42_PLL_KVCO_ADJ,
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val, RK3528_PHYREG42);
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val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE);
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rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val,
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RK3528_PHYREG6);
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}
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}
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if (priv->type == PHY_TYPE_PCIE) {
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if (device_property_read_bool(priv->dev, "rockchip,enable-ssc"))
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rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN,
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RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40);
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}
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return 0;
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}
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static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
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/* pipe-phy-grf */
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.pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
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.usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
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.pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
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.pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
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.pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
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.pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 },
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.pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
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.pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
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.pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
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.pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
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.pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
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.pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
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.con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x110 },
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.con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x00 },
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.con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x101 },
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.con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
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/* pipe-grf */
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.u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 },
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};
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static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
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.num_phys = 1,
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.phy_ids = {
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0xffdc0000,
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},
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.grfcfg = &rk3528_combphy_grfcfgs,
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.combphy_cfg = rk3528_combphy_cfg,
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};
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static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
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{
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const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
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@ -1225,6 +1408,10 @@ static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
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};
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static const struct of_device_id rockchip_combphy_of_match[] = {
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{
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.compatible = "rockchip,rk3528-naneng-combphy",
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.data = &rk3528_combphy_cfgs,
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},
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{
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.compatible = "rockchip,rk3562-naneng-combphy",
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.data = &rk3562_combphy_cfgs,
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