superrob1500
/
mirror-linux
mirror of https://github.com/torvalds/linux
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

gpu: host1x: Syncpoint interrupt performance optimization 

Optimize performance of syncpoint interrupt handling by reading
the status register in 64-bit chunks when possible, and skipping
processing when the read value is zero.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patch.msgid.link/20250917-host1x-syncpt-irq-perf-v2-1-736ef69b1347@nvidia.com
pull/1354/merge
Mikko Perttunen 2025-09-17 10:48:30 +09:00 committed by Thierry Reding
parent ca25834123
commit bfe6897576
3 changed files with 59 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/gpu/host1x/dev.c
View File

@ -71,6 +71,15 @@ u32 host1x_sync_readl(struct host1x *host1x, u32 r)
return readl(sync_regs + r);
}
#ifdef CONFIG_64BIT
u64 host1x_sync_readq(struct host1x *host1x, u32 r)
{
void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
return readq(sync_regs + r);
}
#endif
void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
{
writel(v, ch->regs + r);

3
drivers/gpu/host1x/dev.h
View File

@ -179,6 +179,9 @@ void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r);
u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r);
void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r);
u32 host1x_sync_readl(struct host1x *host1x, u32 r);
#ifdef CONFIG_64BIT
u64 host1x_sync_readq(struct host1x *host1x, u32 r);
#endif
void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r);
u32 host1x_ch_readl(struct host1x_channel *ch, u32 r);

56
drivers/gpu/host1x/hw/intr_hw.c
View File

@ -11,27 +11,65 @@
#include "../intr.h"
#include "../dev.h"
static void process_32_syncpts(struct host1x *host, unsigned long val, u32 reg_offset)
{
unsigned int id;
if (!val)
return;
host1x_sync_writel(host, val, HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(reg_offset));
host1x_sync_writel(host, val, HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(reg_offset));
for_each_set_bit(id, &val, 32)
host1x_intr_handle_interrupt(host, reg_offset * 32 + id);
}
static irqreturn_t syncpt_thresh_isr(int irq, void *dev_id)
{
struct host1x_intr_irq_data *irq_data = dev_id;
struct host1x *host = irq_data->host;
unsigned long reg;
unsigned int i, id;
unsigned int i;
#if !defined(CONFIG_64BIT)
for (i = irq_data->offset; i < DIV_ROUND_UP(host->info->nb_pts, 32);
i += host->num_syncpt_irqs) {
reg = host1x_sync_readl(host,
HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i));
host1x_sync_writel(host, reg,
HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(i));
host1x_sync_writel(host, reg,
process_32_syncpts(host, reg, i);
}
#elif HOST1X_HW == 6 || HOST1X_HW == 7
/*
* Tegra186 and Tegra194 have the first INT_STATUS register not 64-bit aligned,
* and only have one interrupt line.
*/
reg = host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(0));
process_32_syncpts(host, reg, 0);
for (i = 1; i < (host->info->nb_pts / 32) - 1; i += 2) {
reg = host1x_sync_readq(host,
HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i));
for_each_set_bit(id, &reg, 32)
host1x_intr_handle_interrupt(host, i * 32 + id);
process_32_syncpts(host, lower_32_bits(reg), i);
process_32_syncpts(host, upper_32_bits(reg), i + 1);
}
reg = host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i));
process_32_syncpts(host, reg, i);
#else
/* All 64-bit capable SoCs have number of syncpoints divisible by 64 */
for (i = irq_data->offset; i < DIV_ROUND_UP(host->info->nb_pts, 64);
i += host->num_syncpt_irqs) {
reg = host1x_sync_readq(host,
HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i * 2));
process_32_syncpts(host, lower_32_bits(reg), i * 2 + 0);
process_32_syncpts(host, upper_32_bits(reg), i * 2 + 1);
}
#endif
return IRQ_HANDLED;
}
@ -68,12 +106,12 @@ host1x_intr_init_host_sync(struct host1x *host, u32 cpm)
/*
* Program threshold interrupt destination among 8 lines per VM,
* per syncpoint. For each group of 32 syncpoints (corresponding to one
* interrupt status register), direct to one interrupt line, going
* per syncpoint. For each group of 64 syncpoints (corresponding to two
* interrupt status registers), direct to one interrupt line, going
* around in a round robin fashion.
*/
for (id = 0; id < host->info->nb_pts; id++) {
u32 reg_offset = id / 32;
u32 reg_offset = id / 64;
u32 irq_index = reg_offset % host->num_syncpt_irqs;
host1x_sync_writel(host, irq_index, HOST1X_SYNC_SYNCPT_INTR_DEST(id));