arm64: dts: qcom: Add Mahua SoC and CRD
Introduce support for the Mahua SoC and the CRD based on it. Some of the notable differences are the absent CPU cluster, interconnect, TLMM, thermal zones and adjusted PCIe west clocks. Everything else should work as-is. Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Co-developed-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260318124100.212992-4-gopikrishna.garmidi@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>master
Gopikrishna Garmidi
Bjorn Andersson
parent
a5ad8a8e47
commit
c1014a629d
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@ -49,6 +49,7 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera.dtb
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lemans-evk-el2-dtbs := lemans-evk.dtb lemans-el2.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-el2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += mahua-crd.dtb
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dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb
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dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb
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@ -282,7 +282,7 @@
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};
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};
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cluster2 {
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cpu_map_cluster2: cluster2 {
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core0 {
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cpu = <&cpu12>;
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};
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@ -0,0 +1,21 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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/dts-v1/;
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#include "mahua.dtsi"
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#include "glymur-crd.dtsi"
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/delete-node/ &pmcx0102_d_e0;
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/delete-node/ &pmcx0102_d0_thermal;
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/delete-node/ &pmh0104_i_e0;
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/delete-node/ &pmh0104_i0_thermal;
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/delete-node/ &pmh0104_j_e0;
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/delete-node/ &pmh0104_j0_thermal;
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/ {
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model = "Qualcomm Technologies, Inc. Mahua CRD";
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compatible = "qcom,mahua-crd", "qcom,mahua";
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};
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@ -0,0 +1,299 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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/* Mahua is heavily based on Glymur, with some meaningful differences */
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#include "glymur.dtsi"
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/delete-node/ &cluster2_pd;
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/delete-node/ &cpu_map_cluster2;
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/delete-node/ &cpu12;
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/delete-node/ &cpu13;
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/delete-node/ &cpu14;
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/delete-node/ &cpu15;
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/delete-node/ &cpu16;
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/delete-node/ &cpu17;
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/delete-node/ &cpu_pd12;
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/delete-node/ &cpu_pd13;
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/delete-node/ &cpu_pd14;
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/delete-node/ &cpu_pd15;
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/delete-node/ &cpu_pd16;
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/delete-node/ &cpu_pd17;
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/delete-node/ &tsens6;
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/delete-node/ &tsens7;
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&aggre1_noc {
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compatible = "qcom,mahua-aggre1-noc", "qcom,glymur-aggre1-noc";
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};
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&aggre2_noc {
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compatible = "qcom,mahua-aggre2-noc", "qcom,glymur-aggre2-noc";
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};
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&aggre3_noc {
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compatible = "qcom,mahua-aggre3-noc", "qcom,glymur-aggre3-noc";
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};
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&aggre4_noc {
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compatible = "qcom,mahua-aggre4-noc", "qcom,glymur-aggre4-noc";
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};
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&clk_virt {
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compatible = "qcom,mahua-clk-virt", "qcom,glymur-clk-virt";
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};
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&cnoc_main {
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compatible = "qcom,mahua-cnoc-main", "qcom,glymur-cnoc-main";
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};
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&config_noc {
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compatible = "qcom,mahua-cnoc-cfg";
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};
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&hsc_noc {
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compatible = "qcom,mahua-hscnoc";
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};
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&lpass_ag_noc {
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compatible = "qcom,mahua-lpass-ag-noc", "qcom,glymur-lpass-ag-noc";
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};
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&lpass_lpiaon_noc {
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compatible = "qcom,mahua-lpass-lpiaon-noc", "qcom,glymur-lpass-lpiaon-noc";
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};
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&lpass_lpicx_noc {
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compatible = "qcom,mahua-lpass-lpicx-noc", "qcom,glymur-lpass-lpicx-noc";
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};
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&mc_virt {
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compatible = "qcom,mahua-mc-virt";
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};
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&mmss_noc {
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compatible = "qcom,mahua-mmss-noc", "qcom,glymur-mmss-noc";
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};
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&nsi_noc {
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compatible = "qcom,mahua-nsinoc", "qcom,glymur-nsinoc";
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};
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&nsp_noc {
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compatible = "qcom,mahua-nsp-noc", "qcom,glymur-nsp-noc";
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};
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&oobm_ss_noc {
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compatible = "qcom,mahua-oobm-ss-noc", "qcom,glymur-oobm-ss-noc";
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};
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&pcie_east_anoc {
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compatible = "qcom,mahua-pcie-east-anoc", "qcom,glymur-pcie-east-anoc";
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};
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&pcie_east_slv_noc {
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compatible = "qcom,mahua-pcie-east-slv-noc", "qcom,glymur-pcie-east-slv-noc";
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};
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&pcie_west_anoc {
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compatible = "qcom,mahua-pcie-west-anoc";
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clocks = <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>;
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};
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&pcie_west_slv_noc {
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compatible = "qcom,mahua-pcie-west-slv-noc";
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};
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&system_noc {
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compatible = "qcom,mahua-system-noc", "qcom,glymur-system-noc";
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};
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&tlmm {
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compatible = "qcom,mahua-tlmm";
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};
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&thermal_zones {
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/delete-node/ aoss-6-thermal;
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/delete-node/ aoss-7-thermal;
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/delete-node/ cpu-2-0-0-thermal;
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/delete-node/ cpu-2-0-1-thermal;
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/delete-node/ cpu-2-1-0-thermal;
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/delete-node/ cpu-2-1-1-thermal;
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/delete-node/ cpu-2-2-0-thermal;
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/delete-node/ cpu-2-2-1-thermal;
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/delete-node/ cpu-2-3-0-thermal;
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/delete-node/ cpu-2-3-1-thermal;
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/delete-node/ cpu-2-4-0-thermal;
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/delete-node/ cpu-2-4-1-thermal;
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/delete-node/ cpu-2-5-0-thermal;
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/delete-node/ cpu-2-5-1-thermal;
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/delete-node/ cpullc-2-0-thermal;
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/delete-node/ cpuillc-2-1-thermal;
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/delete-node/ ddr-2-thermal;
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/delete-node/ gpu-3-0-thermal;
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/delete-node/ gpu-3-1-thermal;
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/delete-node/ gpu-3-2-thermal;
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/delete-node/ qmx-2-0-thermal;
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/delete-node/ qmx-2-1-thermal;
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/delete-node/ qmx-2-2-thermal;
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/delete-node/ qmx-2-3-thermal;
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/delete-node/ qmx-2-4-thermal;
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/delete-node/ video-1-thermal;
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ddr-1-thermal {
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thermal-sensors = <&tsens1 7>;
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};
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video-0-thermal {
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thermal-sensors = <&tsens1 8>;
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};
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nsphvx-0-thermal {
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thermal-sensors = <&tsens4 1>;
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};
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nsphvx-1-thermal {
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thermal-sensors = <&tsens4 2>;
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};
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nsphvx-2-thermal {
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thermal-sensors = <&tsens4 3>;
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};
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nsphvx-3-thermal {
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thermal-sensors = <&tsens4 4>;
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};
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nsphmx-0-thermal {
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thermal-sensors = <&tsens4 5>;
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};
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nsphmx-1-thermal {
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thermal-sensors = <&tsens4 6>;
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};
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nsphmx-2-thermal {
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thermal-sensors = <&tsens4 7>;
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};
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nsphmx-3-thermal {
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thermal-sensors = <&tsens4 8>;
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};
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camera-0-thermal {
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thermal-sensors = <&tsens4 9>;
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};
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camera-1-thermal {
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thermal-sensors = <&tsens4 10>;
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};
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gpu-0-0-thermal {
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thermal-sensors = <&tsens5 1>;
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};
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gpu-0-1-thermal {
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thermal-sensors = <&tsens5 2>;
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};
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gpu-0-2-thermal {
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thermal-sensors = <&tsens5 3>;
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};
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gpu-1-0-thermal {
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thermal-sensors = <&tsens5 4>;
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};
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gpu-1-1-thermal {
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thermal-sensors = <&tsens5 5>;
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};
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gpu-1-2-thermal {
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thermal-sensors = <&tsens5 6>;
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};
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gpu-2-0-thermal {
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thermal-sensors = <&tsens5 7>;
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};
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gpu-2-1-thermal {
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thermal-sensors = <&tsens5 8>;
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};
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gpu-2-2-thermal {
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thermal-sensors = <&tsens5 9>;
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};
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gpuss-0-thermal {
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thermal-sensors = <&tsens5 10>;
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};
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gpuss-1-thermal {
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thermal-sensors = <&tsens5 11>;
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};
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gpuss-2-thermal {
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thermal-sensors = <&tsens5 12>;
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trips {
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trip-point0 {
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temperature = <90000>;
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hysteresis = <5000>;
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type = "hot";
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};
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gpuss-2-critical {
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temperature = <115000>;
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hysteresis = <1000>;
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type = "critical";
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};
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};
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};
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gpuss-3-thermal {
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thermal-sensors = <&tsens5 13>;
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trips {
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trip-point0 {
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temperature = <90000>;
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hysteresis = <5000>;
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type = "hot";
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};
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gpuss-3-critical {
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temperature = <115000>;
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hysteresis = <1000>;
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type = "critical";
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};
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};
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};
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gpuss-4-thermal {
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thermal-sensors = <&tsens5 14>;
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trips {
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trip-point0 {
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temperature = <90000>;
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hysteresis = <5000>;
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type = "hot";
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};
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gpuss-4-critical {
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temperature = <115000>;
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hysteresis = <1000>;
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type = "critical";
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};
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};
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};
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};
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&tsens4 {
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#qcom,sensors = <11>;
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};
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&tsens5 {
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#qcom,sensors = <15>;
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};
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@ -46,7 +46,7 @@
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};
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};
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pmcx0102-d0-thermal {
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pmcx0102_d0_thermal: pmcx0102-d0-thermal {
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polling-delay-passive = <100>;
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thermal-sensors = <&pmcx0102_d_e0_temp_alarm>;
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@ -8,7 +8,7 @@
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/{
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thermal_zones {
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pmh0104-i0-thermal {
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pmh0104_i0_thermal: pmh0104-i0-thermal {
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polling-delay-passive = <100>;
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thermal-sensors = <&pmh0104_i_e0_temp_alarm>;
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@ -27,7 +27,7 @@
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};
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};
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pmh0104-j0-thermal {
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pmh0104_j0_thermal: pmh0104-j0-thermal {
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polling-delay-passive = <100>;
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thermal-sensors = <&pmh0104_j_e0_temp_alarm>;
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