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x86/CPU/AMD: Prevent improper isolation of shared resources in Zen2's op cache 

Make sure resources are not improperly shared in the op cache and
cause instruction corruption this way.

Signed-off-by: Prathyushi Nangia <prathyushi.nangia@amd.com>
Co-developed-by: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Cc: stable@vger.kernel.org
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
master
Prathyushi Nangia 2025-12-09 10:01:33 -06:00 committed by Linus Torvalds
parent 50897c9559
commit c21b90f776
3 changed files with 7 additions and 2 deletions
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3
arch/x86/include/asm/msr-index.h
View File

@ -803,9 +803,10 @@
#define MSR_AMD64_LBR_SELECT 0xc000010e #define MSR_AMD64_LBR_SELECT 0xc000010e
/* Zen4 */ /* Zen4 */
#define MSR_ZEN4_BP_CFG 0xc001102e #define MSR_ZEN4_BP_CFG 0xc001102e
#define MSR_ZEN4_BP_CFG_BP_SPEC_REDUCE_BIT 4 #define MSR_ZEN4_BP_CFG_BP_SPEC_REDUCE_BIT 4
#define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5 #define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5
#define MSR_ZEN2_BP_CFG_BUG_FIX_BIT 33
/* Fam 19h MSRs */ /* Fam 19h MSRs */
#define MSR_F19H_UMC_PERF_CTL 0xc0010800 #define MSR_F19H_UMC_PERF_CTL 0xc0010800

3
arch/x86/kernel/cpu/amd.c
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@ -989,6 +989,9 @@ static void init_amd_zen2(struct cpuinfo_x86 *c)
/* Correct misconfigured CPUID on some clients. */ /* Correct misconfigured CPUID on some clients. */
clear_cpu_cap(c, X86_FEATURE_INVLPGB); clear_cpu_cap(c, X86_FEATURE_INVLPGB);
if (!cpu_has(c, X86_FEATURE_HYPERVISOR))
msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN2_BP_CFG_BUG_FIX_BIT);
} }
static void init_amd_zen3(struct cpuinfo_x86 *c) static void init_amd_zen3(struct cpuinfo_x86 *c)

3
tools/arch/x86/include/asm/msr-index.h
View File

@ -793,9 +793,10 @@
#define MSR_AMD64_LBR_SELECT 0xc000010e #define MSR_AMD64_LBR_SELECT 0xc000010e
/* Zen4 */ /* Zen4 */
#define MSR_ZEN4_BP_CFG 0xc001102e #define MSR_ZEN4_BP_CFG 0xc001102e
#define MSR_ZEN4_BP_CFG_BP_SPEC_REDUCE_BIT 4 #define MSR_ZEN4_BP_CFG_BP_SPEC_REDUCE_BIT 4
#define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5 #define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5
#define MSR_ZEN2_BP_CFG_BUG_FIX_BIT 33
/* Fam 19h MSRs */ /* Fam 19h MSRs */
#define MSR_F19H_UMC_PERF_CTL 0xc0010800 #define MSR_F19H_UMC_PERF_CTL 0xc0010800