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riscv: dts: thead: Add reset controllers of more subsystems for TH1520 

Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The
one for AO subsystem is marked as reserved, since it may be used by AON
firmware.

Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Yao Zi <ziyao@disroot.org>
Signed-off-by: Drew Fustini <fustini@kernel.org>
pull/1354/merge
Yao Zi 2025-10-14 13:10:32 +00:00 committed by Drew Fustini
parent a9fb9c7e3b
commit d8a174babf
1 changed files with 37 additions and 0 deletions
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37
arch/riscv/boot/dts/thead/th1520.dtsi
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@ -289,6 +289,12 @@
<&cpu3_intc 3>, <&cpu3_intc 7>;
};
rst_vi: reset-controller@ffe4040100 {
compatible = "thead,th1520-reset-vi";
reg = <0xff 0xe4040100 0x0 0x8>;
#reset-cells = <1>;
};
spi0: spi@ffe700c000 {
compatible = "thead,th1520-spi", "snps,dw-apb-ssi";
reg = <0xff 0xe700c000 0x0 0x1000>;
@ -521,6 +527,18 @@
#pwm-cells = <3>;
};
rst_misc: reset-controller@ffec02c000 {
compatible = "thead,th1520-reset-misc";
reg = <0xff 0xec02c000 0x0 0x18>;
#reset-cells = <1>;
};
rst_vp: reset-controller@ffecc30000 {
compatible = "thead,th1520-reset-vp";
reg = <0xff 0xecc30000 0x0 0x14>;
#reset-cells = <1>;
};
clk: clock-controller@ffef010000 {
compatible = "thead,th1520-clk-ap";
reg = <0xff 0xef010000 0x0 0x1000>;
@ -528,6 +546,18 @@
#clock-cells = <1>;
};
rst_ap: reset-controller@ffef014000 {
compatible = "thead,th1520-reset-ap";
reg = <0xff 0xef014000 0x0 0x1000>;
#reset-cells = <1>;
};
rst_dsp: reset-controller@ffef040028 {
compatible = "thead,th1520-reset-dsp";
reg = <0xff 0xef040028 0x0 0x4>;
#reset-cells = <1>;
};
gpu: gpu@ffef400000 {
compatible = "thead,th1520-gpu", "img,img-bxm-4-64",
"img,img-rogue";
@ -700,6 +730,13 @@
};
};
rst_ao: reset-controller@fffff44000 {
compatible = "thead,th1520-reset-ao";
reg = <0xff 0xfff44000 0x0 0x2000>;
#reset-cells = <1>;
status = "reserved";
};
padctrl_aosys: pinctrl@fffff4a000 {
compatible = "thead,th1520-pinctrl";
reg = <0xff 0xfff4a000 0x0 0x2000>;