LoongArch: Adjust memory management for 32BIT/64BIT
Adjust memory management for both 32BIT and 64BIT, including: address space definition, DMW CSR definition, page table bits definition, boot time detection of VA/PA bits, page table init, tlb exception handling, copy_page/clear_page/dump_tlb libraries, etc. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Yawei Li <liyawei@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>pull/1354/merge
Huacai Chen
parent
7b2afeafaf
commit
dd55dd0d7e
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@ -38,11 +38,20 @@ extern unsigned long vm_map_base;
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#endif
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#ifndef WRITECOMBINE_BASE
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#ifdef CONFIG_32BIT
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#define WRITECOMBINE_BASE CSR_DMW0_BASE
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#else
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#define WRITECOMBINE_BASE CSR_DMW2_BASE
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#endif
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#endif
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#ifdef CONFIG_32BIT
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#define DMW_PABITS 29
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#define TO_PHYS_MASK ((_UL(1) << _UL(DMW_PABITS)) - 1)
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#else
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#define DMW_PABITS 48
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#define TO_PHYS_MASK ((_ULL(1) << _ULL(DMW_PABITS)) - 1)
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#endif
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/*
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* Memory above this physical address will be considered highmem.
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@ -112,7 +121,11 @@ extern unsigned long vm_map_base;
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/*
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* Returns the physical address of a KPRANGEx / XKPRANGE address
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*/
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#ifdef CONFIG_32BIT
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#define PHYSADDR(a) ((_ACAST32_(a)) & TO_PHYS_MASK)
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#else
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#define PHYSADDR(a) ((_ACAST64_(a)) & TO_PHYS_MASK)
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#endif
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/*
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* On LoongArch, I/O ports mappring is following:
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@ -20,16 +20,13 @@
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#define cpu_has_loongarch64 (cpu_data[0].isa_level & LOONGARCH_CPU_ISA_64BIT)
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#ifdef CONFIG_32BIT
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# define cpu_has_64bits (cpu_data[0].isa_level & LOONGARCH_CPU_ISA_64BIT)
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# define cpu_vabits 31
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# define cpu_pabits 31
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#endif
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#ifdef CONFIG_64BIT
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# define cpu_has_64bits 1
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# define cpu_vabits cpu_data[0].vabits
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# define cpu_pabits cpu_data[0].pabits
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# define __NEED_ADDRBITS_PROBE
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#endif
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/*
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@ -912,6 +912,26 @@
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#define LOONGARCH_CSR_DMWIN3 0x183 /* 64 direct map win3: MEM */
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/* Direct Map window 0/1/2/3 */
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#ifdef CONFIG_32BIT
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#define CSR_DMW0_PLV0 (1 << 0)
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#define CSR_DMW0_VSEG (0x4)
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#define CSR_DMW0_BASE (CSR_DMW0_VSEG << DMW_PABITS)
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#define CSR_DMW0_INIT (CSR_DMW0_BASE | CSR_DMW0_PLV0)
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#define CSR_DMW1_PLV0 (1 << 0)
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#define CSR_DMW1_MAT (1 << 4)
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#define CSR_DMW1_VSEG (0x5)
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#define CSR_DMW1_BASE (CSR_DMW1_VSEG << DMW_PABITS)
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#define CSR_DMW1_INIT (CSR_DMW1_BASE | CSR_DMW1_MAT | CSR_DMW1_PLV0)
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#define CSR_DMW2_INIT 0x0
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#define CSR_DMW3_INIT 0x0
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#else
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#define CSR_DMW0_PLV0 _CONST64_(1 << 0)
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#define CSR_DMW0_VSEG _CONST64_(0x8000)
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#define CSR_DMW0_BASE (CSR_DMW0_VSEG << DMW_PABITS)
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@ -931,6 +951,8 @@
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#define CSR_DMW3_INIT 0x0
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#endif
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/* Performance Counter registers */
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#define LOONGARCH_CSR_PERFCTRL0 0x200 /* 32 perf event 0 config */
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#define LOONGARCH_CSR_PERFCNTR0 0x201 /* 64 perf event 0 count value */
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@ -1388,8 +1410,10 @@ __BUILD_CSR_OP(tlbidx)
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#define ENTRYLO_C_SHIFT 4
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#define ENTRYLO_C (_ULCAST_(3) << ENTRYLO_C_SHIFT)
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#define ENTRYLO_G (_ULCAST_(1) << 6)
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#ifdef CONFIG_64BIT
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#define ENTRYLO_NR (_ULCAST_(1) << 61)
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#define ENTRYLO_NX (_ULCAST_(1) << 62)
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#endif
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/* Values for PageSize register */
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#define PS_4K 0x0000000c
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@ -10,7 +10,7 @@
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#include <vdso/page.h>
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#define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3)
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#define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - PTRLOG)
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#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
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#define HPAGE_MASK (~(HPAGE_SIZE - 1))
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#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
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@ -6,6 +6,26 @@
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#define _ASM_PGTABLE_BITS_H
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/* Page table bits */
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#ifdef CONFIG_32BIT
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#define _PAGE_VALID_SHIFT 0
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#define _PAGE_ACCESSED_SHIFT 0 /* Reuse Valid for Accessed */
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#define _PAGE_DIRTY_SHIFT 1
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#define _PAGE_PLV_SHIFT 2 /* 2~3, two bits */
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#define _CACHE_SHIFT 4 /* 4~5, two bits */
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#define _PAGE_GLOBAL_SHIFT 6
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#define _PAGE_HUGE_SHIFT 6 /* HUGE is a PMD bit */
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#define _PAGE_PRESENT_SHIFT 7
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#define _PAGE_PFN_SHIFT 8
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#define _PAGE_HGLOBAL_SHIFT 12 /* HGlobal is a PMD bit */
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#define _PAGE_SWP_EXCLUSIVE_SHIFT 13
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#define _PAGE_PFN_END_SHIFT 28
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#define _PAGE_WRITE_SHIFT 29
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#define _PAGE_MODIFIED_SHIFT 30
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#define _PAGE_PRESENT_INVALID_SHIFT 31
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#endif
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#ifdef CONFIG_64BIT
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#define _PAGE_VALID_SHIFT 0
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#define _PAGE_ACCESSED_SHIFT 0 /* Reuse Valid for Accessed */
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#define _PAGE_DIRTY_SHIFT 1
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@ -18,14 +38,15 @@
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#define _PAGE_MODIFIED_SHIFT 9
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#define _PAGE_PROTNONE_SHIFT 10
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#define _PAGE_SPECIAL_SHIFT 11
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#define _PAGE_HGLOBAL_SHIFT 12 /* HGlobal is a PMD bit */
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#define _PAGE_PFN_SHIFT 12
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#define _PAGE_HGLOBAL_SHIFT 12 /* HGlobal is a PMD bit */
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#define _PAGE_SWP_EXCLUSIVE_SHIFT 23
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#define _PAGE_PFN_END_SHIFT 48
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#define _PAGE_PRESENT_INVALID_SHIFT 60
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#define _PAGE_NO_READ_SHIFT 61
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#define _PAGE_NO_EXEC_SHIFT 62
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#define _PAGE_RPLV_SHIFT 63
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#endif
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/* Used by software */
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#define _PAGE_PRESENT (_ULCAST_(1) << _PAGE_PRESENT_SHIFT)
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@ -33,10 +54,15 @@
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#define _PAGE_WRITE (_ULCAST_(1) << _PAGE_WRITE_SHIFT)
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#define _PAGE_ACCESSED (_ULCAST_(1) << _PAGE_ACCESSED_SHIFT)
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#define _PAGE_MODIFIED (_ULCAST_(1) << _PAGE_MODIFIED_SHIFT)
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#ifdef CONFIG_32BIT
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#define _PAGE_PROTNONE 0
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#define _PAGE_SPECIAL 0
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#else
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#define _PAGE_PROTNONE (_ULCAST_(1) << _PAGE_PROTNONE_SHIFT)
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#define _PAGE_SPECIAL (_ULCAST_(1) << _PAGE_SPECIAL_SHIFT)
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#endif
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/* We borrow bit 23 to store the exclusive marker in swap PTEs. */
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/* We borrow bit 13/23 to store the exclusive marker in swap PTEs. */
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#define _PAGE_SWP_EXCLUSIVE (_ULCAST_(1) << _PAGE_SWP_EXCLUSIVE_SHIFT)
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/* Used by TLB hardware (placed in EntryLo*) */
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@ -46,9 +72,15 @@
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#define _PAGE_GLOBAL (_ULCAST_(1) << _PAGE_GLOBAL_SHIFT)
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#define _PAGE_HUGE (_ULCAST_(1) << _PAGE_HUGE_SHIFT)
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#define _PAGE_HGLOBAL (_ULCAST_(1) << _PAGE_HGLOBAL_SHIFT)
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#ifdef CONFIG_32BIT
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#define _PAGE_NO_READ 0
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#define _PAGE_NO_EXEC 0
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#define _PAGE_RPLV 0
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#else
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#define _PAGE_NO_READ (_ULCAST_(1) << _PAGE_NO_READ_SHIFT)
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#define _PAGE_NO_EXEC (_ULCAST_(1) << _PAGE_NO_EXEC_SHIFT)
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#define _PAGE_RPLV (_ULCAST_(1) << _PAGE_RPLV_SHIFT)
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#endif
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#define _CACHE_MASK (_ULCAST_(3) << _CACHE_SHIFT)
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#define PFN_PTE_SHIFT (PAGE_SHIFT - 12 + _PAGE_PFN_SHIFT)
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@ -11,6 +11,7 @@
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#include <linux/compiler.h>
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include <asm/page.h>
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#include <asm/pgtable-bits.h>
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@ -23,37 +24,45 @@
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#endif
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#if CONFIG_PGTABLE_LEVELS == 2
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#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - 3))
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#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - PTRLOG))
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#elif CONFIG_PGTABLE_LEVELS == 3
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#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - 3))
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#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - PTRLOG))
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT - 3))
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#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT - PTRLOG))
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#elif CONFIG_PGTABLE_LEVELS == 4
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#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - 3))
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#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - PTRLOG))
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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#define PUD_SHIFT (PMD_SHIFT + (PAGE_SHIFT - 3))
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#define PUD_SHIFT (PMD_SHIFT + (PAGE_SHIFT - PTRLOG))
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#define PUD_SIZE (1UL << PUD_SHIFT)
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#define PUD_MASK (~(PUD_SIZE-1))
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#define PGDIR_SHIFT (PUD_SHIFT + (PAGE_SHIFT - 3))
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#define PGDIR_SHIFT (PUD_SHIFT + (PAGE_SHIFT - PTRLOG))
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#endif
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#define VA_BITS (PGDIR_SHIFT + (PAGE_SHIFT - 3))
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#ifdef CONFIG_32BIT
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#define VA_BITS 32
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#else
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#define VA_BITS (PGDIR_SHIFT + (PAGE_SHIFT - PTRLOG))
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#endif
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#define PTRS_PER_PGD (PAGE_SIZE >> 3)
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#define PTRS_PER_PGD (PAGE_SIZE >> PTRLOG)
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#if CONFIG_PGTABLE_LEVELS > 3
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#define PTRS_PER_PUD (PAGE_SIZE >> 3)
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#define PTRS_PER_PUD (PAGE_SIZE >> PTRLOG)
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#endif
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#if CONFIG_PGTABLE_LEVELS > 2
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#define PTRS_PER_PMD (PAGE_SIZE >> 3)
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#define PTRS_PER_PMD (PAGE_SIZE >> PTRLOG)
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#endif
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#define PTRS_PER_PTE (PAGE_SIZE >> 3)
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#define PTRS_PER_PTE (PAGE_SIZE >> PTRLOG)
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#ifdef CONFIG_32BIT
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#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
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#else
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#define USER_PTRS_PER_PGD ((TASK_SIZE64 / PGDIR_SIZE)?(TASK_SIZE64 / PGDIR_SIZE):1)
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#endif
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#ifndef __ASSEMBLER__
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@ -74,11 +83,15 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
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#define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page)
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/*
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* TLB refill handlers may also map the vmalloc area into xkvrange.
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* Avoid the first couple of pages so NULL pointer dereferences will
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* still reliably trap.
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*/
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#ifdef CONFIG_32BIT
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#define VMALLOC_START (vm_map_base + PCI_IOSIZE + (2 * PAGE_SIZE))
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#define VMALLOC_END (FIXADDR_START - (2 * PAGE_SIZE))
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#endif
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#ifdef CONFIG_64BIT
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#define MODULES_VADDR (vm_map_base + PCI_IOSIZE + (2 * PAGE_SIZE))
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#define MODULES_END (MODULES_VADDR + SZ_256M)
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@ -106,6 +119,8 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
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#define KFENCE_AREA_START (VMEMMAP_END + 1)
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#define KFENCE_AREA_END (KFENCE_AREA_START + KFENCE_AREA_SIZE - 1)
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#endif
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#define ptep_get(ptep) READ_ONCE(*(ptep))
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#define pmdp_get(pmdp) READ_ONCE(*(pmdp))
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@ -277,7 +292,16 @@ extern void kernel_pte_init(void *addr);
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* Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
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* are !pte_none() && !pte_present().
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*
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* Format of swap PTEs:
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* Format of 32bit swap PTEs:
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*
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* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* <------------ offset -------------> E <- type -> <-- zeroes -->
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*
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* E is the exclusive marker that is not stored in swap entries.
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* The zero'ed bits include _PAGE_PRESENT.
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*
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* Format of 64bit swap PTEs:
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*
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* 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3
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* 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
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@ -290,16 +314,27 @@ extern void kernel_pte_init(void *addr);
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* E is the exclusive marker that is not stored in swap entries.
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* The zero'ed bits include _PAGE_PRESENT and _PAGE_PROTNONE.
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*/
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static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
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{ pte_t pte; pte_val(pte) = ((type & 0x7f) << 16) | (offset << 24); return pte; }
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#define __swp_type(x) (((x).val >> 16) & 0x7f)
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#define __swp_offset(x) ((x).val >> 24)
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#define __SWP_TYPE_BITS (IS_ENABLED(CONFIG_32BIT) ? 5 : 7)
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#define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1)
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#define __SWP_TYPE_SHIFT (IS_ENABLED(CONFIG_32BIT) ? 8 : 16)
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#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT + 1)
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static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
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{
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pte_t pte;
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pte_val(pte) = ((type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | (offset << __SWP_OFFSET_SHIFT);
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return pte;
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}
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#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
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#define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT)
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#define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) __pte((x).val)
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#define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) })
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#define __swp_entry_to_pmd(x) __pmd((x).val | _PAGE_HUGE)
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) })
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static inline bool pte_swp_exclusive(pte_t pte)
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{
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@ -106,7 +106,11 @@ EXPORT_SYMBOL(vm_map_base);
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static void cpu_probe_addrbits(struct cpuinfo_loongarch *c)
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{
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#ifdef __NEED_ADDRBITS_PROBE
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#ifdef CONFIG_32BIT
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c->pabits = cpu_pabits;
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c->vabits = cpu_vabits;
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vm_map_base = KVRANGE;
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#else
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c->pabits = (read_cpucfg(LOONGARCH_CPUCFG1) & CPUCFG1_PABITS) >> 4;
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c->vabits = (read_cpucfg(LOONGARCH_CPUCFG1) & CPUCFG1_VABITS) >> 12;
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vm_map_base = 0UL - (1UL << c->vabits);
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@ -73,12 +73,16 @@ static void dump_tlb(int first, int last)
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vwidth, (entryhi & ~0x1fffUL), asidwidth, asid & asidmask);
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/* NR/NX are in awkward places, so mask them off separately */
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#ifdef CONFIG_64BIT
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pa = entrylo0 & ~(ENTRYLO_NR | ENTRYLO_NX);
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#endif
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pa = pa & PAGE_MASK;
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pr_cont("\n\t[");
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#ifdef CONFIG_64BIT
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pr_cont("nr=%d nx=%d ",
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(entrylo0 & ENTRYLO_NR) ? 1 : 0,
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(entrylo0 & ENTRYLO_NX) ? 1 : 0);
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#endif
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pr_cont("pa=0x%0*llx c=%d d=%d v=%d g=%d plv=%lld] [",
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pwidth, pa, c0,
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(entrylo0 & ENTRYLO_D) ? 1 : 0,
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@ -86,11 +90,15 @@ static void dump_tlb(int first, int last)
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(entrylo0 & ENTRYLO_G) ? 1 : 0,
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(entrylo0 & ENTRYLO_PLV) >> ENTRYLO_PLV_SHIFT);
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/* NR/NX are in awkward places, so mask them off separately */
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#ifdef CONFIG_64BIT
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pa = entrylo1 & ~(ENTRYLO_NR | ENTRYLO_NX);
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#endif
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pa = pa & PAGE_MASK;
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#ifdef CONFIG_64BIT
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pr_cont("nr=%d nx=%d ",
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(entrylo1 & ENTRYLO_NR) ? 1 : 0,
|
||||
(entrylo1 & ENTRYLO_NX) ? 1 : 0);
|
||||
#endif
|
||||
pr_cont("pa=0x%0*llx c=%d d=%d v=%d g=%d plv=%lld]\n",
|
||||
pwidth, pa, c1,
|
||||
(entrylo1 & ENTRYLO_D) ? 1 : 0,
|
||||
|
|
|
|||
|
|
@ -224,7 +224,7 @@ EXPORT_SYMBOL(invalid_pmd_table);
|
|||
pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned_bss;
|
||||
EXPORT_SYMBOL(invalid_pte_table);
|
||||
|
||||
#ifdef CONFIG_EXECMEM
|
||||
#if defined(CONFIG_EXECMEM) && defined(MODULES_VADDR)
|
||||
static struct execmem_info execmem_info __ro_after_init;
|
||||
|
||||
struct execmem_info __init *execmem_arch_setup(void)
|
||||
|
|
@ -242,4 +242,4 @@ struct execmem_info __init *execmem_arch_setup(void)
|
|||
|
||||
return &execmem_info;
|
||||
}
|
||||
#endif /* CONFIG_EXECMEM */
|
||||
#endif /* CONFIG_EXECMEM && MODULES_VADDR */
|
||||
|
|
|
|||
|
|
@ -10,75 +10,75 @@
|
|||
|
||||
.align 5
|
||||
SYM_FUNC_START(clear_page)
|
||||
lu12i.w t0, 1 << (PAGE_SHIFT - 12)
|
||||
add.d t0, t0, a0
|
||||
lu12i.w t0, 1 << (PAGE_SHIFT - 12)
|
||||
PTR_ADD t0, t0, a0
|
||||
1:
|
||||
st.d zero, a0, 0
|
||||
st.d zero, a0, 8
|
||||
st.d zero, a0, 16
|
||||
st.d zero, a0, 24
|
||||
st.d zero, a0, 32
|
||||
st.d zero, a0, 40
|
||||
st.d zero, a0, 48
|
||||
st.d zero, a0, 56
|
||||
addi.d a0, a0, 128
|
||||
st.d zero, a0, -64
|
||||
st.d zero, a0, -56
|
||||
st.d zero, a0, -48
|
||||
st.d zero, a0, -40
|
||||
st.d zero, a0, -32
|
||||
st.d zero, a0, -24
|
||||
st.d zero, a0, -16
|
||||
st.d zero, a0, -8
|
||||
bne t0, a0, 1b
|
||||
LONG_S zero, a0, (LONGSIZE * 0)
|
||||
LONG_S zero, a0, (LONGSIZE * 1)
|
||||
LONG_S zero, a0, (LONGSIZE * 2)
|
||||
LONG_S zero, a0, (LONGSIZE * 3)
|
||||
LONG_S zero, a0, (LONGSIZE * 4)
|
||||
LONG_S zero, a0, (LONGSIZE * 5)
|
||||
LONG_S zero, a0, (LONGSIZE * 6)
|
||||
LONG_S zero, a0, (LONGSIZE * 7)
|
||||
PTR_ADDI a0, a0, (LONGSIZE * 16)
|
||||
LONG_S zero, a0, -(LONGSIZE * 8)
|
||||
LONG_S zero, a0, -(LONGSIZE * 7)
|
||||
LONG_S zero, a0, -(LONGSIZE * 6)
|
||||
LONG_S zero, a0, -(LONGSIZE * 5)
|
||||
LONG_S zero, a0, -(LONGSIZE * 4)
|
||||
LONG_S zero, a0, -(LONGSIZE * 3)
|
||||
LONG_S zero, a0, -(LONGSIZE * 2)
|
||||
LONG_S zero, a0, -(LONGSIZE * 1)
|
||||
bne t0, a0, 1b
|
||||
|
||||
jr ra
|
||||
jr ra
|
||||
SYM_FUNC_END(clear_page)
|
||||
EXPORT_SYMBOL(clear_page)
|
||||
|
||||
.align 5
|
||||
SYM_FUNC_START(copy_page)
|
||||
lu12i.w t8, 1 << (PAGE_SHIFT - 12)
|
||||
add.d t8, t8, a0
|
||||
lu12i.w t8, 1 << (PAGE_SHIFT - 12)
|
||||
PTR_ADD t8, t8, a0
|
||||
1:
|
||||
ld.d t0, a1, 0
|
||||
ld.d t1, a1, 8
|
||||
ld.d t2, a1, 16
|
||||
ld.d t3, a1, 24
|
||||
ld.d t4, a1, 32
|
||||
ld.d t5, a1, 40
|
||||
ld.d t6, a1, 48
|
||||
ld.d t7, a1, 56
|
||||
LONG_L t0, a1, (LONGSIZE * 0)
|
||||
LONG_L t1, a1, (LONGSIZE * 1)
|
||||
LONG_L t2, a1, (LONGSIZE * 2)
|
||||
LONG_L t3, a1, (LONGSIZE * 3)
|
||||
LONG_L t4, a1, (LONGSIZE * 4)
|
||||
LONG_L t5, a1, (LONGSIZE * 5)
|
||||
LONG_L t6, a1, (LONGSIZE * 6)
|
||||
LONG_L t7, a1, (LONGSIZE * 7)
|
||||
|
||||
st.d t0, a0, 0
|
||||
st.d t1, a0, 8
|
||||
ld.d t0, a1, 64
|
||||
ld.d t1, a1, 72
|
||||
st.d t2, a0, 16
|
||||
st.d t3, a0, 24
|
||||
ld.d t2, a1, 80
|
||||
ld.d t3, a1, 88
|
||||
st.d t4, a0, 32
|
||||
st.d t5, a0, 40
|
||||
ld.d t4, a1, 96
|
||||
ld.d t5, a1, 104
|
||||
st.d t6, a0, 48
|
||||
st.d t7, a0, 56
|
||||
ld.d t6, a1, 112
|
||||
ld.d t7, a1, 120
|
||||
addi.d a0, a0, 128
|
||||
addi.d a1, a1, 128
|
||||
LONG_S t0, a0, (LONGSIZE * 0)
|
||||
LONG_S t1, a0, (LONGSIZE * 1)
|
||||
LONG_L t0, a1, (LONGSIZE * 8)
|
||||
LONG_L t1, a1, (LONGSIZE * 9)
|
||||
LONG_S t2, a0, (LONGSIZE * 2)
|
||||
LONG_S t3, a0, (LONGSIZE * 3)
|
||||
LONG_L t2, a1, (LONGSIZE * 10)
|
||||
LONG_L t3, a1, (LONGSIZE * 11)
|
||||
LONG_S t4, a0, (LONGSIZE * 4)
|
||||
LONG_S t5, a0, (LONGSIZE * 5)
|
||||
LONG_L t4, a1, (LONGSIZE * 12)
|
||||
LONG_L t5, a1, (LONGSIZE * 13)
|
||||
LONG_S t6, a0, (LONGSIZE * 6)
|
||||
LONG_S t7, a0, (LONGSIZE * 7)
|
||||
LONG_L t6, a1, (LONGSIZE * 14)
|
||||
LONG_L t7, a1, (LONGSIZE * 15)
|
||||
PTR_ADDI a0, a0, (LONGSIZE * 16)
|
||||
PTR_ADDI a1, a1, (LONGSIZE * 16)
|
||||
|
||||
st.d t0, a0, -64
|
||||
st.d t1, a0, -56
|
||||
st.d t2, a0, -48
|
||||
st.d t3, a0, -40
|
||||
st.d t4, a0, -32
|
||||
st.d t5, a0, -24
|
||||
st.d t6, a0, -16
|
||||
st.d t7, a0, -8
|
||||
LONG_S t0, a0, -(LONGSIZE * 8)
|
||||
LONG_S t1, a0, -(LONGSIZE * 7)
|
||||
LONG_S t2, a0, -(LONGSIZE * 6)
|
||||
LONG_S t3, a0, -(LONGSIZE * 5)
|
||||
LONG_S t4, a0, -(LONGSIZE * 4)
|
||||
LONG_S t5, a0, -(LONGSIZE * 3)
|
||||
LONG_S t6, a0, -(LONGSIZE * 2)
|
||||
LONG_S t7, a0, -(LONGSIZE * 1)
|
||||
|
||||
bne t8, a0, 1b
|
||||
jr ra
|
||||
bne t8, a0, 1b
|
||||
jr ra
|
||||
SYM_FUNC_END(copy_page)
|
||||
EXPORT_SYMBOL(copy_page)
|
||||
|
|
|
|||
|
|
@ -251,8 +251,10 @@ static void output_pgtable_bits_defines(void)
|
|||
pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
|
||||
pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
|
||||
pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
|
||||
#ifdef CONFIG_64BIT
|
||||
pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
|
||||
pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
|
||||
#endif
|
||||
pr_define("PFN_PTE_SHIFT %d\n", PFN_PTE_SHIFT);
|
||||
pr_debug("\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,10 +11,18 @@
|
|||
|
||||
#define INVTLB_ADDR_GFALSE_AND_ASID 5
|
||||
|
||||
#define PTRS_PER_PGD_BITS (PAGE_SHIFT - 3)
|
||||
#define PTRS_PER_PUD_BITS (PAGE_SHIFT - 3)
|
||||
#define PTRS_PER_PMD_BITS (PAGE_SHIFT - 3)
|
||||
#define PTRS_PER_PTE_BITS (PAGE_SHIFT - 3)
|
||||
#define PTRS_PER_PGD_BITS (PAGE_SHIFT - PTRLOG)
|
||||
#define PTRS_PER_PUD_BITS (PAGE_SHIFT - PTRLOG)
|
||||
#define PTRS_PER_PMD_BITS (PAGE_SHIFT - PTRLOG)
|
||||
#define PTRS_PER_PTE_BITS (PAGE_SHIFT - PTRLOG)
|
||||
|
||||
#ifdef CONFIG_32BIT
|
||||
#define PTE_LL ll.w
|
||||
#define PTE_SC sc.w
|
||||
#else
|
||||
#define PTE_LL ll.d
|
||||
#define PTE_SC sc.d
|
||||
#endif
|
||||
|
||||
.macro tlb_do_page_fault, write
|
||||
SYM_CODE_START(tlb_do_page_fault_\write)
|
||||
|
|
@ -60,52 +68,61 @@ SYM_CODE_START(handle_tlb_load)
|
|||
|
||||
vmalloc_done_load:
|
||||
/* Get PGD offset in bytes */
|
||||
bstrpick.d ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT
|
||||
alsl.d t1, ra, t1, 3
|
||||
#ifdef CONFIG_32BIT
|
||||
PTR_BSTRPICK ra, t0, 31, PGDIR_SHIFT
|
||||
#else
|
||||
PTR_BSTRPICK ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT
|
||||
#endif
|
||||
PTR_ALSL t1, ra, t1, _PGD_T_LOG2
|
||||
|
||||
#if CONFIG_PGTABLE_LEVELS > 3
|
||||
ld.d t1, t1, 0
|
||||
bstrpick.d ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT
|
||||
alsl.d t1, ra, t1, 3
|
||||
PTR_L t1, t1, 0
|
||||
PTR_BSTRPICK ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT
|
||||
PTR_ALSL t1, ra, t1, _PMD_T_LOG2
|
||||
|
||||
#endif
|
||||
#if CONFIG_PGTABLE_LEVELS > 2
|
||||
ld.d t1, t1, 0
|
||||
bstrpick.d ra, t0, PTRS_PER_PMD_BITS + PMD_SHIFT - 1, PMD_SHIFT
|
||||
alsl.d t1, ra, t1, 3
|
||||
PTR_L t1, t1, 0
|
||||
PTR_BSTRPICK ra, t0, PTRS_PER_PMD_BITS + PMD_SHIFT - 1, PMD_SHIFT
|
||||
PTR_ALSL t1, ra, t1, _PMD_T_LOG2
|
||||
|
||||
#endif
|
||||
ld.d ra, t1, 0
|
||||
PTR_L ra, t1, 0
|
||||
|
||||
/*
|
||||
* For huge tlb entries, pmde doesn't contain an address but
|
||||
* instead contains the tlb pte. Check the PAGE_HUGE bit and
|
||||
* see if we need to jump to huge tlb processing.
|
||||
*/
|
||||
rotri.d ra, ra, _PAGE_HUGE_SHIFT + 1
|
||||
PTR_ROTRI ra, ra, _PAGE_HUGE_SHIFT + 1
|
||||
bltz ra, tlb_huge_update_load
|
||||
|
||||
rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1)
|
||||
bstrpick.d t0, t0, PTRS_PER_PTE_BITS + PAGE_SHIFT - 1, PAGE_SHIFT
|
||||
alsl.d t1, t0, ra, _PTE_T_LOG2
|
||||
PTR_ROTRI ra, ra, BITS_PER_LONG - (_PAGE_HUGE_SHIFT + 1)
|
||||
PTR_BSTRPICK t0, t0, PTRS_PER_PTE_BITS + PAGE_SHIFT - 1, PAGE_SHIFT
|
||||
PTR_ALSL t1, t0, ra, _PTE_T_LOG2
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
smp_pgtable_change_load:
|
||||
ll.d t0, t1, 0
|
||||
PTE_LL t0, t1, 0
|
||||
#else
|
||||
ld.d t0, t1, 0
|
||||
PTR_L t0, t1, 0
|
||||
#endif
|
||||
andi ra, t0, _PAGE_PRESENT
|
||||
beqz ra, nopage_tlb_load
|
||||
|
||||
ori t0, t0, _PAGE_VALID
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
sc.d t0, t1, 0
|
||||
PTE_SC t0, t1, 0
|
||||
beqz t0, smp_pgtable_change_load
|
||||
#else
|
||||
st.d t0, t1, 0
|
||||
PTR_S t0, t1, 0
|
||||
#endif
|
||||
|
||||
tlbsrch
|
||||
bstrins.d t1, zero, 3, 3
|
||||
ld.d t0, t1, 0
|
||||
ld.d t1, t1, 8
|
||||
PTR_BSTRINS t1, zero, _PTE_T_LOG2, _PTE_T_LOG2
|
||||
PTR_L t0, t1, 0
|
||||
PTR_L t1, t1, _PTE_T_SIZE
|
||||
csrwr t0, LOONGARCH_CSR_TLBELO0
|
||||
csrwr t1, LOONGARCH_CSR_TLBELO1
|
||||
tlbwr
|
||||
|
|
@ -115,30 +132,28 @@ smp_pgtable_change_load:
|
|||
csrrd ra, EXCEPTION_KS2
|
||||
ertn
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
vmalloc_load:
|
||||
la_abs t1, swapper_pg_dir
|
||||
b vmalloc_done_load
|
||||
#endif
|
||||
|
||||
/* This is the entry point of a huge page. */
|
||||
tlb_huge_update_load:
|
||||
#ifdef CONFIG_SMP
|
||||
ll.d ra, t1, 0
|
||||
PTE_LL ra, t1, 0
|
||||
#else
|
||||
rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1)
|
||||
PTR_ROTRI ra, ra, BITS_PER_LONG - (_PAGE_HUGE_SHIFT + 1)
|
||||
#endif
|
||||
andi t0, ra, _PAGE_PRESENT
|
||||
beqz t0, nopage_tlb_load
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
ori t0, ra, _PAGE_VALID
|
||||
sc.d t0, t1, 0
|
||||
PTE_SC t0, t1, 0
|
||||
beqz t0, tlb_huge_update_load
|
||||
ori t0, ra, _PAGE_VALID
|
||||
#else
|
||||
ori t0, ra, _PAGE_VALID
|
||||
st.d t0, t1, 0
|
||||
PTR_S t0, t1, 0
|
||||
#endif
|
||||
csrrd ra, LOONGARCH_CSR_ASID
|
||||
csrrd t1, LOONGARCH_CSR_BADV
|
||||
|
|
@ -158,27 +173,27 @@ tlb_huge_update_load:
|
|||
xori t0, t0, _PAGE_HUGE
|
||||
lu12i.w t1, _PAGE_HGLOBAL >> 12
|
||||
and t1, t0, t1
|
||||
srli.d t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT)
|
||||
PTR_SRLI t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT)
|
||||
or t0, t0, t1
|
||||
|
||||
move ra, t0
|
||||
csrwr ra, LOONGARCH_CSR_TLBELO0
|
||||
|
||||
/* Convert to entrylo1 */
|
||||
addi.d t1, zero, 1
|
||||
slli.d t1, t1, (HPAGE_SHIFT - 1)
|
||||
add.d t0, t0, t1
|
||||
PTR_ADDI t1, zero, 1
|
||||
PTR_SLLI t1, t1, (HPAGE_SHIFT - 1)
|
||||
PTR_ADD t0, t0, t1
|
||||
csrwr t0, LOONGARCH_CSR_TLBELO1
|
||||
|
||||
/* Set huge page tlb entry size */
|
||||
addu16i.d t0, zero, (CSR_TLBIDX_PS >> 16)
|
||||
addu16i.d t1, zero, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT - 16))
|
||||
PTR_LI t0, (CSR_TLBIDX_PS >> 16) << 16
|
||||
PTR_LI t1, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT))
|
||||
csrxchg t1, t0, LOONGARCH_CSR_TLBIDX
|
||||
|
||||
tlbfill
|
||||
|
||||
addu16i.d t0, zero, (CSR_TLBIDX_PS >> 16)
|
||||
addu16i.d t1, zero, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT - 16))
|
||||
PTR_LI t0, (CSR_TLBIDX_PS >> 16) << 16
|
||||
PTR_LI t1, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT))
|
||||
csrxchg t1, t0, LOONGARCH_CSR_TLBIDX
|
||||
|
||||
csrrd t0, EXCEPTION_KS0
|
||||
|
|
@ -216,53 +231,71 @@ SYM_CODE_START(handle_tlb_store)
|
|||
|
||||
vmalloc_done_store:
|
||||
/* Get PGD offset in bytes */
|
||||
bstrpick.d ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT
|
||||
alsl.d t1, ra, t1, 3
|
||||
#ifdef CONFIG_32BIT
|
||||
PTR_BSTRPICK ra, t0, 31, PGDIR_SHIFT
|
||||
#else
|
||||
PTR_BSTRPICK ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT
|
||||
#endif
|
||||
PTR_ALSL t1, ra, t1, _PGD_T_LOG2
|
||||
|
||||
#if CONFIG_PGTABLE_LEVELS > 3
|
||||
ld.d t1, t1, 0
|
||||
bstrpick.d ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT
|
||||
alsl.d t1, ra, t1, 3
|
||||
PTR_L t1, t1, 0
|
||||
PTR_BSTRPICK ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT
|
||||
PTR_ALSL t1, ra, t1, _PMD_T_LOG2
|
||||
#endif
|
||||
#if CONFIG_PGTABLE_LEVELS > 2
|
||||
ld.d t1, t1, 0
|
||||
bstrpick.d ra, t0, PTRS_PER_PMD_BITS + PMD_SHIFT - 1, PMD_SHIFT
|
||||
alsl.d t1, ra, t1, 3
|
||||
PTR_L t1, t1, 0
|
||||
PTR_BSTRPICK ra, t0, PTRS_PER_PMD_BITS + PMD_SHIFT - 1, PMD_SHIFT
|
||||
PTR_ALSL t1, ra, t1, _PMD_T_LOG2
|
||||
#endif
|
||||
ld.d ra, t1, 0
|
||||
PTR_L ra, t1, 0
|
||||
|
||||
/*
|
||||
* For huge tlb entries, pmde doesn't contain an address but
|
||||
* instead contains the tlb pte. Check the PAGE_HUGE bit and
|
||||
* see if we need to jump to huge tlb processing.
|
||||
*/
|
||||
rotri.d ra, ra, _PAGE_HUGE_SHIFT + 1
|
||||
PTR_ROTRI ra, ra, _PAGE_HUGE_SHIFT + 1
|
||||
bltz ra, tlb_huge_update_store
|
||||
|
||||
rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1)
|
||||
bstrpick.d t0, t0, PTRS_PER_PTE_BITS + PAGE_SHIFT - 1, PAGE_SHIFT
|
||||
alsl.d t1, t0, ra, _PTE_T_LOG2
|
||||
PTR_ROTRI ra, ra, BITS_PER_LONG - (_PAGE_HUGE_SHIFT + 1)
|
||||
PTR_BSTRPICK t0, t0, PTRS_PER_PTE_BITS + PAGE_SHIFT - 1, PAGE_SHIFT
|
||||
PTR_ALSL t1, t0, ra, _PTE_T_LOG2
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
smp_pgtable_change_store:
|
||||
ll.d t0, t1, 0
|
||||
PTE_LL t0, t1, 0
|
||||
#else
|
||||
ld.d t0, t1, 0
|
||||
PTR_L t0, t1, 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
andi ra, t0, _PAGE_PRESENT | _PAGE_WRITE
|
||||
xori ra, ra, _PAGE_PRESENT | _PAGE_WRITE
|
||||
#else
|
||||
PTR_LI ra, _PAGE_PRESENT | _PAGE_WRITE
|
||||
and ra, ra, t0
|
||||
nor ra, ra, zero
|
||||
#endif
|
||||
bnez ra, nopage_tlb_store
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
ori t0, t0, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
|
||||
#else
|
||||
PTR_LI ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
|
||||
or t0, ra, t0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
sc.d t0, t1, 0
|
||||
PTE_SC t0, t1, 0
|
||||
beqz t0, smp_pgtable_change_store
|
||||
#else
|
||||
st.d t0, t1, 0
|
||||
PTR_S t0, t1, 0
|
||||
#endif
|
||||
tlbsrch
|
||||
bstrins.d t1, zero, 3, 3
|
||||
ld.d t0, t1, 0
|
||||
ld.d t1, t1, 8
|
||||
PTR_BSTRINS t1, zero, _PTE_T_LOG2, _PTE_T_LOG2
|
||||
PTR_L t0, t1, 0
|
||||
PTR_L t1, t1, _PTE_T_SIZE
|
||||
csrwr t0, LOONGARCH_CSR_TLBELO0
|
||||
csrwr t1, LOONGARCH_CSR_TLBELO1
|
||||
tlbwr
|
||||
|
|
@ -272,31 +305,42 @@ smp_pgtable_change_store:
|
|||
csrrd ra, EXCEPTION_KS2
|
||||
ertn
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
vmalloc_store:
|
||||
la_abs t1, swapper_pg_dir
|
||||
b vmalloc_done_store
|
||||
#endif
|
||||
|
||||
/* This is the entry point of a huge page. */
|
||||
tlb_huge_update_store:
|
||||
#ifdef CONFIG_SMP
|
||||
ll.d ra, t1, 0
|
||||
PTE_LL ra, t1, 0
|
||||
#else
|
||||
rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1)
|
||||
PTR_ROTRI ra, ra, BITS_PER_LONG - (_PAGE_HUGE_SHIFT + 1)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
andi t0, ra, _PAGE_PRESENT | _PAGE_WRITE
|
||||
xori t0, t0, _PAGE_PRESENT | _PAGE_WRITE
|
||||
#else
|
||||
PTR_LI t0, _PAGE_PRESENT | _PAGE_WRITE
|
||||
and t0, t0, ra
|
||||
nor t0, t0, zero
|
||||
#endif
|
||||
|
||||
bnez t0, nopage_tlb_store
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
|
||||
sc.d t0, t1, 0
|
||||
PTE_SC t0, t1, 0
|
||||
beqz t0, tlb_huge_update_store
|
||||
ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
|
||||
#else
|
||||
#ifdef CONFIG_64BIT
|
||||
ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
|
||||
st.d t0, t1, 0
|
||||
#else
|
||||
PTR_LI t0, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
|
||||
or t0, ra, t0
|
||||
#endif
|
||||
PTR_S t0, t1, 0
|
||||
#endif
|
||||
csrrd ra, LOONGARCH_CSR_ASID
|
||||
csrrd t1, LOONGARCH_CSR_BADV
|
||||
|
|
@ -316,28 +360,28 @@ tlb_huge_update_store:
|
|||
xori t0, t0, _PAGE_HUGE
|
||||
lu12i.w t1, _PAGE_HGLOBAL >> 12
|
||||
and t1, t0, t1
|
||||
srli.d t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT)
|
||||
PTR_SRLI t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT)
|
||||
or t0, t0, t1
|
||||
|
||||
move ra, t0
|
||||
csrwr ra, LOONGARCH_CSR_TLBELO0
|
||||
|
||||
/* Convert to entrylo1 */
|
||||
addi.d t1, zero, 1
|
||||
slli.d t1, t1, (HPAGE_SHIFT - 1)
|
||||
add.d t0, t0, t1
|
||||
PTR_ADDI t1, zero, 1
|
||||
PTR_SLLI t1, t1, (HPAGE_SHIFT - 1)
|
||||
PTR_ADD t0, t0, t1
|
||||
csrwr t0, LOONGARCH_CSR_TLBELO1
|
||||
|
||||
/* Set huge page tlb entry size */
|
||||
addu16i.d t0, zero, (CSR_TLBIDX_PS >> 16)
|
||||
addu16i.d t1, zero, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT - 16))
|
||||
PTR_LI t0, (CSR_TLBIDX_PS >> 16) << 16
|
||||
PTR_LI t1, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT))
|
||||
csrxchg t1, t0, LOONGARCH_CSR_TLBIDX
|
||||
|
||||
tlbfill
|
||||
|
||||
/* Reset default page size */
|
||||
addu16i.d t0, zero, (CSR_TLBIDX_PS >> 16)
|
||||
addu16i.d t1, zero, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT - 16))
|
||||
PTR_LI t0, (CSR_TLBIDX_PS >> 16) << 16
|
||||
PTR_LI t1, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT))
|
||||
csrxchg t1, t0, LOONGARCH_CSR_TLBIDX
|
||||
|
||||
csrrd t0, EXCEPTION_KS0
|
||||
|
|
@ -375,52 +419,69 @@ SYM_CODE_START(handle_tlb_modify)
|
|||
|
||||
vmalloc_done_modify:
|
||||
/* Get PGD offset in bytes */
|
||||
bstrpick.d ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT
|
||||
alsl.d t1, ra, t1, 3
|
||||
#ifdef CONFIG_32BIT
|
||||
PTR_BSTRPICK ra, t0, 31, PGDIR_SHIFT
|
||||
#else
|
||||
PTR_BSTRPICK ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT
|
||||
#endif
|
||||
PTR_ALSL t1, ra, t1, _PGD_T_LOG2
|
||||
|
||||
#if CONFIG_PGTABLE_LEVELS > 3
|
||||
ld.d t1, t1, 0
|
||||
bstrpick.d ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT
|
||||
alsl.d t1, ra, t1, 3
|
||||
PTR_L t1, t1, 0
|
||||
PTR_BSTRPICK ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT
|
||||
PTR_ALSL t1, ra, t1, _PMD_T_LOG2
|
||||
#endif
|
||||
#if CONFIG_PGTABLE_LEVELS > 2
|
||||
ld.d t1, t1, 0
|
||||
bstrpick.d ra, t0, PTRS_PER_PMD_BITS + PMD_SHIFT - 1, PMD_SHIFT
|
||||
alsl.d t1, ra, t1, 3
|
||||
PTR_L t1, t1, 0
|
||||
PTR_BSTRPICK ra, t0, PTRS_PER_PMD_BITS + PMD_SHIFT - 1, PMD_SHIFT
|
||||
PTR_ALSL t1, ra, t1, _PMD_T_LOG2
|
||||
#endif
|
||||
ld.d ra, t1, 0
|
||||
PTR_L ra, t1, 0
|
||||
|
||||
/*
|
||||
* For huge tlb entries, pmde doesn't contain an address but
|
||||
* instead contains the tlb pte. Check the PAGE_HUGE bit and
|
||||
* see if we need to jump to huge tlb processing.
|
||||
*/
|
||||
rotri.d ra, ra, _PAGE_HUGE_SHIFT + 1
|
||||
PTR_ROTRI ra, ra, _PAGE_HUGE_SHIFT + 1
|
||||
bltz ra, tlb_huge_update_modify
|
||||
|
||||
rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1)
|
||||
bstrpick.d t0, t0, PTRS_PER_PTE_BITS + PAGE_SHIFT - 1, PAGE_SHIFT
|
||||
alsl.d t1, t0, ra, _PTE_T_LOG2
|
||||
PTR_ROTRI ra, ra, BITS_PER_LONG - (_PAGE_HUGE_SHIFT + 1)
|
||||
PTR_BSTRPICK t0, t0, PTRS_PER_PTE_BITS + PAGE_SHIFT - 1, PAGE_SHIFT
|
||||
PTR_ALSL t1, t0, ra, _PTE_T_LOG2
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
smp_pgtable_change_modify:
|
||||
ll.d t0, t1, 0
|
||||
PTE_LL t0, t1, 0
|
||||
#else
|
||||
ld.d t0, t1, 0
|
||||
PTR_L t0, t1, 0
|
||||
#endif
|
||||
#ifdef CONFIG_64BIT
|
||||
andi ra, t0, _PAGE_WRITE
|
||||
#else
|
||||
PTR_LI ra, _PAGE_WRITE
|
||||
and ra, t0, ra
|
||||
#endif
|
||||
|
||||
beqz ra, nopage_tlb_modify
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
ori t0, t0, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
|
||||
#else
|
||||
PTR_LI ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
|
||||
or t0, ra, t0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
sc.d t0, t1, 0
|
||||
PTE_SC t0, t1, 0
|
||||
beqz t0, smp_pgtable_change_modify
|
||||
#else
|
||||
st.d t0, t1, 0
|
||||
PTR_S t0, t1, 0
|
||||
#endif
|
||||
tlbsrch
|
||||
bstrins.d t1, zero, 3, 3
|
||||
ld.d t0, t1, 0
|
||||
ld.d t1, t1, 8
|
||||
PTR_BSTRINS t1, zero, _PTE_T_LOG2, _PTE_T_LOG2
|
||||
PTR_L t0, t1, 0
|
||||
PTR_L t1, t1, _PTE_T_SIZE
|
||||
csrwr t0, LOONGARCH_CSR_TLBELO0
|
||||
csrwr t1, LOONGARCH_CSR_TLBELO1
|
||||
tlbwr
|
||||
|
|
@ -430,30 +491,40 @@ smp_pgtable_change_modify:
|
|||
csrrd ra, EXCEPTION_KS2
|
||||
ertn
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
vmalloc_modify:
|
||||
la_abs t1, swapper_pg_dir
|
||||
b vmalloc_done_modify
|
||||
#endif
|
||||
|
||||
/* This is the entry point of a huge page. */
|
||||
tlb_huge_update_modify:
|
||||
#ifdef CONFIG_SMP
|
||||
ll.d ra, t1, 0
|
||||
PTE_LL ra, t1, 0
|
||||
#else
|
||||
rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1)
|
||||
PTR_ROTRI ra, ra, BITS_PER_LONG - (_PAGE_HUGE_SHIFT + 1)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
andi t0, ra, _PAGE_WRITE
|
||||
#else
|
||||
PTR_LI t0, _PAGE_WRITE
|
||||
and t0, ra, t0
|
||||
#endif
|
||||
|
||||
beqz t0, nopage_tlb_modify
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
|
||||
sc.d t0, t1, 0
|
||||
PTE_SC t0, t1, 0
|
||||
beqz t0, tlb_huge_update_modify
|
||||
ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
|
||||
#else
|
||||
#ifdef CONFIG_64BIT
|
||||
ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
|
||||
st.d t0, t1, 0
|
||||
#else
|
||||
PTR_LI t0, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
|
||||
or t0, ra, t0
|
||||
#endif
|
||||
PTR_S t0, t1, 0
|
||||
#endif
|
||||
csrrd ra, LOONGARCH_CSR_ASID
|
||||
csrrd t1, LOONGARCH_CSR_BADV
|
||||
|
|
@ -473,28 +544,28 @@ tlb_huge_update_modify:
|
|||
xori t0, t0, _PAGE_HUGE
|
||||
lu12i.w t1, _PAGE_HGLOBAL >> 12
|
||||
and t1, t0, t1
|
||||
srli.d t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT)
|
||||
PTR_SRLI t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT)
|
||||
or t0, t0, t1
|
||||
|
||||
move ra, t0
|
||||
csrwr ra, LOONGARCH_CSR_TLBELO0
|
||||
|
||||
/* Convert to entrylo1 */
|
||||
addi.d t1, zero, 1
|
||||
slli.d t1, t1, (HPAGE_SHIFT - 1)
|
||||
add.d t0, t0, t1
|
||||
PTR_ADDI t1, zero, 1
|
||||
PTR_SLLI t1, t1, (HPAGE_SHIFT - 1)
|
||||
PTR_ADD t0, t0, t1
|
||||
csrwr t0, LOONGARCH_CSR_TLBELO1
|
||||
|
||||
/* Set huge page tlb entry size */
|
||||
addu16i.d t0, zero, (CSR_TLBIDX_PS >> 16)
|
||||
addu16i.d t1, zero, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT - 16))
|
||||
PTR_LI t0, (CSR_TLBIDX_PS >> 16) << 16
|
||||
PTR_LI t1, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT))
|
||||
csrxchg t1, t0, LOONGARCH_CSR_TLBIDX
|
||||
|
||||
tlbfill
|
||||
|
||||
/* Reset default page size */
|
||||
addu16i.d t0, zero, (CSR_TLBIDX_PS >> 16)
|
||||
addu16i.d t1, zero, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT - 16))
|
||||
PTR_LI t0, (CSR_TLBIDX_PS >> 16) << 16
|
||||
PTR_LI t1, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT))
|
||||
csrxchg t1, t0, LOONGARCH_CSR_TLBIDX
|
||||
|
||||
csrrd t0, EXCEPTION_KS0
|
||||
|
|
@ -517,6 +588,44 @@ SYM_CODE_START(handle_tlb_modify_ptw)
|
|||
jr t0
|
||||
SYM_CODE_END(handle_tlb_modify_ptw)
|
||||
|
||||
#ifdef CONFIG_32BIT
|
||||
SYM_CODE_START(handle_tlb_refill)
|
||||
UNWIND_HINT_UNDEFINED
|
||||
csrwr t0, EXCEPTION_KS0
|
||||
csrwr t1, EXCEPTION_KS1
|
||||
csrwr ra, EXCEPTION_KS2
|
||||
li.w ra, 0x1fffffff
|
||||
|
||||
csrrd t0, LOONGARCH_CSR_PGD
|
||||
csrrd t1, LOONGARCH_CSR_TLBRBADV
|
||||
srli.w t1, t1, PGDIR_SHIFT
|
||||
slli.w t1, t1, 0x2
|
||||
add.w t0, t0, t1
|
||||
and t0, t0, ra
|
||||
|
||||
ld.w t0, t0, 0
|
||||
csrrd t1, LOONGARCH_CSR_TLBRBADV
|
||||
slli.w t1, t1, (32 - PGDIR_SHIFT)
|
||||
srli.w t1, t1, (32 - PGDIR_SHIFT + PAGE_SHIFT + 1)
|
||||
slli.w t1, t1, (0x2 + 1)
|
||||
add.w t0, t0, t1
|
||||
and t0, t0, ra
|
||||
|
||||
ld.w t1, t0, 0x0
|
||||
csrwr t1, LOONGARCH_CSR_TLBRELO0
|
||||
|
||||
ld.w t1, t0, 0x4
|
||||
csrwr t1, LOONGARCH_CSR_TLBRELO1
|
||||
|
||||
tlbfill
|
||||
csrrd t0, EXCEPTION_KS0
|
||||
csrrd t1, EXCEPTION_KS1
|
||||
csrrd ra, EXCEPTION_KS2
|
||||
ertn
|
||||
SYM_CODE_END(handle_tlb_refill)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
SYM_CODE_START(handle_tlb_refill)
|
||||
UNWIND_HINT_UNDEFINED
|
||||
csrwr t0, LOONGARCH_CSR_TLBRSAVE
|
||||
|
|
@ -534,3 +643,4 @@ SYM_CODE_START(handle_tlb_refill)
|
|||
csrrd t0, LOONGARCH_CSR_TLBRSAVE
|
||||
ertn
|
||||
SYM_CODE_END(handle_tlb_refill)
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue