From aee8c4d9d48d661624d72de670ebe5c6b5687842 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 5 Nov 2025 18:27:00 +0100 Subject: [PATCH 01/16] mtd: spi-nor: winbond: Add support for W25Q01NWxxIQ chips This chip must be described as none of the block protection information are discoverable. This chip supports 4 bits plus the top/bottom addressing capability to identify the protected blocks. Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal Reviewed-by: Michael Walle Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/winbond.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 63a93c9eb917..a13a1201eae9 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -343,6 +343,10 @@ static const struct flash_info winbond_nor_parts[] = { .id = SNOR_ID(0xef, 0x80, 0x20), .name = "w25q512nwm", .otp = SNOR_OTP(256, 3, 0x1000, 0x1000), + }, { + /* W25Q01NWxxIQ */ + .id = SNOR_ID(0xef, 0x60, 0x21), + .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP, }, }; From a607e676c8b9258eabc3fc88f45bcd70ea178b41 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 5 Nov 2025 18:27:01 +0100 Subject: [PATCH 02/16] mtd: spi-nor: winbond: Add support for W25Q01NWxxIM chips These chips must be described as none of the block protection information are discoverable. This chip supports 4 bits plus the top/bottom addressing capability to identify the protected blocks. Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal Reviewed-by: Michael Walle Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/winbond.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index a13a1201eae9..580c9cb37958 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -347,6 +347,10 @@ static const struct flash_info winbond_nor_parts[] = { /* W25Q01NWxxIQ */ .id = SNOR_ID(0xef, 0x60, 0x21), .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP, + }, { + /* W25Q01NWxxIM */ + .id = SNOR_ID(0xef, 0x80, 0x21), + .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP, }, }; From 71c239348d9fbdb1f0d6f36013f1697cc06c3e9c Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 5 Nov 2025 18:27:02 +0100 Subject: [PATCH 03/16] mtd: spi-nor: winbond: Add support for W25Q02NWxxIM chips These chips must be described as none of the block protection information are discoverable. This chip supports 4 bits plus the top/bottom addressing capability to identify the protected blocks. Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal Reviewed-by: Michael Walle Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/winbond.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 580c9cb37958..a65cbbccbbac 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -351,6 +351,10 @@ static const struct flash_info winbond_nor_parts[] = { /* W25Q01NWxxIM */ .id = SNOR_ID(0xef, 0x80, 0x21), .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP, + }, { + /* W25Q02NWxxIM */ + .id = SNOR_ID(0xef, 0x80, 0x22), + .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP, }, }; From f21d2c7d37553b24825918f2f61df123e182b712 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 5 Nov 2025 18:27:03 +0100 Subject: [PATCH 04/16] mtd: spi-nor: winbond: Add support for W25H512NWxxAM chips These chips must be described as none of the block protection information are discoverable. This chip supports 4 bits plus the top/bottom addressing capability to identify the protected blocks. Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal Reviewed-by: Michael Walle Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/winbond.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index a65cbbccbbac..781ca0abfcdc 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -355,6 +355,10 @@ static const struct flash_info winbond_nor_parts[] = { /* W25Q02NWxxIM */ .id = SNOR_ID(0xef, 0x80, 0x22), .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP, + }, { + /* W25H512NWxxAM */ + .id = SNOR_ID(0xef, 0xa0, 0x20), + .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP, }, }; From 1df1fdbc7e63350b2962dc7d87ded124ee26f3ad Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 5 Nov 2025 18:27:04 +0100 Subject: [PATCH 05/16] mtd: spi-nor: winbond: Add support for W25H01NWxxAM chips These chips must be described as none of the block protection information are discoverable. This chip supports 4 bits plus the top/bottom addressing capability to identify the protected blocks. Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal Reviewed-by: Michael Walle Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/winbond.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 781ca0abfcdc..338e44db506a 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -359,6 +359,10 @@ static const struct flash_info winbond_nor_parts[] = { /* W25H512NWxxAM */ .id = SNOR_ID(0xef, 0xa0, 0x20), .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP, + }, { + /* W25H01NWxxAM */ + .id = SNOR_ID(0xef, 0xa0, 0x21), + .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP, }, }; From 604cf6a40157abba4677dea9834de8df9047d798 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 5 Nov 2025 18:27:05 +0100 Subject: [PATCH 06/16] mtd: spi-nor: winbond: Add support for W25H02NWxxAM chips These chips must be described as none of the block protection information are discoverable. This chip supports 4 bits plus the top/bottom addressing capability to identify the protected blocks. Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal Reviewed-by: Michael Walle Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/winbond.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 338e44db506a..fb855fe44733 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -363,6 +363,10 @@ static const struct flash_info winbond_nor_parts[] = { /* W25H01NWxxAM */ .id = SNOR_ID(0xef, 0xa0, 0x21), .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP, + }, { + /* W25H02NWxxAM */ + .id = SNOR_ID(0xef, 0xa0, 0x22), + .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP, }, }; From 653f6def567c81f37302f9591ffd54df3e2a11eb Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Wed, 5 Nov 2025 16:47:58 +0900 Subject: [PATCH 07/16] mtd: spi-nor: sfdp: introduce smpt_read_dummy fixup hook SMPT contains config detection info that describes opcode, address, and dummy cycles to read sector map config. The dummy cycles parameter can be SMPT_CMD_READ_DUMMY_IS_VARIABLE and in that case nor->read_dummy (initialized as 0) is used. In Infineon flash chips, Read Any Register command with variable dummy cycle is defined in SMPT. S25Hx/S28Hx flash has 0 dummy cycle by default to read volatile regiters and nor->read_dummy can work. S25FS-S flash has 8 dummy cycles so we need a hook that can fix dummy cycles with actually used value. Inroduce smpt_read_dummy() in struct spi_nor_fixups. It is called when the dummy cycle field in SMPT config detection is 'varialble'. Reviewed-by: Tudor Ambarus Tested-by: Marek Vasut # S25FS512S Signed-off-by: Takahiro Kuwano Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.h | 3 +++ drivers/mtd/spi-nor/sfdp.c | 18 ++++++++++++++++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index ceff412f7d65..5ad46d95d09c 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -409,6 +409,8 @@ struct spi_nor_flash_parameter { * flash parameters when information provided by the flash_info * table is incomplete or wrong. * @post_bfpt: called after the BFPT table has been parsed + * @smpt_read_dummy: called during SMPT table is being parsed. Used to fix the + * number of dummy cycles in read register ops. * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs * that do not support RDSFDP). Typically used to tweak various * parameters that could not be extracted by other means (i.e. @@ -426,6 +428,7 @@ struct spi_nor_fixups { int (*post_bfpt)(struct spi_nor *nor, const struct sfdp_parameter_header *bfpt_header, const struct sfdp_bfpt *bfpt); + void (*smpt_read_dummy)(const struct spi_nor *nor, u8 *read_dummy); int (*post_sfdp)(struct spi_nor *nor); int (*late_init)(struct spi_nor *nor); }; diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 21727f9a4ac6..9a47dcaca06a 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -699,6 +699,17 @@ static u8 spi_nor_smpt_addr_nbytes(const struct spi_nor *nor, const u32 settings } } +static void spi_nor_smpt_read_dummy_fixups(const struct spi_nor *nor, + u8 *read_dummy) +{ + if (nor->manufacturer && nor->manufacturer->fixups && + nor->manufacturer->fixups->smpt_read_dummy) + nor->manufacturer->fixups->smpt_read_dummy(nor, read_dummy); + + if (nor->info->fixups && nor->info->fixups->smpt_read_dummy) + nor->info->fixups->smpt_read_dummy(nor, read_dummy); +} + /** * spi_nor_smpt_read_dummy() - return the configuration detection command read * latency, in clock cycles. @@ -711,8 +722,11 @@ static u8 spi_nor_smpt_read_dummy(const struct spi_nor *nor, const u32 settings) { u8 read_dummy = SMPT_CMD_READ_DUMMY(settings); - if (read_dummy == SMPT_CMD_READ_DUMMY_IS_VARIABLE) - return nor->read_dummy; + if (read_dummy == SMPT_CMD_READ_DUMMY_IS_VARIABLE) { + read_dummy = nor->read_dummy; + spi_nor_smpt_read_dummy_fixups(nor, &read_dummy); + } + return read_dummy; } From f74de390557bf2bcc5dca4a357b41c0701d3f76e Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Wed, 5 Nov 2025 16:47:59 +0900 Subject: [PATCH 08/16] mtd: spi-nor: sfdp: introduce smpt_map_id fixup hook Certain chips have inconsistent Sector Map Parameter Table (SMPT) data, which leads to the wrong map ID being identified, causing failures to detect the correct sector map. To fix this, introduce smpt_map_id() into the struct spi_nor_fixups. This function will be called after the initial SMPT-based detection, allowing chip-specific logic to correct the map ID. Infineon S25FS512S needs this fixup as it has inconsistency between map ID definition and configuration register value actually obtained. Co-developed-by: Marek Vasut Signed-off-by: Marek Vasut Reviewed-by: Tudor Ambarus Tested-by: Marek Vasut # S25FS512S Signed-off-by: Takahiro Kuwano Reviewed-by: Tudor Ambarus > Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.h | 3 +++ drivers/mtd/spi-nor/sfdp.c | 12 ++++++++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 5ad46d95d09c..16b382d4f04f 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -411,6 +411,8 @@ struct spi_nor_flash_parameter { * @post_bfpt: called after the BFPT table has been parsed * @smpt_read_dummy: called during SMPT table is being parsed. Used to fix the * number of dummy cycles in read register ops. + * @smpt_map_id: called after map ID in SMPT table has been determined for the + * case the map ID is wrong and needs to be fixed. * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs * that do not support RDSFDP). Typically used to tweak various * parameters that could not be extracted by other means (i.e. @@ -429,6 +431,7 @@ struct spi_nor_fixups { const struct sfdp_parameter_header *bfpt_header, const struct sfdp_bfpt *bfpt); void (*smpt_read_dummy)(const struct spi_nor *nor, u8 *read_dummy); + void (*smpt_map_id)(const struct spi_nor *nor, u8 *map_id); int (*post_sfdp)(struct spi_nor *nor); int (*late_init)(struct spi_nor *nor); }; diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 9a47dcaca06a..a8324c2da0ac 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -730,6 +730,16 @@ static u8 spi_nor_smpt_read_dummy(const struct spi_nor *nor, const u32 settings) return read_dummy; } +static void spi_nor_smpt_map_id_fixups(const struct spi_nor *nor, u8 *map_id) +{ + if (nor->manufacturer && nor->manufacturer->fixups && + nor->manufacturer->fixups->smpt_map_id) + nor->manufacturer->fixups->smpt_map_id(nor, map_id); + + if (nor->info->fixups && nor->info->fixups->smpt_map_id) + nor->info->fixups->smpt_map_id(nor, map_id); +} + /** * spi_nor_get_map_in_use() - get the configuration map in use * @nor: pointer to a 'struct spi_nor' @@ -783,6 +793,8 @@ static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32 *smpt, map_id = map_id << 1 | !!(*buf & read_data_mask); } + spi_nor_smpt_map_id_fixups(nor, &map_id); + /* * If command descriptors are provided, they always precede map * descriptors in the table. There is no need to start the iteration From e8f288a115f4850a65063af8787545dbf50abf47 Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Wed, 5 Nov 2025 16:48:00 +0900 Subject: [PATCH 09/16] mtd: spi-nor: spansion: SMPT fixups for S25FS-S S25FS-S family supports SMPT that helps to detect sector layout settings in configuration registers, but some of parameters in the table are wrong or undetermined so the fixups below are required. Read Any Register op is used to read configuration registers that related to sector map. The op requires 8 cycles latency by default. Implement smpt_read_dummy() to set correct dummy cycles. Map ID is structured by combination of CR3NV[3], CR1NV[2], and CR3NV[1]. However, in S25FS512S, CR3NV[1] is RFU and always 0, while map IDs defined in the table assume it is always 1. Implement smpt_map_id() to fix map ID for S25FS512S. Other densities in S25FS-S family (256Mb and 128Mb) don't need this fix as CR3NV[1] in those chips is configurable and map IDs are correctly defined in SMPT. Co-developed-by: Marek Vasut Signed-off-by: Marek Vasut Reviewed-by: Tudor Ambarus Tested-by: Marek Vasut # S25FS512S Signed-off-by: Takahiro Kuwano Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/spansion.c | 38 ++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index a0296c871634..8498c7003d88 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -785,8 +785,46 @@ s25fs_s_nor_post_bfpt_fixups(struct spi_nor *nor, return 0; } +static void s25fs_s_nor_smpt_read_dummy(const struct spi_nor *nor, + u8 *read_dummy) +{ + /* + * The configuration detection dwords in S25FS-S SMPT has 65h as + * command instruction and 'variable' as configuration detection command + * latency. Set 8 dummy cycles as it is factory default for 65h (read + * any register) op. + */ + *read_dummy = 8; +} + +static void s25fs_s_nor_smpt_map_id_dummy(const struct spi_nor *nor, u8 *map_id) +{ + /* + * The S25FS512S chip supports: + * - Hybrid sector option which has physical set of eight 4-KB sectors + * and one 224-KB sector at the top or bottom of address space with + * all remaining sectors of 256-KB + * - Uniform sector option which has uniform 256-KB sectors + * + * On the other hand, the datasheet rev.O Table 71 on page 153 JEDEC + * Sector Map Parameter Dword-6 Config. Detect-3 does use CR3NV[1] to + * discern 64-KB(CR3NV[1]=0) and 256-KB(CR3NV[1]=1) uniform sectors + * device configuration. And in section 7.5.5.1 Configuration Register 3 + * Non-volatile (CR3NV) page 61, the CR3NV[1] is RFU Reserved for Future + * Use and set to 0, which means 64-KB uniform. Since the device does + * not support 64-KB uniform sectors in any configuration, parsing SMPT + * table cannot find a valid sector map entry and fails. Fix this up by + * setting SMPT by overwriting the CR3NV[1] value to 1, as the table + * expects. + */ + if (nor->params->size == SZ_64M) + *map_id |= BIT(0); +} + static const struct spi_nor_fixups s25fs_s_nor_fixups = { .post_bfpt = s25fs_s_nor_post_bfpt_fixups, + .smpt_read_dummy = s25fs_s_nor_smpt_read_dummy, + .smpt_map_id = s25fs_s_nor_smpt_map_id_dummy, }; static const struct flash_info spansion_nor_parts[] = { From 74883accfa4a717337413c3ca243e997cc384a55 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Wed, 12 Nov 2025 19:05:09 +0800 Subject: [PATCH 10/16] mtd: spi-nor: micron-st: rename the die_late_init functions st_nor_two/four_die_late_init() also suit for micron chips, so rename to micron_st_nor_two/four_die_late_init(), and move these functions up, then micron can use these function without declaration. Reviewed-by: Tudor Ambarus Signed-off-by: Haibo Chen Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/micron-st.c | 70 ++++++++++++++++----------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index 187239ccd549..92eb14ca76c5 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -127,6 +127,38 @@ static int micron_st_nor_set_octal_dtr(struct spi_nor *nor, bool enable) micron_st_nor_octal_dtr_dis(nor); } +static int micron_st_nor_four_die_late_init(struct spi_nor *nor) +{ + struct spi_nor_flash_parameter *params = nor->params; + + params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE; + params->n_dice = 4; + + /* + * Unfortunately the die erase opcode does not have a 4-byte opcode + * correspondent for these flashes. The SFDP 4BAIT table fails to + * consider the die erase too. We're forced to enter in the 4 byte + * address mode in order to benefit of the die erase. + */ + return spi_nor_set_4byte_addr_mode(nor, true); +} + +static int micron_st_nor_two_die_late_init(struct spi_nor *nor) +{ + struct spi_nor_flash_parameter *params = nor->params; + + params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE; + params->n_dice = 2; + + /* + * Unfortunately the die erase opcode does not have a 4-byte opcode + * correspondent for these flashes. The SFDP 4BAIT table fails to + * consider the die erase too. We're forced to enter in the 4 byte + * address mode in order to benefit of the die erase. + */ + return spi_nor_set_4byte_addr_mode(nor, true); +} + static void mt35xu512aba_default_init(struct spi_nor *nor) { nor->params->set_octal_dtr = micron_st_nor_set_octal_dtr; @@ -193,48 +225,16 @@ static const struct spi_nor_fixups mt25qu512a_fixups = { .post_bfpt = mt25qu512a_post_bfpt_fixup, }; -static int st_nor_four_die_late_init(struct spi_nor *nor) -{ - struct spi_nor_flash_parameter *params = nor->params; - - params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE; - params->n_dice = 4; - - /* - * Unfortunately the die erase opcode does not have a 4-byte opcode - * correspondent for these flashes. The SFDP 4BAIT table fails to - * consider the die erase too. We're forced to enter in the 4 byte - * address mode in order to benefit of the die erase. - */ - return spi_nor_set_4byte_addr_mode(nor, true); -} - -static int st_nor_two_die_late_init(struct spi_nor *nor) -{ - struct spi_nor_flash_parameter *params = nor->params; - - params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE; - params->n_dice = 2; - - /* - * Unfortunately the die erase opcode does not have a 4-byte opcode - * correspondent for these flashes. The SFDP 4BAIT table fails to - * consider the die erase too. We're forced to enter in the 4 byte - * address mode in order to benefit of the die erase. - */ - return spi_nor_set_4byte_addr_mode(nor, true); -} - static const struct spi_nor_fixups n25q00_fixups = { - .late_init = st_nor_four_die_late_init, + .late_init = micron_st_nor_four_die_late_init, }; static const struct spi_nor_fixups mt25q01_fixups = { - .late_init = st_nor_two_die_late_init, + .late_init = micron_st_nor_two_die_late_init, }; static const struct spi_nor_fixups mt25q02_fixups = { - .late_init = st_nor_four_die_late_init, + .late_init = micron_st_nor_four_die_late_init, }; static const struct flash_info st_nor_parts[] = { From 9437a14ae2167124ce8741aed8c8922de8ae01e5 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Wed, 12 Nov 2025 19:05:10 +0800 Subject: [PATCH 11/16] mtd: spi-nor: micron-st: move set_octal_dtr to late_init() Move params->set_octal_dtr from flash_info->fixups->default_init() to spi_nor_manufacturer-> fixups-> late_init(), this can cover all Micorn and ST chips without repeat in each chip's flash_info. Reviewed-by: Tudor Ambarus Signed-off-by: Haibo Chen Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/micron-st.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index 92eb14ca76c5..81a9bead1434 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -159,11 +159,6 @@ static int micron_st_nor_two_die_late_init(struct spi_nor *nor) return spi_nor_set_4byte_addr_mode(nor, true); } -static void mt35xu512aba_default_init(struct spi_nor *nor) -{ - nor->params->set_octal_dtr = micron_st_nor_set_octal_dtr; -} - static int mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor) { /* Set the Fast Read settings. */ @@ -187,7 +182,6 @@ static int mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor) } static const struct spi_nor_fixups mt35xu512aba_fixups = { - .default_init = mt35xu512aba_default_init, .post_sfdp = mt35xu512aba_post_sfdp_fixup, }; @@ -635,6 +629,8 @@ static int micron_st_nor_late_init(struct spi_nor *nor) if (!params->set_4byte_addr_mode) params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_wren_en4b_ex4b; + params->set_octal_dtr = micron_st_nor_set_octal_dtr; + return 0; } From 44dd635cd632824f412ff2a6b320d9302a277ad0 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Wed, 12 Nov 2025 19:05:11 +0800 Subject: [PATCH 12/16] mtd: spi-nor: micron-st: use SFDP of mt35xu512aba mt35xu512aba has SFDP, already contain the necessary information, so remove size and some flags here. Reviewed-by: Tudor Ambarus Signed-off-by: Haibo Chen Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/micron-st.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index 81a9bead1434..9a8f82045e4d 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -187,14 +187,10 @@ static const struct spi_nor_fixups mt35xu512aba_fixups = { static const struct flash_info micron_nor_parts[] = { { + /* MT35XU512ABA */ .id = SNOR_ID(0x2c, 0x5b, 0x1a), - .name = "mt35xu512aba", - .sector_size = SZ_128K, - .size = SZ_64M, - .no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ | - SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP, .mfr_flags = USE_FSR, - .fixup_flags = SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE, + .fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE, .fixups = &mt35xu512aba_fixups, }, { .id = SNOR_ID(0x2c, 0x5b, 0x1c), From a5dff51e190c20226cc5a6ade9a35fd71b22f42c Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Wed, 12 Nov 2025 19:05:12 +0800 Subject: [PATCH 13/16] mtd: spi-nor: micron-st: add mt35xu01gbba support mt35xu01gbba is similar with mt35xu512aba, but with two dies. mt35xu01gbba has SFDP and support 8D-8D-8D mode, but SFDP lack SNOR_F_IO_MODE_EN_VOLATILE, so add this fixup flags here. Besides, mt35xu01gbba do not support chip erase, but support die erase, so add that in late_init(). Link: https://datasheet.octopart.com/MT35XU02GCBA1G12-0AAT-Micron-datasheet-138896808.pdf Signed-off-by: Haibo Chen Reviewed-by: Tudor Ambarus Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/micron-st.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index 9a8f82045e4d..c89c06b1fc61 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -185,6 +185,11 @@ static const struct spi_nor_fixups mt35xu512aba_fixups = { .post_sfdp = mt35xu512aba_post_sfdp_fixup, }; +static const struct spi_nor_fixups mt35xu01gbba_fixups = { + .post_sfdp = mt35xu512aba_post_sfdp_fixup, + .late_init = micron_st_nor_two_die_late_init, +}; + static const struct flash_info micron_nor_parts[] = { { /* MT35XU512ABA */ @@ -192,6 +197,12 @@ static const struct flash_info micron_nor_parts[] = { .mfr_flags = USE_FSR, .fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE, .fixups = &mt35xu512aba_fixups, + }, { + /* MT35XU01GBBA */ + .id = SNOR_ID(0x2c, 0x5b, 0x1b), + .mfr_flags = USE_FSR, + .fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE, + .fixups = &mt35xu01gbba_fixups, }, { .id = SNOR_ID(0x2c, 0x5b, 0x1c), .name = "mt35xu02g", From 7f77c561e22783387af91cd16f3a4324a99c9a4f Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Wed, 12 Nov 2025 19:05:13 +0800 Subject: [PATCH 14/16] mtd: spi-nor: micron-st: add TODO for fixing mt35xu02gcba The MT35XU02GCBA flash device does not support chip erase, according to its datasheet. It supports die erase, which means the current driver implementation will likely need to be converted to use die erase. Furthermore, similar to the MT35XU01GBBA, the SPI_NOR_IO_MODE_EN_VOLATILE flag probably needs to be enabled. Currently no active contributor has access to this hardware so there is no way of testing the fixes. Add a TODO item on the flash entry so someone with the flash can test that the support is indeed broken and send the fixes. Link: https://datasheet.octopart.com/MT35XU02GCBA1G12-0AAT-Micron-datasheet-138896808.pdf Reviewed-by: Tudor Ambarus Signed-off-by: Haibo Chen [pratyush@kernel.org: refactor the comment and commit message to make the purpose of the comment clearer] Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/micron-st.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index c89c06b1fc61..88033384a71e 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -204,6 +204,16 @@ static const struct flash_info micron_nor_parts[] = { .fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE, .fixups = &mt35xu01gbba_fixups, }, { + /* + * The MT35XU02GCBA flash device does not support chip erase, + * according to its datasheet. It supports die erase, which + * means the current driver implementation will likely need to + * be converted to use die erase. Furthermore, similar to the + * MT35XU01GBBA, the SPI_NOR_IO_MODE_EN_VOLATILE flag probably + * needs to be enabled. + * + * TODO: Fix these and test on real hardware. + */ .id = SNOR_ID(0x2c, 0x5b, 0x1c), .name = "mt35xu02g", .sector_size = SZ_128K, From 5008c3ec3f891456e74f8dab882fcd5bc515d327 Mon Sep 17 00:00:00 2001 From: Jakub Czapiga Date: Fri, 19 Sep 2025 18:15:47 +0000 Subject: [PATCH 15/16] mtd: spi-nor: core: Check read CR support Some SPI controllers like Intel's one on the PCI bus do not support opcode 35h. This opcode is used to read the Configuration Register on SPI-NOR chips that have 16-bit Status Register configured regardless of the controller support for it. Adding a check call in the setup step allows disabling use of the 35h opcode and falling back to the manual Status Registers management. Before: openat(AT_FDCWD, "/dev/mtd0", O_RDWR) = 4 ioctl(4, MIXER_WRITE(6) or MEMUNLOCK, {start=0, length=0x2000000}) = -1 EOPNOTSUPP After: openat(AT_FDCWD, "/dev/mtd0", O_RDWR) = 4 ioctl(4, MIXER_WRITE(6) or MEMUNLOCK, {start=0, length=0x2000000}) = 0 ioctl(4, MIXER_WRITE(5) or MEMLOCK, {start=0x1800000, length=0x800000}) = 0 Suggested-by: Adeel Arshad Signed-off-by: Jakub Czapiga Reviewed-by: Pratyush Yadav Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 20ea80450f22..d3f8a78efd3b 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2459,6 +2459,16 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps) ¶ms->page_programs[ppidx])) *hwcaps &= ~BIT(cap); } + + /* Some SPI controllers might not support CR read opcode. */ + if (!(nor->flags & SNOR_F_NO_READ_CR)) { + struct spi_mem_op op = SPI_NOR_RDCR_OP(nor->bouncebuf); + + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); + + if (spi_nor_spimem_check_op(nor, &op)) + nor->flags |= SNOR_F_NO_READ_CR; + } } /** From ed26bd40df11ee438d623adc9c6cc2a7bf9c5dd3 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Tue, 25 Nov 2025 18:16:53 +0100 Subject: [PATCH 16/16] mailmap: update Pratyush Yadav's email address I will stop having access to my Amazon email soon. Map it to my kernel email. Signed-off-by: Pratyush Yadav --- .mailmap | 1 + 1 file changed, 1 insertion(+) diff --git a/.mailmap b/.mailmap index d2edd256b19d..cf42344098ff 100644 --- a/.mailmap +++ b/.mailmap @@ -632,6 +632,7 @@ Peter Oruba Peter Oruba Pierre-Louis Bossart Pratyush Anand +Pratyush Yadav Praveen BP Pradeep Kumar Chitrapu Prasad Sodagudi