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drm/amd/display: add debug option for ExtendedVBlank DLG adjust 

[why & how]
Add new option for debug usage

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
pull/477/merge
Muhammad Ahmed 2023-12-06 18:07:57 -05:00 committed by Alex Deucher
parent b588267507
commit ec39a6d003
2 changed files with 3 additions and 1 deletions
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1
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -979,6 +979,7 @@ struct dc_debug_options {
unsigned int ips2_eval_delay_us;
unsigned int ips2_entry_delay_us;
bool disable_timeout;
bool disable_extblankadj;
};
struct gpu_info_soc_bounding_box_v1_0;

3
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
View File

@ -2221,7 +2221,8 @@ void dcn20_optimize_bandwidth(
dc->clk_mgr,
context,
true);
if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) {
if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW &&
!dc->debug.disable_extblankadj) {
for (i = 0; i < dc->res_pool->pipe_count; ++i) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];