iommu/amd: Report SEV-TIO support
The SEV-TIO switch in the AMD BIOS is reported to the OS via the IOMMU Extended Feature 2 register (EFR2), bit 1. Add helper to parse the bit and report the feature presence. Signed-off-by: Alexey Kardashevskiy <aik@amd.com> Link: https://patch.msgid.link/20251202024449.542361-4-aik@amd.com Acked-by: Joerg Roedel <joerg.roedel@amd.com> Reviewed-by: Vasant Hegde <vasant.hegde@amd.com> Acked-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>pull/1354/merge
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c3859de858
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eeb934137d
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@ -107,6 +107,7 @@
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/* Extended Feature 2 Bits */
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/* Extended Feature 2 Bits */
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#define FEATURE_SEVSNPIO_SUP BIT_ULL(1)
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#define FEATURE_SNPAVICSUP GENMASK_ULL(7, 5)
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#define FEATURE_SNPAVICSUP GENMASK_ULL(7, 5)
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#define FEATURE_SNPAVICSUP_GAM(x) \
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#define FEATURE_SNPAVICSUP_GAM(x) \
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(FIELD_GET(FEATURE_SNPAVICSUP, x) == 0x1)
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(FIELD_GET(FEATURE_SNPAVICSUP, x) == 0x1)
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@ -2252,6 +2252,9 @@ static void print_iommu_info(void)
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if (check_feature(FEATURE_SNP))
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if (check_feature(FEATURE_SNP))
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pr_cont(" SNP");
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pr_cont(" SNP");
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if (check_feature2(FEATURE_SEVSNPIO_SUP))
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pr_cont(" SEV-TIO");
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pr_cont("\n");
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pr_cont("\n");
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}
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}
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@ -4015,4 +4018,10 @@ int amd_iommu_snp_disable(void)
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return 0;
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return 0;
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}
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}
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EXPORT_SYMBOL_GPL(amd_iommu_snp_disable);
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EXPORT_SYMBOL_GPL(amd_iommu_snp_disable);
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bool amd_iommu_sev_tio_supported(void)
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{
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return check_feature2(FEATURE_SEVSNPIO_SUP);
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}
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EXPORT_SYMBOL_GPL(amd_iommu_sev_tio_supported);
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#endif
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#endif
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@ -18,10 +18,12 @@ struct task_struct;
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struct pci_dev;
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struct pci_dev;
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extern void amd_iommu_detect(void);
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extern void amd_iommu_detect(void);
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extern bool amd_iommu_sev_tio_supported(void);
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#else /* CONFIG_AMD_IOMMU */
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#else /* CONFIG_AMD_IOMMU */
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static inline void amd_iommu_detect(void) { }
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static inline void amd_iommu_detect(void) { }
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static inline bool amd_iommu_sev_tio_supported(void) { return false; }
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#endif /* CONFIG_AMD_IOMMU */
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#endif /* CONFIG_AMD_IOMMU */
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