i2c-host for v6.17, part 2
- apple: add support for Apple A7–A11, T2 chips - qcom-geni: fix controller frequency mapping - stm32f7: add DMA-safe transfer support - tegra: use controller reset if device reset is missing - tegra: remove unnecessary dma_sync*() calls -----BEGIN PGP SIGNATURE----- iIwEABYKADQWIQScDfrjQa34uOld1VLaeAVmJtMtbgUCaI3XghYcYW5kaS5zaHl0 aUBrZXJuZWwub3JnAAoJENp4BWYm0y1u9moA/1bAEgLdl934yksPMliGIobJUj86 YuQHK0kloCsppJBVAP9o2pS7avHBeiPLJ89pwsMSu1s/yPm7NzO52Q/FYB3rCA== =jmKU -----END PGP SIGNATURE----- Merge tag 'i2c-host-6.17-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow i2c-host for v6.17, part 2 - apple: add support for Apple A7–A11, T2 chips - qcom-geni: fix controller frequency mapping - stm32f7: add DMA-safe transfer support - tegra: use controller reset if device reset is missing - tegra: remove unnecessary dma_sync*() callspull/1314/head
Wolfram Sang
commit
efb2ad898d
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@ -22,6 +22,11 @@ properties:
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compatible:
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items:
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- enum:
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- apple,s5l8960x-i2c
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- apple,t7000-i2c
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- apple,s8000-i2c
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- apple,t8010-i2c
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- apple,t8015-i2c
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- apple,t8103-i2c
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- apple,t8112-i2c
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- apple,t6000-i2c
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@ -155,9 +155,9 @@ static const struct geni_i2c_clk_fld geni_i2c_clk_map_19p2mhz[] = {
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/* source_clock = 32 MHz */
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static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = {
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{ I2C_MAX_STANDARD_MODE_FREQ, 8, 14, 18, 40 },
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{ I2C_MAX_FAST_MODE_FREQ, 4, 3, 11, 20 },
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{ I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 6, 15 },
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{ I2C_MAX_STANDARD_MODE_FREQ, 8, 14, 18, 38 },
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{ I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 19 },
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{ I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 5, 15 },
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{}
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};
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@ -742,11 +742,14 @@ static void stm32f7_i2c_dma_callback(void *arg)
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{
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struct stm32f7_i2c_dev *i2c_dev = arg;
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struct stm32_i2c_dma *dma = i2c_dev->dma;
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struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
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stm32f7_i2c_disable_dma_req(i2c_dev);
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dmaengine_terminate_async(dma->chan_using);
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dma_unmap_single(i2c_dev->dev, dma->dma_buf, dma->dma_len,
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dma->dma_data_dir);
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if (!f7_msg->smbus)
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i2c_put_dma_safe_msg_buf(f7_msg->buf, i2c_dev->msg, true);
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complete(&dma->dma_complete);
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}
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@ -882,6 +885,7 @@ static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
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{
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struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
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void __iomem *base = i2c_dev->base;
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u8 *dma_buf;
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u32 cr1, cr2;
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int ret;
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@ -931,17 +935,23 @@ static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
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/* Configure DMA or enable RX/TX interrupt */
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i2c_dev->use_dma = false;
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if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN
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&& !i2c_dev->atomic) {
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ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
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msg->flags & I2C_M_RD,
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f7_msg->count, f7_msg->buf,
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stm32f7_i2c_dma_callback,
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i2c_dev);
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if (!ret)
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i2c_dev->use_dma = true;
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else
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dev_warn(i2c_dev->dev, "can't use DMA\n");
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if (i2c_dev->dma && !i2c_dev->atomic) {
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dma_buf = i2c_get_dma_safe_msg_buf(msg, STM32F7_I2C_DMA_LEN_MIN);
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if (dma_buf) {
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f7_msg->buf = dma_buf;
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ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
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msg->flags & I2C_M_RD,
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f7_msg->count, f7_msg->buf,
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stm32f7_i2c_dma_callback,
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i2c_dev);
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if (ret) {
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dev_warn(i2c_dev->dev, "can't use DMA\n");
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i2c_put_dma_safe_msg_buf(f7_msg->buf, msg, false);
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f7_msg->buf = msg->buf;
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} else {
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i2c_dev->use_dma = true;
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}
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}
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}
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if (!i2c_dev->use_dma) {
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@ -134,6 +134,8 @@
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#define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16)
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#define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0)
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#define I2C_MASTER_RESET_CNTRL 0x0a8
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/* configuration load timeout in microseconds */
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#define I2C_CONFIG_LOAD_TIMEOUT 1000000
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@ -184,6 +186,9 @@ enum msg_end_type {
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* @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
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* provides additional features and allows for longer messages to
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* be transferred in one go.
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* @has_mst_reset: The I2C controller contains MASTER_RESET_CTRL register which
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* provides an alternative to controller reset when configured as
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* I2C master
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* @quirks: I2C adapter quirks for limiting write/read transfer size and not
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* allowing 0 length transfers.
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* @supports_bus_clear: Bus Clear support to recover from bus hang during
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@ -213,6 +218,7 @@ struct tegra_i2c_hw_feature {
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bool has_multi_master_mode;
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bool has_slcg_override_reg;
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bool has_mst_fifo;
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bool has_mst_reset;
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const struct i2c_adapter_quirks *quirks;
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bool supports_bus_clear;
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bool has_apb_dma;
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@ -605,12 +611,42 @@ static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
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return 0;
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}
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static int tegra_i2c_master_reset(struct tegra_i2c_dev *i2c_dev)
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{
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if (!i2c_dev->hw->has_mst_reset)
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return -EOPNOTSUPP;
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/*
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* Writing 1 to I2C_MASTER_RESET_CNTRL will reset all internal state of
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* Master logic including FIFOs. Clear this bit to 0 for normal operation.
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* SW needs to wait for 2us after assertion and de-assertion of this soft
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* reset.
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*/
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i2c_writel(i2c_dev, 0x1, I2C_MASTER_RESET_CNTRL);
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fsleep(2);
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i2c_writel(i2c_dev, 0x0, I2C_MASTER_RESET_CNTRL);
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fsleep(2);
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return 0;
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}
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static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
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{
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u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode;
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struct i2c_timings *t = &i2c_dev->timings;
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int err;
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/*
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* Reset the controller before initializing it.
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* In case if device_reset() returns -ENOENT, i.e. when the reset is
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* not available, the internal software reset will be used if it is
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* supported by the controller.
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*/
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err = device_reset(i2c_dev->dev);
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if (err == -ENOENT)
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err = tegra_i2c_master_reset(i2c_dev);
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/*
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* The reset shouldn't ever fail in practice. The failure will be a
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* sign of a severe problem that needs to be resolved. Still we don't
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@ -619,7 +655,6 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
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* emit a noisy warning on error, which won't stay unnoticed and
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* won't hose machine entirely.
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*/
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err = device_reset(i2c_dev->dev);
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WARN_ON_ONCE(err);
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if (IS_DVC(i2c_dev))
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@ -1266,17 +1301,9 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
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if (i2c_dev->dma_mode) {
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if (i2c_dev->msg_read) {
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dma_sync_single_for_device(i2c_dev->dma_dev,
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i2c_dev->dma_phys,
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xfer_size, DMA_FROM_DEVICE);
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err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
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if (err)
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return err;
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} else {
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dma_sync_single_for_cpu(i2c_dev->dma_dev,
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i2c_dev->dma_phys,
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xfer_size, DMA_TO_DEVICE);
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}
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}
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@ -1286,11 +1313,6 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
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if (i2c_dev->dma_mode) {
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memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE,
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msg->buf, i2c_dev->msg_len);
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dma_sync_single_for_device(i2c_dev->dma_dev,
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i2c_dev->dma_phys,
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xfer_size, DMA_TO_DEVICE);
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err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
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if (err)
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return err;
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@ -1331,13 +1353,8 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
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return -ETIMEDOUT;
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}
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if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) {
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dma_sync_single_for_cpu(i2c_dev->dma_dev,
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i2c_dev->dma_phys,
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xfer_size, DMA_FROM_DEVICE);
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if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE)
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memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, i2c_dev->msg_len);
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}
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}
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time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete,
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@ -1468,6 +1485,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
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.has_multi_master_mode = false,
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.has_slcg_override_reg = false,
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.has_mst_fifo = false,
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.has_mst_reset = false,
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.quirks = &tegra_i2c_quirks,
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.supports_bus_clear = false,
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.has_apb_dma = true,
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@ -1492,6 +1510,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
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.has_multi_master_mode = false,
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.has_slcg_override_reg = false,
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.has_mst_fifo = false,
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.has_mst_reset = false,
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.quirks = &tegra_i2c_quirks,
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.supports_bus_clear = false,
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.has_apb_dma = true,
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@ -1516,6 +1535,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
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.has_multi_master_mode = false,
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.has_slcg_override_reg = false,
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.has_mst_fifo = false,
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.has_mst_reset = false,
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.quirks = &tegra_i2c_quirks,
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.supports_bus_clear = true,
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.has_apb_dma = true,
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@ -1540,6 +1560,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
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.has_multi_master_mode = false,
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.has_slcg_override_reg = true,
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.has_mst_fifo = false,
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.has_mst_reset = false,
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.quirks = &tegra_i2c_quirks,
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.supports_bus_clear = true,
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.has_apb_dma = true,
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@ -1564,6 +1585,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
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.has_multi_master_mode = false,
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.has_slcg_override_reg = true,
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.has_mst_fifo = false,
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.has_mst_reset = false,
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.quirks = &tegra_i2c_quirks,
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.supports_bus_clear = true,
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.has_apb_dma = true,
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@ -1588,6 +1610,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
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.has_multi_master_mode = false,
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.has_slcg_override_reg = true,
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.has_mst_fifo = false,
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.has_mst_reset = false,
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.quirks = &tegra_i2c_quirks,
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.supports_bus_clear = true,
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.has_apb_dma = false,
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@ -1612,6 +1635,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
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.has_multi_master_mode = true,
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.has_slcg_override_reg = true,
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.has_mst_fifo = true,
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.has_mst_reset = true,
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.quirks = &tegra194_i2c_quirks,
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.supports_bus_clear = true,
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.has_apb_dma = false,
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Reference in New Issue