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drm/amdgpu: Check vcn sram load return value 

Log an error when vcn sram load fails in indirect mode
and return the same error value.

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
pull/1354/merge
Sathishkumar S 2025-07-13 01:28:02 +05:30 committed by Alex Deucher
parent 9d1ac25c7f
commit faab5ea083
8 changed files with 63 additions and 18 deletions
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10
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
View File

@ -865,6 +865,7 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
uint32_t rb_bufsz, tmp; uint32_t rb_bufsz, tmp;
int ret;
vcn_v2_0_enable_static_power_gating(vinst); vcn_v2_0_enable_static_power_gating(vinst);
@ -948,8 +949,13 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
UVD, 0, mmUVD_MASTINT_EN), UVD, 0, mmUVD_MASTINT_EN),
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
if (indirect) if (indirect) {
amdgpu_vcn_psp_update_sram(adev, 0, 0); ret = amdgpu_vcn_psp_update_sram(adev, 0, 0);
if (ret) {
dev_err(adev->dev, "vcn sram load failed %d\n", ret);
return ret;
}
}
/* force RBC into idle state */ /* force RBC into idle state */
rb_bufsz = order_base_2(ring->ring_size); rb_bufsz = order_base_2(ring->ring_size);

10
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
View File

@ -1035,6 +1035,7 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
struct amdgpu_ring *ring; struct amdgpu_ring *ring;
uint32_t rb_bufsz, tmp; uint32_t rb_bufsz, tmp;
int ret;
/* disable register anti-hang mechanism */ /* disable register anti-hang mechanism */
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,
@ -1125,8 +1126,13 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
VCN, 0, mmUVD_MASTINT_EN), VCN, 0, mmUVD_MASTINT_EN),
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
if (indirect) if (indirect) {
amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
if (ret) {
dev_err(adev->dev, "vcn sram load failed %d\n", ret);
return ret;
}
}
ring = &adev->vcn.inst[inst_idx].ring_dec; ring = &adev->vcn.inst[inst_idx].ring_dec;
/* force RBC into idle state */ /* force RBC into idle state */

10
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
View File

@ -1042,6 +1042,7 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
struct amdgpu_ring *ring; struct amdgpu_ring *ring;
uint32_t rb_bufsz, tmp; uint32_t rb_bufsz, tmp;
int ret;
/* disable register anti-hang mechanism */ /* disable register anti-hang mechanism */
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,
@ -1134,8 +1135,13 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
if (indirect) if (indirect) {
amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
if (ret) {
dev_err(adev->dev, "vcn sram load failed %d\n", ret);
return ret;
}
}
ring = &adev->vcn.inst[inst_idx].ring_dec; ring = &adev->vcn.inst[inst_idx].ring_dec;
/* force RBC into idle state */ /* force RBC into idle state */

10
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
View File

@ -1012,6 +1012,7 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
struct amdgpu_ring *ring; struct amdgpu_ring *ring;
uint32_t tmp; uint32_t tmp;
int ret;
/* disable register anti-hang mechanism */ /* disable register anti-hang mechanism */
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
@ -1094,8 +1095,13 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
if (indirect) if (indirect) {
amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
if (ret) {
dev_err(adev->dev, "vcn sram load failed %d\n", ret);
return ret;
}
}
ring = &adev->vcn.inst[inst_idx].ring_enc[0]; ring = &adev->vcn.inst[inst_idx].ring_enc[0];

11
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
View File

@ -851,7 +851,7 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
volatile struct amdgpu_vcn4_fw_shared *fw_shared = volatile struct amdgpu_vcn4_fw_shared *fw_shared =
adev->vcn.inst[inst_idx].fw_shared.cpu_addr; adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
struct amdgpu_ring *ring; struct amdgpu_ring *ring;
int vcn_inst; int vcn_inst, ret;
uint32_t tmp; uint32_t tmp;
vcn_inst = GET_INST(VCN, inst_idx); vcn_inst = GET_INST(VCN, inst_idx);
@ -944,8 +944,13 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
VCN, 0, regUVD_MASTINT_EN), VCN, 0, regUVD_MASTINT_EN),
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
if (indirect) if (indirect) {
amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM);
if (ret) {
dev_err(adev->dev, "vcn sram load failed %d\n", ret);
return ret;
}
}
ring = &adev->vcn.inst[inst_idx].ring_enc[0]; ring = &adev->vcn.inst[inst_idx].ring_enc[0];

10
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
View File

@ -926,6 +926,7 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
struct amdgpu_ring *ring; struct amdgpu_ring *ring;
uint32_t tmp; uint32_t tmp;
int ret;
/* disable register anti-hang mechanism */ /* disable register anti-hang mechanism */
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
@ -1006,8 +1007,13 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
VCN, inst_idx, regUVD_MASTINT_EN), VCN, inst_idx, regUVD_MASTINT_EN),
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
if (indirect) if (indirect) {
amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
if (ret) {
dev_err(adev->dev, "vcn sram load failed %d\n", ret);
return ret;
}
}
ring = &adev->vcn.inst[inst_idx].ring_enc[0]; ring = &adev->vcn.inst[inst_idx].ring_enc[0];

9
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
View File

@ -713,6 +713,7 @@ static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
volatile struct amdgpu_vcn5_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; volatile struct amdgpu_vcn5_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
struct amdgpu_ring *ring; struct amdgpu_ring *ring;
uint32_t tmp; uint32_t tmp;
int ret;
/* disable register anti-hang mechanism */ /* disable register anti-hang mechanism */
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
@ -766,8 +767,12 @@ static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
VCN, inst_idx, regUVD_MASTINT_EN), VCN, inst_idx, regUVD_MASTINT_EN),
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
if (indirect) if (indirect) {
amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
dev_err(adev->dev, "%s: vcn sram load failed %d\n", __func__, ret);
if (ret)
return ret;
}
ring = &adev->vcn.inst[inst_idx].ring_enc[0]; ring = &adev->vcn.inst[inst_idx].ring_enc[0];

11
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
View File

@ -605,7 +605,7 @@ static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
adev->vcn.inst[inst_idx].fw_shared.cpu_addr; adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
struct amdgpu_ring *ring; struct amdgpu_ring *ring;
struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__PAUSE}; struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__PAUSE};
int vcn_inst; int vcn_inst, ret;
uint32_t tmp; uint32_t tmp;
vcn_inst = GET_INST(VCN, inst_idx); vcn_inst = GET_INST(VCN, inst_idx);
@ -666,8 +666,13 @@ static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
VCN, 0, regUVD_MASTINT_EN), VCN, 0, regUVD_MASTINT_EN),
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
if (indirect) if (indirect) {
amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM);
if (ret) {
dev_err(adev->dev, "vcn sram load failed %d\n", ret);
return ret;
}
}
/* resetting ring, fw should not check RB ring */ /* resetting ring, fw should not check RB ring */
fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;