soundwire: intel: move bank switch routine to common intel_bus_common.c
No functionality change, just moving the routines to a common file so that they can be used for new hardware. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Rander Wang <rander.wang@intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Link: https://lore.kernel.org/r/20230314015410.487311-11-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>pull/795/merge
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1e76de2e5d
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fb43d62ee7
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@ -682,55 +682,6 @@ static int intel_free_stream(struct sdw_intel *sdw,
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return 0;
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return 0;
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}
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}
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/*
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* bank switch routines
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*/
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static int intel_pre_bank_switch(struct sdw_intel *sdw)
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{
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struct sdw_cdns *cdns = &sdw->cdns;
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struct sdw_bus *bus = &cdns->bus;
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/* Write to register only for multi-link */
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if (!bus->multi_link)
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return 0;
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sdw_intel_sync_arm(sdw);
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return 0;
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}
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static int intel_post_bank_switch(struct sdw_intel *sdw)
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{
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struct sdw_cdns *cdns = &sdw->cdns;
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struct sdw_bus *bus = &cdns->bus;
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int ret = 0;
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/* Write to register only for multi-link */
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if (!bus->multi_link)
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return 0;
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mutex_lock(sdw->link_res->shim_lock);
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/*
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* post_bank_switch() ops is called from the bus in loop for
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* all the Masters in the steam with the expectation that
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* we trigger the bankswitch for the only first Master in the list
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* and do nothing for the other Masters
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*
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* So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
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*/
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if (sdw_intel_sync_check_cmdsync_unlocked(sdw))
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ret = sdw_intel_sync_go_unlocked(sdw);
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mutex_unlock(sdw->link_res->shim_lock);
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if (ret < 0)
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dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
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return ret;
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}
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/*
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/*
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* DAI routines
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* DAI routines
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*/
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*/
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@ -201,4 +201,8 @@ void intel_check_clock_stop(struct sdw_intel *sdw);
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int intel_start_bus_after_clock_stop(struct sdw_intel *sdw);
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int intel_start_bus_after_clock_stop(struct sdw_intel *sdw);
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int intel_stop_bus(struct sdw_intel *sdw, bool clock_stop);
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int intel_stop_bus(struct sdw_intel *sdw, bool clock_stop);
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/* common bank switch routines */
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int intel_pre_bank_switch(struct sdw_intel *sdw);
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int intel_post_bank_switch(struct sdw_intel *sdw);
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#endif /* __SDW_INTEL_LOCAL_H */
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#endif /* __SDW_INTEL_LOCAL_H */
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@ -208,3 +208,52 @@ int intel_stop_bus(struct sdw_intel *sdw, bool clock_stop)
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return 0;
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return 0;
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}
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}
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/*
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* bank switch routines
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*/
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int intel_pre_bank_switch(struct sdw_intel *sdw)
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{
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struct sdw_cdns *cdns = &sdw->cdns;
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struct sdw_bus *bus = &cdns->bus;
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/* Write to register only for multi-link */
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if (!bus->multi_link)
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return 0;
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sdw_intel_sync_arm(sdw);
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return 0;
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}
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int intel_post_bank_switch(struct sdw_intel *sdw)
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{
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struct sdw_cdns *cdns = &sdw->cdns;
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struct sdw_bus *bus = &cdns->bus;
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int ret = 0;
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/* Write to register only for multi-link */
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if (!bus->multi_link)
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return 0;
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mutex_lock(sdw->link_res->shim_lock);
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/*
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* post_bank_switch() ops is called from the bus in loop for
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* all the Masters in the steam with the expectation that
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* we trigger the bankswitch for the only first Master in the list
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* and do nothing for the other Masters
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*
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* So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
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*/
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if (sdw_intel_sync_check_cmdsync_unlocked(sdw))
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ret = sdw_intel_sync_go_unlocked(sdw);
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mutex_unlock(sdw->link_res->shim_lock);
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if (ret < 0)
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dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
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return ret;
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}
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